// subsys_cam.v

// Generated using ACDS version 18.1 625

`timescale 1 ps / 1 ps
module subsys_cam (
		input  wire         cam_clk_clk,               //   cam_clk.clk
		input  wire         cam_in_vid_clk,            //    cam_in.vid_clk
		input  wire [15:0]  cam_in_vid_data,           //          .vid_data
		input  wire         cam_in_vid_de,             //          .vid_de
		input  wire         cam_in_vid_datavalid,      //          .vid_datavalid
		input  wire         cam_in_vid_locked,         //          .vid_locked
		input  wire         cam_in_vid_f,              //          .vid_f
		input  wire         cam_in_vid_v_sync,         //          .vid_v_sync
		input  wire         cam_in_vid_h_sync,         //          .vid_h_sync
		input  wire         cam_in_vid_hd_sdn,         //          .vid_hd_sdn
		input  wire [7:0]   cam_in_vid_color_encoding, //          .vid_color_encoding
		input  wire [7:0]   cam_in_vid_bit_width,      //          .vid_bit_width
		output wire         cam_in_sof,                //          .sof
		output wire         cam_in_sof_locked,         //          .sof_locked
		output wire         cam_in_refclk_div,         //          .refclk_div
		output wire         cam_in_clipping,           //          .clipping
		output wire         cam_in_padding,            //          .padding
		output wire         cam_in_overflow,           //          .overflow
		output wire         cam_pwdn_export,           //  cam_pwdn.export
		input  wire         cam_reset_reset_n,         // cam_reset.reset_n
		output wire         control_waitrequest,       //   control.waitrequest
		output wire [31:0]  control_readdata,          //          .readdata
		output wire         control_readdatavalid,     //          .readdatavalid
		input  wire [0:0]   control_burstcount,        //          .burstcount
		input  wire [31:0]  control_writedata,         //          .writedata
		input  wire [9:0]   control_address,           //          .address
		input  wire         control_write,             //          .write
		input  wire         control_read,              //          .read
		input  wire [3:0]   control_byteenable,        //          .byteenable
		input  wire         control_debugaccess,       //          .debugaccess
		output wire         interrupt_irq,             // interrupt.irq
		output wire [31:0]  master_wr_address,         // master_wr.address
		output wire [3:0]   master_wr_burstcount,      //          .burstcount
		input  wire         master_wr_waitrequest,     //          .waitrequest
		output wire         master_wr_write,           //          .write
		output wire [255:0] master_wr_writedata,       //          .writedata
		output wire [31:0]  master_wr_byteenable       //          .byteenable
	);

	wire         crs_dout_valid;                              // crs:dout_valid -> csc:din_valid
	wire  [23:0] crs_dout_data;                               // crs:dout_data -> csc:din_data
	wire         crs_dout_ready;                              // csc:din_ready -> crs:dout_ready
	wire         crs_dout_startofpacket;                      // crs:dout_startofpacket -> csc:din_startofpacket
	wire         crs_dout_endofpacket;                        // crs:dout_endofpacket -> csc:din_endofpacket
	wire         csc_dout_valid;                              // csc:dout_valid -> vfb:din_valid
	wire  [23:0] csc_dout_data;                               // csc:dout_data -> vfb:din_data
	wire         csc_dout_ready;                              // vfb:din_ready -> csc:dout_ready
	wire         csc_dout_startofpacket;                      // csc:dout_startofpacket -> vfb:din_startofpacket
	wire         csc_dout_endofpacket;                        // csc:dout_endofpacket -> vfb:din_endofpacket
	wire         scl_dout_valid;                              // scl:dout_valid -> crs:din_valid
	wire  [15:0] scl_dout_data;                               // scl:dout_data -> crs:din_data
	wire         scl_dout_ready;                              // crs:din_ready -> scl:dout_ready
	wire         scl_dout_startofpacket;                      // scl:dout_startofpacket -> crs:din_startofpacket
	wire         scl_dout_endofpacket;                        // scl:dout_endofpacket -> crs:din_endofpacket
	wire         cvi_dout_0_valid;                            // cvi:dout_0_valid -> scl:din_valid
	wire  [15:0] cvi_dout_0_data;                             // cvi:dout_0_data -> scl:din_data
	wire         cvi_dout_0_ready;                            // scl:din_ready -> cvi:dout_0_ready
	wire         cvi_dout_0_startofpacket;                    // cvi:dout_0_startofpacket -> scl:din_startofpacket
	wire         cvi_dout_0_endofpacket;                      // cvi:dout_0_endofpacket -> scl:din_endofpacket
	wire         mm_bridge_0_m0_waitrequest;                  // mm_interconnect_0:mm_bridge_0_m0_waitrequest -> mm_bridge_0:m0_waitrequest
	wire  [31:0] mm_bridge_0_m0_readdata;                     // mm_interconnect_0:mm_bridge_0_m0_readdata -> mm_bridge_0:m0_readdata
	wire         mm_bridge_0_m0_debugaccess;                  // mm_bridge_0:m0_debugaccess -> mm_interconnect_0:mm_bridge_0_m0_debugaccess
	wire   [9:0] mm_bridge_0_m0_address;                      // mm_bridge_0:m0_address -> mm_interconnect_0:mm_bridge_0_m0_address
	wire         mm_bridge_0_m0_read;                         // mm_bridge_0:m0_read -> mm_interconnect_0:mm_bridge_0_m0_read
	wire   [3:0] mm_bridge_0_m0_byteenable;                   // mm_bridge_0:m0_byteenable -> mm_interconnect_0:mm_bridge_0_m0_byteenable
	wire         mm_bridge_0_m0_readdatavalid;                // mm_interconnect_0:mm_bridge_0_m0_readdatavalid -> mm_bridge_0:m0_readdatavalid
	wire  [31:0] mm_bridge_0_m0_writedata;                    // mm_bridge_0:m0_writedata -> mm_interconnect_0:mm_bridge_0_m0_writedata
	wire         mm_bridge_0_m0_write;                        // mm_bridge_0:m0_write -> mm_interconnect_0:mm_bridge_0_m0_write
	wire   [0:0] mm_bridge_0_m0_burstcount;                   // mm_bridge_0:m0_burstcount -> mm_interconnect_0:mm_bridge_0_m0_burstcount
	wire  [31:0] mm_interconnect_0_vfb_control_readdata;      // vfb:control_readdata -> mm_interconnect_0:vfb_control_readdata
	wire         mm_interconnect_0_vfb_control_waitrequest;   // vfb:control_waitrequest -> mm_interconnect_0:vfb_control_waitrequest
	wire   [3:0] mm_interconnect_0_vfb_control_address;       // mm_interconnect_0:vfb_control_address -> vfb:control_address
	wire         mm_interconnect_0_vfb_control_read;          // mm_interconnect_0:vfb_control_read -> vfb:control_read
	wire   [3:0] mm_interconnect_0_vfb_control_byteenable;    // mm_interconnect_0:vfb_control_byteenable -> vfb:control_byteenable
	wire         mm_interconnect_0_vfb_control_readdatavalid; // vfb:control_readdatavalid -> mm_interconnect_0:vfb_control_readdatavalid
	wire         mm_interconnect_0_vfb_control_write;         // mm_interconnect_0:vfb_control_write -> vfb:control_write
	wire  [31:0] mm_interconnect_0_vfb_control_writedata;     // mm_interconnect_0:vfb_control_writedata -> vfb:control_writedata
	wire  [31:0] mm_interconnect_0_scl_control_readdata;      // scl:control_readdata -> mm_interconnect_0:scl_control_readdata
	wire         mm_interconnect_0_scl_control_waitrequest;   // scl:control_waitrequest -> mm_interconnect_0:scl_control_waitrequest
	wire   [6:0] mm_interconnect_0_scl_control_address;       // mm_interconnect_0:scl_control_address -> scl:control_address
	wire         mm_interconnect_0_scl_control_read;          // mm_interconnect_0:scl_control_read -> scl:control_read
	wire   [3:0] mm_interconnect_0_scl_control_byteenable;    // mm_interconnect_0:scl_control_byteenable -> scl:control_byteenable
	wire         mm_interconnect_0_scl_control_readdatavalid; // scl:control_readdatavalid -> mm_interconnect_0:scl_control_readdatavalid
	wire         mm_interconnect_0_scl_control_write;         // mm_interconnect_0:scl_control_write -> scl:control_write
	wire  [31:0] mm_interconnect_0_scl_control_writedata;     // mm_interconnect_0:scl_control_writedata -> scl:control_writedata
	wire         mm_interconnect_0_cam_pwdn_s1_chipselect;    // mm_interconnect_0:cam_pwdn_s1_chipselect -> cam_pwdn:chipselect
	wire  [31:0] mm_interconnect_0_cam_pwdn_s1_readdata;      // cam_pwdn:readdata -> mm_interconnect_0:cam_pwdn_s1_readdata
	wire   [1:0] mm_interconnect_0_cam_pwdn_s1_address;       // mm_interconnect_0:cam_pwdn_s1_address -> cam_pwdn:address
	wire         mm_interconnect_0_cam_pwdn_s1_write;         // mm_interconnect_0:cam_pwdn_s1_write -> cam_pwdn:write_n
	wire  [31:0] mm_interconnect_0_cam_pwdn_s1_writedata;     // mm_interconnect_0:cam_pwdn_s1_writedata -> cam_pwdn:writedata
	wire         rst_controller_reset_out_reset;              // rst_controller:reset_out -> [cam_pwdn:reset_n, crs:main_reset, csc:main_reset, cvi:main_reset_reset, mm_bridge_0:reset, mm_interconnect_0:mm_bridge_0_reset_reset_bridge_in_reset_reset, scl:main_reset, vfb:main_reset]

	subsys_cam_cam_pwdn cam_pwdn (
		.clk        (cam_clk_clk),                              //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),          //               reset.reset_n
		.address    (mm_interconnect_0_cam_pwdn_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_cam_pwdn_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_cam_pwdn_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_cam_pwdn_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_cam_pwdn_s1_readdata),   //                    .readdata
		.out_port   (cam_pwdn_export)                           // external_connection.export
	);

	subsys_cam_crs crs (
		.main_clock         (cam_clk_clk),                    // main_clock.clk
		.main_reset         (rst_controller_reset_out_reset), // main_reset.reset
		.din_data           (scl_dout_data),                  //        din.data
		.din_valid          (scl_dout_valid),                 //           .valid
		.din_startofpacket  (scl_dout_startofpacket),         //           .startofpacket
		.din_endofpacket    (scl_dout_endofpacket),           //           .endofpacket
		.din_ready          (scl_dout_ready),                 //           .ready
		.dout_data          (crs_dout_data),                  //       dout.data
		.dout_valid         (crs_dout_valid),                 //           .valid
		.dout_startofpacket (crs_dout_startofpacket),         //           .startofpacket
		.dout_endofpacket   (crs_dout_endofpacket),           //           .endofpacket
		.dout_ready         (crs_dout_ready)                  //           .ready
	);

	subsys_cam_csc csc (
		.main_clock         (cam_clk_clk),                    // main_clock.clk
		.main_reset         (rst_controller_reset_out_reset), // main_reset.reset
		.din_data           (crs_dout_data),                  //        din.data
		.din_valid          (crs_dout_valid),                 //           .valid
		.din_startofpacket  (crs_dout_startofpacket),         //           .startofpacket
		.din_endofpacket    (crs_dout_endofpacket),           //           .endofpacket
		.din_ready          (crs_dout_ready),                 //           .ready
		.dout_data          (csc_dout_data),                  //       dout.data
		.dout_valid         (csc_dout_valid),                 //           .valid
		.dout_startofpacket (csc_dout_startofpacket),         //           .startofpacket
		.dout_endofpacket   (csc_dout_endofpacket),           //           .endofpacket
		.dout_ready         (csc_dout_ready)                  //           .ready
	);

	subsys_cam_cvi #(
		.BPS                           (8),
		.NUMBER_OF_COLOUR_PLANES       (2),
		.COLOUR_PLANES_ARE_IN_PARALLEL (1),
		.PIXELS_IN_PARALLEL            (1),
		.SYNC_TO                       (2),
		.MATCH_CTRLDATA_PKT_CLIP_BASIC (0),
		.MATCH_CTRLDATA_PKT_PAD_ADV    (0),
		.OVERFLOW_HANDLING             (0),
		.USE_EMBEDDED_SYNCS            (0),
		.USE_HDMI_DEPRICATION          (0),
		.GENERATE_VID_F                (0),
		.USE_STD                       (0),
		.STD_WIDTH                     (1),
		.GENERATE_ANC                  (0),
		.ANC_DEPTH                     (1),
		.EXTRACT_TOTAL_RESOLUTION      (1),
		.INTERLACED                    (0),
		.H_ACTIVE_PIXELS_F0            (640),
		.V_ACTIVE_LINES_F0             (480),
		.V_ACTIVE_LINES_F1             (32),
		.FIFO_DEPTH                    (1024),
		.CLOCKS_ARE_SAME               (0),
		.USE_CONTROL                   (0)
	) cvi (
		.main_clock_clk                   (cam_clk_clk),                    //    main_clock.clk
		.main_reset_reset                 (rst_controller_reset_out_reset), //    main_reset.reset
		.dout_0_data                      (cvi_dout_0_data),                //        dout_0.data
		.dout_0_valid                     (cvi_dout_0_valid),               //              .valid
		.dout_0_startofpacket             (cvi_dout_0_startofpacket),       //              .startofpacket
		.dout_0_endofpacket               (cvi_dout_0_endofpacket),         //              .endofpacket
		.dout_0_ready                     (cvi_dout_0_ready),               //              .ready
		.clocked_video_vid_clk            (cam_in_vid_clk),                 // clocked_video.vid_clk
		.clocked_video_vid_data           (cam_in_vid_data),                //              .vid_data
		.clocked_video_vid_de             (cam_in_vid_de),                  //              .vid_de
		.clocked_video_vid_datavalid      (cam_in_vid_datavalid),           //              .vid_datavalid
		.clocked_video_vid_locked         (cam_in_vid_locked),              //              .vid_locked
		.clocked_video_vid_f              (cam_in_vid_f),                   //              .vid_f
		.clocked_video_vid_v_sync         (cam_in_vid_v_sync),              //              .vid_v_sync
		.clocked_video_vid_h_sync         (cam_in_vid_h_sync),              //              .vid_h_sync
		.clocked_video_vid_hd_sdn         (cam_in_vid_hd_sdn),              //              .vid_hd_sdn
		.clocked_video_vid_color_encoding (cam_in_vid_color_encoding),      //              .vid_color_encoding
		.clocked_video_vid_bit_width      (cam_in_vid_bit_width),           //              .vid_bit_width
		.clocked_video_sof                (cam_in_sof),                     //              .sof
		.clocked_video_sof_locked         (cam_in_sof_locked),              //              .sof_locked
		.clocked_video_refclk_div         (cam_in_refclk_div),              //              .refclk_div
		.clocked_video_clipping           (cam_in_clipping),                //              .clipping
		.clocked_video_padding            (cam_in_padding),                 //              .padding
		.clocked_video_overflow           (cam_in_overflow)                 //              .overflow
	);

	altera_avalon_mm_bridge #(
		.DATA_WIDTH        (32),
		.SYMBOL_WIDTH      (8),
		.HDL_ADDR_WIDTH    (10),
		.BURSTCOUNT_WIDTH  (1),
		.PIPELINE_COMMAND  (1),
		.PIPELINE_RESPONSE (1)
	) mm_bridge_0 (
		.clk              (cam_clk_clk),                    //   clk.clk
		.reset            (rst_controller_reset_out_reset), // reset.reset
		.s0_waitrequest   (control_waitrequest),            //    s0.waitrequest
		.s0_readdata      (control_readdata),               //      .readdata
		.s0_readdatavalid (control_readdatavalid),          //      .readdatavalid
		.s0_burstcount    (control_burstcount),             //      .burstcount
		.s0_writedata     (control_writedata),              //      .writedata
		.s0_address       (control_address),                //      .address
		.s0_write         (control_write),                  //      .write
		.s0_read          (control_read),                   //      .read
		.s0_byteenable    (control_byteenable),             //      .byteenable
		.s0_debugaccess   (control_debugaccess),            //      .debugaccess
		.m0_waitrequest   (mm_bridge_0_m0_waitrequest),     //    m0.waitrequest
		.m0_readdata      (mm_bridge_0_m0_readdata),        //      .readdata
		.m0_readdatavalid (mm_bridge_0_m0_readdatavalid),   //      .readdatavalid
		.m0_burstcount    (mm_bridge_0_m0_burstcount),      //      .burstcount
		.m0_writedata     (mm_bridge_0_m0_writedata),       //      .writedata
		.m0_address       (mm_bridge_0_m0_address),         //      .address
		.m0_write         (mm_bridge_0_m0_write),           //      .write
		.m0_read          (mm_bridge_0_m0_read),            //      .read
		.m0_byteenable    (mm_bridge_0_m0_byteenable),      //      .byteenable
		.m0_debugaccess   (mm_bridge_0_m0_debugaccess),     //      .debugaccess
		.s0_response      (),                               // (terminated)
		.m0_response      (2'b00)                           // (terminated)
	);

	subsys_cam_scl scl (
		.main_clock            (cam_clk_clk),                                 // main_clock.clk
		.main_reset            (rst_controller_reset_out_reset),              // main_reset.reset
		.din_data              (cvi_dout_0_data),                             //        din.data
		.din_valid             (cvi_dout_0_valid),                            //           .valid
		.din_startofpacket     (cvi_dout_0_startofpacket),                    //           .startofpacket
		.din_endofpacket       (cvi_dout_0_endofpacket),                      //           .endofpacket
		.din_ready             (cvi_dout_0_ready),                            //           .ready
		.dout_data             (scl_dout_data),                               //       dout.data
		.dout_valid            (scl_dout_valid),                              //           .valid
		.dout_startofpacket    (scl_dout_startofpacket),                      //           .startofpacket
		.dout_endofpacket      (scl_dout_endofpacket),                        //           .endofpacket
		.dout_ready            (scl_dout_ready),                              //           .ready
		.control_address       (mm_interconnect_0_scl_control_address),       //    control.address
		.control_byteenable    (mm_interconnect_0_scl_control_byteenable),    //           .byteenable
		.control_write         (mm_interconnect_0_scl_control_write),         //           .write
		.control_writedata     (mm_interconnect_0_scl_control_writedata),     //           .writedata
		.control_read          (mm_interconnect_0_scl_control_read),          //           .read
		.control_readdata      (mm_interconnect_0_scl_control_readdata),      //           .readdata
		.control_readdatavalid (mm_interconnect_0_scl_control_readdatavalid), //           .readdatavalid
		.control_waitrequest   (mm_interconnect_0_scl_control_waitrequest)    //           .waitrequest
	);

	subsys_cam_vfb #(
		.BITS_PER_SYMBOL              (8),
		.NUMBER_OF_COLOR_PLANES       (3),
		.COLOR_PLANES_ARE_IN_PARALLEL (1),
		.PIXELS_IN_PARALLEL           (1),
		.READY_LATENCY                (1),
		.MAX_WIDTH                    (1280),
		.MAX_HEIGHT                   (720),
		.CLOCKS_ARE_SEPARATE          (0),
		.MEM_PORT_WIDTH               (256),
		.MEM_BASE_ADDR                (2130706432),
		.BURST_ALIGNMENT              (1),
		.WRITE_FIFO_DEPTH             (16),
		.WRITE_BURST_TARGET           (8),
		.READ_FIFO_DEPTH              (16),
		.READ_BURST_TARGET            (8),
		.WRITER_RUNTIME_CONTROL       (1),
		.READER_RUNTIME_CONTROL       (0),
		.IS_FRAME_WRITER              (1),
		.IS_FRAME_READER              (0),
		.DROP_FRAMES                  (1),
		.REPEAT_FRAMES                (1),
		.DROP_REPEAT_USER             (0),
		.INTERLACED_SUPPORT           (0),
		.CONTROLLED_DROP_REPEAT       (0),
		.DROP_INVALID_FIELDS          (0),
		.MULTI_FRAME_DELAY            (1),
		.IS_SYNC_MASTER               (0),
		.IS_SYNC_SLAVE                (0),
		.LINE_BASED_BUFFERING         (0),
		.PRIORITIZE_FMAX              (0),
		.USER_PACKETS_MAX_STORAGE     (0),
		.MAX_SYMBOLS_PER_PACKET       (10),
		.NUM_BUFFERS                  (3)
	) vfb (
		.main_clock                (cam_clk_clk),                                 //        main_clock.clk
		.main_reset                (rst_controller_reset_out_reset),              //        main_reset.reset
		.din_data                  (csc_dout_data),                               //               din.data
		.din_valid                 (csc_dout_valid),                              //                  .valid
		.din_startofpacket         (csc_dout_startofpacket),                      //                  .startofpacket
		.din_endofpacket           (csc_dout_endofpacket),                        //                  .endofpacket
		.din_ready                 (csc_dout_ready),                              //                  .ready
		.mem_master_wr_address     (master_wr_address),                           //     mem_master_wr.address
		.mem_master_wr_burstcount  (master_wr_burstcount),                        //                  .burstcount
		.mem_master_wr_waitrequest (master_wr_waitrequest),                       //                  .waitrequest
		.mem_master_wr_write       (master_wr_write),                             //                  .write
		.mem_master_wr_writedata   (master_wr_writedata),                         //                  .writedata
		.mem_master_wr_byteenable  (master_wr_byteenable),                        //                  .byteenable
		.control_interrupt_irq     (interrupt_irq),                               // control_interrupt.irq
		.control_address           (mm_interconnect_0_vfb_control_address),       //           control.address
		.control_byteenable        (mm_interconnect_0_vfb_control_byteenable),    //                  .byteenable
		.control_write             (mm_interconnect_0_vfb_control_write),         //                  .write
		.control_writedata         (mm_interconnect_0_vfb_control_writedata),     //                  .writedata
		.control_read              (mm_interconnect_0_vfb_control_read),          //                  .read
		.control_readdata          (mm_interconnect_0_vfb_control_readdata),      //                  .readdata
		.control_readdatavalid     (mm_interconnect_0_vfb_control_readdatavalid), //                  .readdatavalid
		.control_waitrequest       (mm_interconnect_0_vfb_control_waitrequest)    //                  .waitrequest
	);

	subsys_cam_mm_interconnect_0 mm_interconnect_0 (
		.clk_0_clk_clk                                 (cam_clk_clk),                                 //                               clk_0_clk.clk
		.mm_bridge_0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset),              // mm_bridge_0_reset_reset_bridge_in_reset.reset
		.mm_bridge_0_m0_address                        (mm_bridge_0_m0_address),                      //                          mm_bridge_0_m0.address
		.mm_bridge_0_m0_waitrequest                    (mm_bridge_0_m0_waitrequest),                  //                                        .waitrequest
		.mm_bridge_0_m0_burstcount                     (mm_bridge_0_m0_burstcount),                   //                                        .burstcount
		.mm_bridge_0_m0_byteenable                     (mm_bridge_0_m0_byteenable),                   //                                        .byteenable
		.mm_bridge_0_m0_read                           (mm_bridge_0_m0_read),                         //                                        .read
		.mm_bridge_0_m0_readdata                       (mm_bridge_0_m0_readdata),                     //                                        .readdata
		.mm_bridge_0_m0_readdatavalid                  (mm_bridge_0_m0_readdatavalid),                //                                        .readdatavalid
		.mm_bridge_0_m0_write                          (mm_bridge_0_m0_write),                        //                                        .write
		.mm_bridge_0_m0_writedata                      (mm_bridge_0_m0_writedata),                    //                                        .writedata
		.mm_bridge_0_m0_debugaccess                    (mm_bridge_0_m0_debugaccess),                  //                                        .debugaccess
		.cam_pwdn_s1_address                           (mm_interconnect_0_cam_pwdn_s1_address),       //                             cam_pwdn_s1.address
		.cam_pwdn_s1_write                             (mm_interconnect_0_cam_pwdn_s1_write),         //                                        .write
		.cam_pwdn_s1_readdata                          (mm_interconnect_0_cam_pwdn_s1_readdata),      //                                        .readdata
		.cam_pwdn_s1_writedata                         (mm_interconnect_0_cam_pwdn_s1_writedata),     //                                        .writedata
		.cam_pwdn_s1_chipselect                        (mm_interconnect_0_cam_pwdn_s1_chipselect),    //                                        .chipselect
		.scl_control_address                           (mm_interconnect_0_scl_control_address),       //                             scl_control.address
		.scl_control_write                             (mm_interconnect_0_scl_control_write),         //                                        .write
		.scl_control_read                              (mm_interconnect_0_scl_control_read),          //                                        .read
		.scl_control_readdata                          (mm_interconnect_0_scl_control_readdata),      //                                        .readdata
		.scl_control_writedata                         (mm_interconnect_0_scl_control_writedata),     //                                        .writedata
		.scl_control_byteenable                        (mm_interconnect_0_scl_control_byteenable),    //                                        .byteenable
		.scl_control_readdatavalid                     (mm_interconnect_0_scl_control_readdatavalid), //                                        .readdatavalid
		.scl_control_waitrequest                       (mm_interconnect_0_scl_control_waitrequest),   //                                        .waitrequest
		.vfb_control_address                           (mm_interconnect_0_vfb_control_address),       //                             vfb_control.address
		.vfb_control_write                             (mm_interconnect_0_vfb_control_write),         //                                        .write
		.vfb_control_read                              (mm_interconnect_0_vfb_control_read),          //                                        .read
		.vfb_control_readdata                          (mm_interconnect_0_vfb_control_readdata),      //                                        .readdata
		.vfb_control_writedata                         (mm_interconnect_0_vfb_control_writedata),     //                                        .writedata
		.vfb_control_byteenable                        (mm_interconnect_0_vfb_control_byteenable),    //                                        .byteenable
		.vfb_control_readdatavalid                     (mm_interconnect_0_vfb_control_readdatavalid), //                                        .readdatavalid
		.vfb_control_waitrequest                       (mm_interconnect_0_vfb_control_waitrequest)    //                                        .waitrequest
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (~cam_reset_reset_n),             // reset_in0.reset
		.clk            (cam_clk_clk),                    //       clk.clk
		.reset_out      (rst_controller_reset_out_reset), // reset_out.reset
		.reset_req      (),                               // (terminated)
		.reset_req_in0  (1'b0),                           // (terminated)
		.reset_in1      (1'b0),                           // (terminated)
		.reset_req_in1  (1'b0),                           // (terminated)
		.reset_in2      (1'b0),                           // (terminated)
		.reset_req_in2  (1'b0),                           // (terminated)
		.reset_in3      (1'b0),                           // (terminated)
		.reset_req_in3  (1'b0),                           // (terminated)
		.reset_in4      (1'b0),                           // (terminated)
		.reset_req_in4  (1'b0),                           // (terminated)
		.reset_in5      (1'b0),                           // (terminated)
		.reset_req_in5  (1'b0),                           // (terminated)
		.reset_in6      (1'b0),                           // (terminated)
		.reset_req_in6  (1'b0),                           // (terminated)
		.reset_in7      (1'b0),                           // (terminated)
		.reset_req_in7  (1'b0),                           // (terminated)
		.reset_in8      (1'b0),                           // (terminated)
		.reset_req_in8  (1'b0),                           // (terminated)
		.reset_in9      (1'b0),                           // (terminated)
		.reset_req_in9  (1'b0),                           // (terminated)
		.reset_in10     (1'b0),                           // (terminated)
		.reset_req_in10 (1'b0),                           // (terminated)
		.reset_in11     (1'b0),                           // (terminated)
		.reset_req_in11 (1'b0),                           // (terminated)
		.reset_in12     (1'b0),                           // (terminated)
		.reset_req_in12 (1'b0),                           // (terminated)
		.reset_in13     (1'b0),                           // (terminated)
		.reset_req_in13 (1'b0),                           // (terminated)
		.reset_in14     (1'b0),                           // (terminated)
		.reset_req_in14 (1'b0),                           // (terminated)
		.reset_in15     (1'b0),                           // (terminated)
		.reset_req_in15 (1'b0)                            // (terminated)
	);

endmodule
