datasheet for subsys_vid

subsys_vid |

2020.06.26.14:45:24 | Datasheet

Overview

vip_clk | subsys_vid

All Components
vfr alt_vip_cl_vfb 18.1
Memory Map

| vfr
mem_master_rd
vfr |
control |

## cvo

alt_vip_cl_cvo v18.1

vfr | dout | cvo
din
vip_clk | clk
main_clock
clk_reset
main_reset

## Parameters

BPS | 8
NUMBER_OF_COLOUR_PLANES | 4
COLOUR_PLANES_ARE_IN_PARALLEL | 1
INTERLACED | 0
H_ACTIVE_PIXELS | 1280
V_ACTIVE_LINES | 720
ACCEPT_COLOURS_IN_SEQ | 0
FIFO_DEPTH | 1280
CLOCKS_ARE_SAME | 0
USE_CONTROL | 0
NO_OF_MODES | 1
THRESHOLD | 1279
STD_WIDTH | 1
GENERATE_SYNC | 0
ACCEPT_SYNC | 0
COUNT_STEP_IS_PIP_VALUE | 0
LOW_LATENCY | 0
USE_EMBEDDED_SYNCS | 0
AP_LINE | 0
V_BLANK | 0
H_BLANK | 0
H_SYNC_LENGTH | 46
H_FRONT_PORCH | 110
H_BACK_PORCH | 220
V_SYNC_LENGTH | 5
V_FRONT_PORCH | 5
V_BACK_PORCH | 20
F_RISING_EDGE | 0
F_FALLING_EDGE | 0
FIELD0_V_RISING_EDGE | 0
FIELD0_V_BLANK | 0
FIELD0_V_SYNC_LENGTH | 0
FIELD0_V_FRONT_PORCH | 0
FIELD0_V_BACK_PORCH | 0
ANC_LINE | 0
FIELD0_ANC_LINE | 0
PIXELS_IN_PARALLEL | 1
NO_OF_CHANNELS | 1
SRC_WIDTH | 8
DST_WIDTH | 8
CONTEXT_WIDTH | 8
TASK_WIDTH | 8
AUTO_DEVICE_FAMILY | CYCLONEV
AUTO_DEVICE | 5CSXFC6C6U23I7
AUTO_DEVICE_SPEEDGRADE | 7_H6
deviceFamily | Cyclone V
generateLegacySim | false

## Software Assignments

(none)

## vfr

alt_vip_cl_vfb v18.1

vip_clk | clk | vfr
main_clock
clk_reset
main_reset
|  | dout | cvo
|  | din

## Parameters

BITS_PER_SYMBOL | 8
NUMBER_OF_COLOR_PLANES | 4
COLOR_PLANES_ARE_IN_PARALLEL | 1
PIXELS_IN_PARALLEL | 1
READY_LATENCY | 1
MAX_WIDTH | 1280
MAX_HEIGHT | 720
CLOCKS_ARE_SEPARATE | 0
MEM_PORT_WIDTH | 256
MEM_BASE_ADDR | 0
USE_BUFFER_OFFSET | 0
MEM_BUFFER_OFFSET | 16777216
BURST_ALIGNMENT | 1
WRITE_FIFO_DEPTH | 32
WRITE_BURST_TARGET | 16
READ_FIFO_DEPTH | 32
READ_BURST_TARGET | 16
WRITER_RUNTIME_CONTROL | 0
READER_RUNTIME_CONTROL | 1
IS_FRAME_WRITER | 0
IS_FRAME_READER | 1
DROP_FRAMES | 1
REPEAT_FRAMES | 1
DROP_REPEAT_USER | 0
INTERLACED_SUPPORT | 0
CONTROLLED_DROP_REPEAT | 0
DROP_INVALID_FIELDS | 1
MULTI_FRAME_DELAY | 1
IS_SYNC_MASTER | 0
IS_SYNC_SLAVE | 0
LINE_BASED_BUFFERING | 0
PRIORITIZE_FMAX | 0
USER_PACKETS_MAX_STORAGE | 0
MAX_SYMBOLS_PER_PACKET | 10
TEST_INIT | 0
ANC_BUFFER_LENGTH | 512
ACTUAL_MAX_SYM_ANC_PACKET | 12
FRAME_BUFFER_LENGTH | 3686400
NUM_BUFFERS | 3
FAMILY | CYCLONEV
AUTO_DEVICE | 5CSXFC6C6U23I7
AUTO_DEVICE_SPEEDGRADE | 7_H6
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## vip_clk

clock_source v18.1

## Parameters

clockFrequency | 74250000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

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