// soc_system_mm_interconnect_2.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 18.1 646

`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_2 (
		input  wire [11:0] hps_0_h2f_lw_axi_master_awid,                                        //                                       hps_0_h2f_lw_axi_master.awid
		input  wire [20:0] hps_0_h2f_lw_axi_master_awaddr,                                      //                                                              .awaddr
		input  wire [3:0]  hps_0_h2f_lw_axi_master_awlen,                                       //                                                              .awlen
		input  wire [2:0]  hps_0_h2f_lw_axi_master_awsize,                                      //                                                              .awsize
		input  wire [1:0]  hps_0_h2f_lw_axi_master_awburst,                                     //                                                              .awburst
		input  wire [1:0]  hps_0_h2f_lw_axi_master_awlock,                                      //                                                              .awlock
		input  wire [3:0]  hps_0_h2f_lw_axi_master_awcache,                                     //                                                              .awcache
		input  wire [2:0]  hps_0_h2f_lw_axi_master_awprot,                                      //                                                              .awprot
		input  wire        hps_0_h2f_lw_axi_master_awvalid,                                     //                                                              .awvalid
		output wire        hps_0_h2f_lw_axi_master_awready,                                     //                                                              .awready
		input  wire [11:0] hps_0_h2f_lw_axi_master_wid,                                         //                                                              .wid
		input  wire [31:0] hps_0_h2f_lw_axi_master_wdata,                                       //                                                              .wdata
		input  wire [3:0]  hps_0_h2f_lw_axi_master_wstrb,                                       //                                                              .wstrb
		input  wire        hps_0_h2f_lw_axi_master_wlast,                                       //                                                              .wlast
		input  wire        hps_0_h2f_lw_axi_master_wvalid,                                      //                                                              .wvalid
		output wire        hps_0_h2f_lw_axi_master_wready,                                      //                                                              .wready
		output wire [11:0] hps_0_h2f_lw_axi_master_bid,                                         //                                                              .bid
		output wire [1:0]  hps_0_h2f_lw_axi_master_bresp,                                       //                                                              .bresp
		output wire        hps_0_h2f_lw_axi_master_bvalid,                                      //                                                              .bvalid
		input  wire        hps_0_h2f_lw_axi_master_bready,                                      //                                                              .bready
		input  wire [11:0] hps_0_h2f_lw_axi_master_arid,                                        //                                                              .arid
		input  wire [20:0] hps_0_h2f_lw_axi_master_araddr,                                      //                                                              .araddr
		input  wire [3:0]  hps_0_h2f_lw_axi_master_arlen,                                       //                                                              .arlen
		input  wire [2:0]  hps_0_h2f_lw_axi_master_arsize,                                      //                                                              .arsize
		input  wire [1:0]  hps_0_h2f_lw_axi_master_arburst,                                     //                                                              .arburst
		input  wire [1:0]  hps_0_h2f_lw_axi_master_arlock,                                      //                                                              .arlock
		input  wire [3:0]  hps_0_h2f_lw_axi_master_arcache,                                     //                                                              .arcache
		input  wire [2:0]  hps_0_h2f_lw_axi_master_arprot,                                      //                                                              .arprot
		input  wire        hps_0_h2f_lw_axi_master_arvalid,                                     //                                                              .arvalid
		output wire        hps_0_h2f_lw_axi_master_arready,                                     //                                                              .arready
		output wire [11:0] hps_0_h2f_lw_axi_master_rid,                                         //                                                              .rid
		output wire [31:0] hps_0_h2f_lw_axi_master_rdata,                                       //                                                              .rdata
		output wire [1:0]  hps_0_h2f_lw_axi_master_rresp,                                       //                                                              .rresp
		output wire        hps_0_h2f_lw_axi_master_rlast,                                       //                                                              .rlast
		output wire        hps_0_h2f_lw_axi_master_rvalid,                                      //                                                              .rvalid
		input  wire        hps_0_h2f_lw_axi_master_rready,                                      //                                                              .rready
		input  wire        clk_0_clk_clk,                                                       //                                                     clk_0_clk.clk
		input  wire        fpga_only_master_clk_reset_reset_bridge_in_reset_reset,              //              fpga_only_master_clk_reset_reset_bridge_in_reset.reset
		input  wire        hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, // hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
		input  wire        mm_bridge_0_reset_reset_bridge_in_reset_reset,                       //                       mm_bridge_0_reset_reset_bridge_in_reset.reset
		input  wire [31:0] fpga_only_master_master_address,                                     //                                       fpga_only_master_master.address
		output wire        fpga_only_master_master_waitrequest,                                 //                                                              .waitrequest
		input  wire [3:0]  fpga_only_master_master_byteenable,                                  //                                                              .byteenable
		input  wire        fpga_only_master_master_read,                                        //                                                              .read
		output wire [31:0] fpga_only_master_master_readdata,                                    //                                                              .readdata
		output wire        fpga_only_master_master_readdatavalid,                               //                                                              .readdatavalid
		input  wire        fpga_only_master_master_write,                                       //                                                              .write
		input  wire [31:0] fpga_only_master_master_writedata,                                   //                                                              .writedata
		input  wire [31:0] sys_console_mst_master_address,                                      //                                        sys_console_mst_master.address
		output wire        sys_console_mst_master_waitrequest,                                  //                                                              .waitrequest
		input  wire [3:0]  sys_console_mst_master_byteenable,                                   //                                                              .byteenable
		input  wire        sys_console_mst_master_read,                                         //                                                              .read
		output wire [31:0] sys_console_mst_master_readdata,                                     //                                                              .readdata
		output wire        sys_console_mst_master_readdatavalid,                                //                                                              .readdatavalid
		input  wire        sys_console_mst_master_write,                                        //                                                              .write
		input  wire [31:0] sys_console_mst_master_writedata,                                    //                                                              .writedata
		output wire [18:0] mm_bridge_0_s0_address,                                              //                                                mm_bridge_0_s0.address
		output wire        mm_bridge_0_s0_write,                                                //                                                              .write
		output wire        mm_bridge_0_s0_read,                                                 //                                                              .read
		input  wire [31:0] mm_bridge_0_s0_readdata,                                             //                                                              .readdata
		output wire [31:0] mm_bridge_0_s0_writedata,                                            //                                                              .writedata
		output wire [0:0]  mm_bridge_0_s0_burstcount,                                           //                                                              .burstcount
		output wire [3:0]  mm_bridge_0_s0_byteenable,                                           //                                                              .byteenable
		input  wire        mm_bridge_0_s0_readdatavalid,                                        //                                                              .readdatavalid
		input  wire        mm_bridge_0_s0_waitrequest,                                          //                                                              .waitrequest
		output wire        mm_bridge_0_s0_debugaccess                                           //                                                              .debugaccess
	);

	wire          rsp_mux_src_valid;                                                          // rsp_mux:src_valid -> hps_0_h2f_lw_axi_master_agent:write_rp_valid
	wire  [124:0] rsp_mux_src_data;                                                           // rsp_mux:src_data -> hps_0_h2f_lw_axi_master_agent:write_rp_data
	wire          rsp_mux_src_ready;                                                          // hps_0_h2f_lw_axi_master_agent:write_rp_ready -> rsp_mux:src_ready
	wire    [3:0] rsp_mux_src_channel;                                                        // rsp_mux:src_channel -> hps_0_h2f_lw_axi_master_agent:write_rp_channel
	wire          rsp_mux_src_startofpacket;                                                  // rsp_mux:src_startofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_startofpacket
	wire          rsp_mux_src_endofpacket;                                                    // rsp_mux:src_endofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_endofpacket
	wire          rsp_mux_001_src_valid;                                                      // rsp_mux_001:src_valid -> hps_0_h2f_lw_axi_master_agent:read_rp_valid
	wire  [124:0] rsp_mux_001_src_data;                                                       // rsp_mux_001:src_data -> hps_0_h2f_lw_axi_master_agent:read_rp_data
	wire          rsp_mux_001_src_ready;                                                      // hps_0_h2f_lw_axi_master_agent:read_rp_ready -> rsp_mux_001:src_ready
	wire    [3:0] rsp_mux_001_src_channel;                                                    // rsp_mux_001:src_channel -> hps_0_h2f_lw_axi_master_agent:read_rp_channel
	wire          rsp_mux_001_src_startofpacket;                                              // rsp_mux_001:src_startofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_startofpacket
	wire          rsp_mux_001_src_endofpacket;                                                // rsp_mux_001:src_endofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_endofpacket
	wire          fpga_only_master_master_translator_avalon_universal_master_0_waitrequest;   // fpga_only_master_master_agent:av_waitrequest -> fpga_only_master_master_translator:uav_waitrequest
	wire   [31:0] fpga_only_master_master_translator_avalon_universal_master_0_readdata;      // fpga_only_master_master_agent:av_readdata -> fpga_only_master_master_translator:uav_readdata
	wire          fpga_only_master_master_translator_avalon_universal_master_0_debugaccess;   // fpga_only_master_master_translator:uav_debugaccess -> fpga_only_master_master_agent:av_debugaccess
	wire   [31:0] fpga_only_master_master_translator_avalon_universal_master_0_address;       // fpga_only_master_master_translator:uav_address -> fpga_only_master_master_agent:av_address
	wire          fpga_only_master_master_translator_avalon_universal_master_0_read;          // fpga_only_master_master_translator:uav_read -> fpga_only_master_master_agent:av_read
	wire    [3:0] fpga_only_master_master_translator_avalon_universal_master_0_byteenable;    // fpga_only_master_master_translator:uav_byteenable -> fpga_only_master_master_agent:av_byteenable
	wire          fpga_only_master_master_translator_avalon_universal_master_0_readdatavalid; // fpga_only_master_master_agent:av_readdatavalid -> fpga_only_master_master_translator:uav_readdatavalid
	wire          fpga_only_master_master_translator_avalon_universal_master_0_lock;          // fpga_only_master_master_translator:uav_lock -> fpga_only_master_master_agent:av_lock
	wire          fpga_only_master_master_translator_avalon_universal_master_0_write;         // fpga_only_master_master_translator:uav_write -> fpga_only_master_master_agent:av_write
	wire   [31:0] fpga_only_master_master_translator_avalon_universal_master_0_writedata;     // fpga_only_master_master_translator:uav_writedata -> fpga_only_master_master_agent:av_writedata
	wire    [2:0] fpga_only_master_master_translator_avalon_universal_master_0_burstcount;    // fpga_only_master_master_translator:uav_burstcount -> fpga_only_master_master_agent:av_burstcount
	wire          rsp_mux_002_src_valid;                                                      // rsp_mux_002:src_valid -> fpga_only_master_master_agent:rp_valid
	wire  [124:0] rsp_mux_002_src_data;                                                       // rsp_mux_002:src_data -> fpga_only_master_master_agent:rp_data
	wire          rsp_mux_002_src_ready;                                                      // fpga_only_master_master_agent:rp_ready -> rsp_mux_002:src_ready
	wire    [3:0] rsp_mux_002_src_channel;                                                    // rsp_mux_002:src_channel -> fpga_only_master_master_agent:rp_channel
	wire          rsp_mux_002_src_startofpacket;                                              // rsp_mux_002:src_startofpacket -> fpga_only_master_master_agent:rp_startofpacket
	wire          rsp_mux_002_src_endofpacket;                                                // rsp_mux_002:src_endofpacket -> fpga_only_master_master_agent:rp_endofpacket
	wire          sys_console_mst_master_translator_avalon_universal_master_0_waitrequest;    // sys_console_mst_master_agent:av_waitrequest -> sys_console_mst_master_translator:uav_waitrequest
	wire   [31:0] sys_console_mst_master_translator_avalon_universal_master_0_readdata;       // sys_console_mst_master_agent:av_readdata -> sys_console_mst_master_translator:uav_readdata
	wire          sys_console_mst_master_translator_avalon_universal_master_0_debugaccess;    // sys_console_mst_master_translator:uav_debugaccess -> sys_console_mst_master_agent:av_debugaccess
	wire   [31:0] sys_console_mst_master_translator_avalon_universal_master_0_address;        // sys_console_mst_master_translator:uav_address -> sys_console_mst_master_agent:av_address
	wire          sys_console_mst_master_translator_avalon_universal_master_0_read;           // sys_console_mst_master_translator:uav_read -> sys_console_mst_master_agent:av_read
	wire    [3:0] sys_console_mst_master_translator_avalon_universal_master_0_byteenable;     // sys_console_mst_master_translator:uav_byteenable -> sys_console_mst_master_agent:av_byteenable
	wire          sys_console_mst_master_translator_avalon_universal_master_0_readdatavalid;  // sys_console_mst_master_agent:av_readdatavalid -> sys_console_mst_master_translator:uav_readdatavalid
	wire          sys_console_mst_master_translator_avalon_universal_master_0_lock;           // sys_console_mst_master_translator:uav_lock -> sys_console_mst_master_agent:av_lock
	wire          sys_console_mst_master_translator_avalon_universal_master_0_write;          // sys_console_mst_master_translator:uav_write -> sys_console_mst_master_agent:av_write
	wire   [31:0] sys_console_mst_master_translator_avalon_universal_master_0_writedata;      // sys_console_mst_master_translator:uav_writedata -> sys_console_mst_master_agent:av_writedata
	wire    [2:0] sys_console_mst_master_translator_avalon_universal_master_0_burstcount;     // sys_console_mst_master_translator:uav_burstcount -> sys_console_mst_master_agent:av_burstcount
	wire          rsp_mux_003_src_valid;                                                      // rsp_mux_003:src_valid -> sys_console_mst_master_agent:rp_valid
	wire  [124:0] rsp_mux_003_src_data;                                                       // rsp_mux_003:src_data -> sys_console_mst_master_agent:rp_data
	wire          rsp_mux_003_src_ready;                                                      // sys_console_mst_master_agent:rp_ready -> rsp_mux_003:src_ready
	wire    [3:0] rsp_mux_003_src_channel;                                                    // rsp_mux_003:src_channel -> sys_console_mst_master_agent:rp_channel
	wire          rsp_mux_003_src_startofpacket;                                              // rsp_mux_003:src_startofpacket -> sys_console_mst_master_agent:rp_startofpacket
	wire          rsp_mux_003_src_endofpacket;                                                // rsp_mux_003:src_endofpacket -> sys_console_mst_master_agent:rp_endofpacket
	wire   [31:0] mm_bridge_0_s0_agent_m0_readdata;                                           // mm_bridge_0_s0_translator:uav_readdata -> mm_bridge_0_s0_agent:m0_readdata
	wire          mm_bridge_0_s0_agent_m0_waitrequest;                                        // mm_bridge_0_s0_translator:uav_waitrequest -> mm_bridge_0_s0_agent:m0_waitrequest
	wire          mm_bridge_0_s0_agent_m0_debugaccess;                                        // mm_bridge_0_s0_agent:m0_debugaccess -> mm_bridge_0_s0_translator:uav_debugaccess
	wire   [31:0] mm_bridge_0_s0_agent_m0_address;                                            // mm_bridge_0_s0_agent:m0_address -> mm_bridge_0_s0_translator:uav_address
	wire    [3:0] mm_bridge_0_s0_agent_m0_byteenable;                                         // mm_bridge_0_s0_agent:m0_byteenable -> mm_bridge_0_s0_translator:uav_byteenable
	wire          mm_bridge_0_s0_agent_m0_read;                                               // mm_bridge_0_s0_agent:m0_read -> mm_bridge_0_s0_translator:uav_read
	wire          mm_bridge_0_s0_agent_m0_readdatavalid;                                      // mm_bridge_0_s0_translator:uav_readdatavalid -> mm_bridge_0_s0_agent:m0_readdatavalid
	wire          mm_bridge_0_s0_agent_m0_lock;                                               // mm_bridge_0_s0_agent:m0_lock -> mm_bridge_0_s0_translator:uav_lock
	wire   [31:0] mm_bridge_0_s0_agent_m0_writedata;                                          // mm_bridge_0_s0_agent:m0_writedata -> mm_bridge_0_s0_translator:uav_writedata
	wire          mm_bridge_0_s0_agent_m0_write;                                              // mm_bridge_0_s0_agent:m0_write -> mm_bridge_0_s0_translator:uav_write
	wire    [2:0] mm_bridge_0_s0_agent_m0_burstcount;                                         // mm_bridge_0_s0_agent:m0_burstcount -> mm_bridge_0_s0_translator:uav_burstcount
	wire          mm_bridge_0_s0_agent_rf_source_valid;                                       // mm_bridge_0_s0_agent:rf_source_valid -> mm_bridge_0_s0_agent_rsp_fifo:in_valid
	wire  [125:0] mm_bridge_0_s0_agent_rf_source_data;                                        // mm_bridge_0_s0_agent:rf_source_data -> mm_bridge_0_s0_agent_rsp_fifo:in_data
	wire          mm_bridge_0_s0_agent_rf_source_ready;                                       // mm_bridge_0_s0_agent_rsp_fifo:in_ready -> mm_bridge_0_s0_agent:rf_source_ready
	wire          mm_bridge_0_s0_agent_rf_source_startofpacket;                               // mm_bridge_0_s0_agent:rf_source_startofpacket -> mm_bridge_0_s0_agent_rsp_fifo:in_startofpacket
	wire          mm_bridge_0_s0_agent_rf_source_endofpacket;                                 // mm_bridge_0_s0_agent:rf_source_endofpacket -> mm_bridge_0_s0_agent_rsp_fifo:in_endofpacket
	wire          mm_bridge_0_s0_agent_rsp_fifo_out_valid;                                    // mm_bridge_0_s0_agent_rsp_fifo:out_valid -> mm_bridge_0_s0_agent:rf_sink_valid
	wire  [125:0] mm_bridge_0_s0_agent_rsp_fifo_out_data;                                     // mm_bridge_0_s0_agent_rsp_fifo:out_data -> mm_bridge_0_s0_agent:rf_sink_data
	wire          mm_bridge_0_s0_agent_rsp_fifo_out_ready;                                    // mm_bridge_0_s0_agent:rf_sink_ready -> mm_bridge_0_s0_agent_rsp_fifo:out_ready
	wire          mm_bridge_0_s0_agent_rsp_fifo_out_startofpacket;                            // mm_bridge_0_s0_agent_rsp_fifo:out_startofpacket -> mm_bridge_0_s0_agent:rf_sink_startofpacket
	wire          mm_bridge_0_s0_agent_rsp_fifo_out_endofpacket;                              // mm_bridge_0_s0_agent_rsp_fifo:out_endofpacket -> mm_bridge_0_s0_agent:rf_sink_endofpacket
	wire          mm_bridge_0_s0_agent_rdata_fifo_src_valid;                                  // mm_bridge_0_s0_agent:rdata_fifo_src_valid -> mm_bridge_0_s0_agent_rdata_fifo:in_valid
	wire   [33:0] mm_bridge_0_s0_agent_rdata_fifo_src_data;                                   // mm_bridge_0_s0_agent:rdata_fifo_src_data -> mm_bridge_0_s0_agent_rdata_fifo:in_data
	wire          mm_bridge_0_s0_agent_rdata_fifo_src_ready;                                  // mm_bridge_0_s0_agent_rdata_fifo:in_ready -> mm_bridge_0_s0_agent:rdata_fifo_src_ready
	wire          hps_0_h2f_lw_axi_master_agent_write_cp_valid;                               // hps_0_h2f_lw_axi_master_agent:write_cp_valid -> router:sink_valid
	wire  [124:0] hps_0_h2f_lw_axi_master_agent_write_cp_data;                                // hps_0_h2f_lw_axi_master_agent:write_cp_data -> router:sink_data
	wire          hps_0_h2f_lw_axi_master_agent_write_cp_ready;                               // router:sink_ready -> hps_0_h2f_lw_axi_master_agent:write_cp_ready
	wire          hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket;                       // hps_0_h2f_lw_axi_master_agent:write_cp_startofpacket -> router:sink_startofpacket
	wire          hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket;                         // hps_0_h2f_lw_axi_master_agent:write_cp_endofpacket -> router:sink_endofpacket
	wire          router_src_valid;                                                           // router:src_valid -> cmd_demux:sink_valid
	wire  [124:0] router_src_data;                                                            // router:src_data -> cmd_demux:sink_data
	wire          router_src_ready;                                                           // cmd_demux:sink_ready -> router:src_ready
	wire    [3:0] router_src_channel;                                                         // router:src_channel -> cmd_demux:sink_channel
	wire          router_src_startofpacket;                                                   // router:src_startofpacket -> cmd_demux:sink_startofpacket
	wire          router_src_endofpacket;                                                     // router:src_endofpacket -> cmd_demux:sink_endofpacket
	wire          hps_0_h2f_lw_axi_master_agent_read_cp_valid;                                // hps_0_h2f_lw_axi_master_agent:read_cp_valid -> router_001:sink_valid
	wire  [124:0] hps_0_h2f_lw_axi_master_agent_read_cp_data;                                 // hps_0_h2f_lw_axi_master_agent:read_cp_data -> router_001:sink_data
	wire          hps_0_h2f_lw_axi_master_agent_read_cp_ready;                                // router_001:sink_ready -> hps_0_h2f_lw_axi_master_agent:read_cp_ready
	wire          hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket;                        // hps_0_h2f_lw_axi_master_agent:read_cp_startofpacket -> router_001:sink_startofpacket
	wire          hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket;                          // hps_0_h2f_lw_axi_master_agent:read_cp_endofpacket -> router_001:sink_endofpacket
	wire          router_001_src_valid;                                                       // router_001:src_valid -> cmd_demux_001:sink_valid
	wire  [124:0] router_001_src_data;                                                        // router_001:src_data -> cmd_demux_001:sink_data
	wire          router_001_src_ready;                                                       // cmd_demux_001:sink_ready -> router_001:src_ready
	wire    [3:0] router_001_src_channel;                                                     // router_001:src_channel -> cmd_demux_001:sink_channel
	wire          router_001_src_startofpacket;                                               // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
	wire          router_001_src_endofpacket;                                                 // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
	wire          fpga_only_master_master_agent_cp_valid;                                     // fpga_only_master_master_agent:cp_valid -> router_002:sink_valid
	wire  [124:0] fpga_only_master_master_agent_cp_data;                                      // fpga_only_master_master_agent:cp_data -> router_002:sink_data
	wire          fpga_only_master_master_agent_cp_ready;                                     // router_002:sink_ready -> fpga_only_master_master_agent:cp_ready
	wire          fpga_only_master_master_agent_cp_startofpacket;                             // fpga_only_master_master_agent:cp_startofpacket -> router_002:sink_startofpacket
	wire          fpga_only_master_master_agent_cp_endofpacket;                               // fpga_only_master_master_agent:cp_endofpacket -> router_002:sink_endofpacket
	wire          router_002_src_valid;                                                       // router_002:src_valid -> cmd_demux_002:sink_valid
	wire  [124:0] router_002_src_data;                                                        // router_002:src_data -> cmd_demux_002:sink_data
	wire          router_002_src_ready;                                                       // cmd_demux_002:sink_ready -> router_002:src_ready
	wire    [3:0] router_002_src_channel;                                                     // router_002:src_channel -> cmd_demux_002:sink_channel
	wire          router_002_src_startofpacket;                                               // router_002:src_startofpacket -> cmd_demux_002:sink_startofpacket
	wire          router_002_src_endofpacket;                                                 // router_002:src_endofpacket -> cmd_demux_002:sink_endofpacket
	wire          sys_console_mst_master_agent_cp_valid;                                      // sys_console_mst_master_agent:cp_valid -> router_003:sink_valid
	wire  [124:0] sys_console_mst_master_agent_cp_data;                                       // sys_console_mst_master_agent:cp_data -> router_003:sink_data
	wire          sys_console_mst_master_agent_cp_ready;                                      // router_003:sink_ready -> sys_console_mst_master_agent:cp_ready
	wire          sys_console_mst_master_agent_cp_startofpacket;                              // sys_console_mst_master_agent:cp_startofpacket -> router_003:sink_startofpacket
	wire          sys_console_mst_master_agent_cp_endofpacket;                                // sys_console_mst_master_agent:cp_endofpacket -> router_003:sink_endofpacket
	wire          router_003_src_valid;                                                       // router_003:src_valid -> cmd_demux_003:sink_valid
	wire  [124:0] router_003_src_data;                                                        // router_003:src_data -> cmd_demux_003:sink_data
	wire          router_003_src_ready;                                                       // cmd_demux_003:sink_ready -> router_003:src_ready
	wire    [3:0] router_003_src_channel;                                                     // router_003:src_channel -> cmd_demux_003:sink_channel
	wire          router_003_src_startofpacket;                                               // router_003:src_startofpacket -> cmd_demux_003:sink_startofpacket
	wire          router_003_src_endofpacket;                                                 // router_003:src_endofpacket -> cmd_demux_003:sink_endofpacket
	wire          mm_bridge_0_s0_agent_rp_valid;                                              // mm_bridge_0_s0_agent:rp_valid -> router_004:sink_valid
	wire  [124:0] mm_bridge_0_s0_agent_rp_data;                                               // mm_bridge_0_s0_agent:rp_data -> router_004:sink_data
	wire          mm_bridge_0_s0_agent_rp_ready;                                              // router_004:sink_ready -> mm_bridge_0_s0_agent:rp_ready
	wire          mm_bridge_0_s0_agent_rp_startofpacket;                                      // mm_bridge_0_s0_agent:rp_startofpacket -> router_004:sink_startofpacket
	wire          mm_bridge_0_s0_agent_rp_endofpacket;                                        // mm_bridge_0_s0_agent:rp_endofpacket -> router_004:sink_endofpacket
	wire          router_004_src_valid;                                                       // router_004:src_valid -> rsp_demux:sink_valid
	wire  [124:0] router_004_src_data;                                                        // router_004:src_data -> rsp_demux:sink_data
	wire          router_004_src_ready;                                                       // rsp_demux:sink_ready -> router_004:src_ready
	wire    [3:0] router_004_src_channel;                                                     // router_004:src_channel -> rsp_demux:sink_channel
	wire          router_004_src_startofpacket;                                               // router_004:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_004_src_endofpacket;                                                 // router_004:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          cmd_mux_src_valid;                                                          // cmd_mux:src_valid -> mm_bridge_0_s0_burst_adapter:sink0_valid
	wire  [124:0] cmd_mux_src_data;                                                           // cmd_mux:src_data -> mm_bridge_0_s0_burst_adapter:sink0_data
	wire          cmd_mux_src_ready;                                                          // mm_bridge_0_s0_burst_adapter:sink0_ready -> cmd_mux:src_ready
	wire    [3:0] cmd_mux_src_channel;                                                        // cmd_mux:src_channel -> mm_bridge_0_s0_burst_adapter:sink0_channel
	wire          cmd_mux_src_startofpacket;                                                  // cmd_mux:src_startofpacket -> mm_bridge_0_s0_burst_adapter:sink0_startofpacket
	wire          cmd_mux_src_endofpacket;                                                    // cmd_mux:src_endofpacket -> mm_bridge_0_s0_burst_adapter:sink0_endofpacket
	wire          mm_bridge_0_s0_burst_adapter_source0_valid;                                 // mm_bridge_0_s0_burst_adapter:source0_valid -> mm_bridge_0_s0_agent:cp_valid
	wire  [124:0] mm_bridge_0_s0_burst_adapter_source0_data;                                  // mm_bridge_0_s0_burst_adapter:source0_data -> mm_bridge_0_s0_agent:cp_data
	wire          mm_bridge_0_s0_burst_adapter_source0_ready;                                 // mm_bridge_0_s0_agent:cp_ready -> mm_bridge_0_s0_burst_adapter:source0_ready
	wire    [3:0] mm_bridge_0_s0_burst_adapter_source0_channel;                               // mm_bridge_0_s0_burst_adapter:source0_channel -> mm_bridge_0_s0_agent:cp_channel
	wire          mm_bridge_0_s0_burst_adapter_source0_startofpacket;                         // mm_bridge_0_s0_burst_adapter:source0_startofpacket -> mm_bridge_0_s0_agent:cp_startofpacket
	wire          mm_bridge_0_s0_burst_adapter_source0_endofpacket;                           // mm_bridge_0_s0_burst_adapter:source0_endofpacket -> mm_bridge_0_s0_agent:cp_endofpacket
	wire          cmd_demux_src0_valid;                                                       // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire  [124:0] cmd_demux_src0_data;                                                        // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire          cmd_demux_src0_ready;                                                       // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire    [3:0] cmd_demux_src0_channel;                                                     // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire          cmd_demux_src0_startofpacket;                                               // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire          cmd_demux_src0_endofpacket;                                                 // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_001_src0_valid;                                                   // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
	wire  [124:0] cmd_demux_001_src0_data;                                                    // cmd_demux_001:src0_data -> cmd_mux:sink1_data
	wire          cmd_demux_001_src0_ready;                                                   // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
	wire    [3:0] cmd_demux_001_src0_channel;                                                 // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
	wire          cmd_demux_001_src0_startofpacket;                                           // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
	wire          cmd_demux_001_src0_endofpacket;                                             // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
	wire          cmd_demux_002_src0_valid;                                                   // cmd_demux_002:src0_valid -> cmd_mux:sink2_valid
	wire  [124:0] cmd_demux_002_src0_data;                                                    // cmd_demux_002:src0_data -> cmd_mux:sink2_data
	wire          cmd_demux_002_src0_ready;                                                   // cmd_mux:sink2_ready -> cmd_demux_002:src0_ready
	wire    [3:0] cmd_demux_002_src0_channel;                                                 // cmd_demux_002:src0_channel -> cmd_mux:sink2_channel
	wire          cmd_demux_002_src0_startofpacket;                                           // cmd_demux_002:src0_startofpacket -> cmd_mux:sink2_startofpacket
	wire          cmd_demux_002_src0_endofpacket;                                             // cmd_demux_002:src0_endofpacket -> cmd_mux:sink2_endofpacket
	wire          cmd_demux_003_src0_valid;                                                   // cmd_demux_003:src0_valid -> cmd_mux:sink3_valid
	wire  [124:0] cmd_demux_003_src0_data;                                                    // cmd_demux_003:src0_data -> cmd_mux:sink3_data
	wire          cmd_demux_003_src0_ready;                                                   // cmd_mux:sink3_ready -> cmd_demux_003:src0_ready
	wire    [3:0] cmd_demux_003_src0_channel;                                                 // cmd_demux_003:src0_channel -> cmd_mux:sink3_channel
	wire          cmd_demux_003_src0_startofpacket;                                           // cmd_demux_003:src0_startofpacket -> cmd_mux:sink3_startofpacket
	wire          cmd_demux_003_src0_endofpacket;                                             // cmd_demux_003:src0_endofpacket -> cmd_mux:sink3_endofpacket
	wire          rsp_demux_src0_valid;                                                       // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire  [124:0] rsp_demux_src0_data;                                                        // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire          rsp_demux_src0_ready;                                                       // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire    [3:0] rsp_demux_src0_channel;                                                     // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire          rsp_demux_src0_startofpacket;                                               // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire          rsp_demux_src0_endofpacket;                                                 // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_src1_valid;                                                       // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
	wire  [124:0] rsp_demux_src1_data;                                                        // rsp_demux:src1_data -> rsp_mux_001:sink0_data
	wire          rsp_demux_src1_ready;                                                       // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
	wire    [3:0] rsp_demux_src1_channel;                                                     // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
	wire          rsp_demux_src1_startofpacket;                                               // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
	wire          rsp_demux_src1_endofpacket;                                                 // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
	wire          rsp_demux_src2_valid;                                                       // rsp_demux:src2_valid -> rsp_mux_002:sink0_valid
	wire  [124:0] rsp_demux_src2_data;                                                        // rsp_demux:src2_data -> rsp_mux_002:sink0_data
	wire          rsp_demux_src2_ready;                                                       // rsp_mux_002:sink0_ready -> rsp_demux:src2_ready
	wire    [3:0] rsp_demux_src2_channel;                                                     // rsp_demux:src2_channel -> rsp_mux_002:sink0_channel
	wire          rsp_demux_src2_startofpacket;                                               // rsp_demux:src2_startofpacket -> rsp_mux_002:sink0_startofpacket
	wire          rsp_demux_src2_endofpacket;                                                 // rsp_demux:src2_endofpacket -> rsp_mux_002:sink0_endofpacket
	wire          rsp_demux_src3_valid;                                                       // rsp_demux:src3_valid -> rsp_mux_003:sink0_valid
	wire  [124:0] rsp_demux_src3_data;                                                        // rsp_demux:src3_data -> rsp_mux_003:sink0_data
	wire          rsp_demux_src3_ready;                                                       // rsp_mux_003:sink0_ready -> rsp_demux:src3_ready
	wire    [3:0] rsp_demux_src3_channel;                                                     // rsp_demux:src3_channel -> rsp_mux_003:sink0_channel
	wire          rsp_demux_src3_startofpacket;                                               // rsp_demux:src3_startofpacket -> rsp_mux_003:sink0_startofpacket
	wire          rsp_demux_src3_endofpacket;                                                 // rsp_demux:src3_endofpacket -> rsp_mux_003:sink0_endofpacket
	wire          mm_bridge_0_s0_agent_rdata_fifo_out_valid;                                  // mm_bridge_0_s0_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
	wire   [33:0] mm_bridge_0_s0_agent_rdata_fifo_out_data;                                   // mm_bridge_0_s0_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
	wire          mm_bridge_0_s0_agent_rdata_fifo_out_ready;                                  // avalon_st_adapter:in_0_ready -> mm_bridge_0_s0_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_out_0_valid;                                              // avalon_st_adapter:out_0_valid -> mm_bridge_0_s0_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_out_0_data;                                               // avalon_st_adapter:out_0_data -> mm_bridge_0_s0_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_out_0_ready;                                              // mm_bridge_0_s0_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
	wire    [0:0] avalon_st_adapter_out_0_error;                                              // avalon_st_adapter:out_0_error -> mm_bridge_0_s0_agent:rdata_fifo_sink_error

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) fpga_only_master_master_translator (
		.clk                    (clk_0_clk_clk),                                                              //                       clk.clk
		.reset                  (mm_bridge_0_reset_reset_bridge_in_reset_reset),                              //                     reset.reset
		.uav_address            (fpga_only_master_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (fpga_only_master_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (fpga_only_master_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (fpga_only_master_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (fpga_only_master_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (fpga_only_master_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (fpga_only_master_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (fpga_only_master_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (fpga_only_master_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (fpga_only_master_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (fpga_only_master_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (fpga_only_master_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (fpga_only_master_master_waitrequest),                                        //                          .waitrequest
		.av_byteenable          (fpga_only_master_master_byteenable),                                         //                          .byteenable
		.av_read                (fpga_only_master_master_read),                                               //                          .read
		.av_readdata            (fpga_only_master_master_readdata),                                           //                          .readdata
		.av_readdatavalid       (fpga_only_master_master_readdatavalid),                                      //                          .readdatavalid
		.av_write               (fpga_only_master_master_write),                                              //                          .write
		.av_writedata           (fpga_only_master_master_writedata),                                          //                          .writedata
		.av_burstcount          (1'b1),                                                                       //               (terminated)
		.av_beginbursttransfer  (1'b0),                                                                       //               (terminated)
		.av_begintransfer       (1'b0),                                                                       //               (terminated)
		.av_chipselect          (1'b0),                                                                       //               (terminated)
		.av_lock                (1'b0),                                                                       //               (terminated)
		.av_debugaccess         (1'b0),                                                                       //               (terminated)
		.uav_clken              (),                                                                           //               (terminated)
		.av_clken               (1'b1),                                                                       //               (terminated)
		.uav_response           (2'b00),                                                                      //               (terminated)
		.av_response            (),                                                                           //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                       //               (terminated)
		.av_writeresponsevalid  ()                                                                            //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) sys_console_mst_master_translator (
		.clk                    (clk_0_clk_clk),                                                             //                       clk.clk
		.reset                  (mm_bridge_0_reset_reset_bridge_in_reset_reset),                             //                     reset.reset
		.uav_address            (sys_console_mst_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (sys_console_mst_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (sys_console_mst_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (sys_console_mst_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (sys_console_mst_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (sys_console_mst_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (sys_console_mst_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (sys_console_mst_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (sys_console_mst_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (sys_console_mst_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (sys_console_mst_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (sys_console_mst_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (sys_console_mst_master_waitrequest),                                        //                          .waitrequest
		.av_byteenable          (sys_console_mst_master_byteenable),                                         //                          .byteenable
		.av_read                (sys_console_mst_master_read),                                               //                          .read
		.av_readdata            (sys_console_mst_master_readdata),                                           //                          .readdata
		.av_readdatavalid       (sys_console_mst_master_readdatavalid),                                      //                          .readdatavalid
		.av_write               (sys_console_mst_master_write),                                              //                          .write
		.av_writedata           (sys_console_mst_master_writedata),                                          //                          .writedata
		.av_burstcount          (1'b1),                                                                      //               (terminated)
		.av_beginbursttransfer  (1'b0),                                                                      //               (terminated)
		.av_begintransfer       (1'b0),                                                                      //               (terminated)
		.av_chipselect          (1'b0),                                                                      //               (terminated)
		.av_lock                (1'b0),                                                                      //               (terminated)
		.av_debugaccess         (1'b0),                                                                      //               (terminated)
		.uav_clken              (),                                                                          //               (terminated)
		.av_clken               (1'b1),                                                                      //               (terminated)
		.uav_response           (2'b00),                                                                     //               (terminated)
		.av_response            (),                                                                          //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                      //               (terminated)
		.av_writeresponsevalid  ()                                                                           //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (19),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) mm_bridge_0_s0_translator (
		.clk                    (clk_0_clk_clk),                                 //                      clk.clk
		.reset                  (mm_bridge_0_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (mm_bridge_0_s0_agent_m0_address),               // avalon_universal_slave_0.address
		.uav_burstcount         (mm_bridge_0_s0_agent_m0_burstcount),            //                         .burstcount
		.uav_read               (mm_bridge_0_s0_agent_m0_read),                  //                         .read
		.uav_write              (mm_bridge_0_s0_agent_m0_write),                 //                         .write
		.uav_waitrequest        (mm_bridge_0_s0_agent_m0_waitrequest),           //                         .waitrequest
		.uav_readdatavalid      (mm_bridge_0_s0_agent_m0_readdatavalid),         //                         .readdatavalid
		.uav_byteenable         (mm_bridge_0_s0_agent_m0_byteenable),            //                         .byteenable
		.uav_readdata           (mm_bridge_0_s0_agent_m0_readdata),              //                         .readdata
		.uav_writedata          (mm_bridge_0_s0_agent_m0_writedata),             //                         .writedata
		.uav_lock               (mm_bridge_0_s0_agent_m0_lock),                  //                         .lock
		.uav_debugaccess        (mm_bridge_0_s0_agent_m0_debugaccess),           //                         .debugaccess
		.av_address             (mm_bridge_0_s0_address),                        //      avalon_anti_slave_0.address
		.av_write               (mm_bridge_0_s0_write),                          //                         .write
		.av_read                (mm_bridge_0_s0_read),                           //                         .read
		.av_readdata            (mm_bridge_0_s0_readdata),                       //                         .readdata
		.av_writedata           (mm_bridge_0_s0_writedata),                      //                         .writedata
		.av_burstcount          (mm_bridge_0_s0_burstcount),                     //                         .burstcount
		.av_byteenable          (mm_bridge_0_s0_byteenable),                     //                         .byteenable
		.av_readdatavalid       (mm_bridge_0_s0_readdatavalid),                  //                         .readdatavalid
		.av_waitrequest         (mm_bridge_0_s0_waitrequest),                    //                         .waitrequest
		.av_debugaccess         (mm_bridge_0_s0_debugaccess),                    //                         .debugaccess
		.av_begintransfer       (),                                              //              (terminated)
		.av_beginbursttransfer  (),                                              //              (terminated)
		.av_writebyteenable     (),                                              //              (terminated)
		.av_lock                (),                                              //              (terminated)
		.av_chipselect          (),                                              //              (terminated)
		.av_clken               (),                                              //              (terminated)
		.uav_clken              (1'b0),                                          //              (terminated)
		.av_outputenable        (),                                              //              (terminated)
		.uav_response           (),                                              //              (terminated)
		.av_response            (2'b00),                                         //              (terminated)
		.uav_writeresponsevalid (),                                              //              (terminated)
		.av_writeresponsevalid  (1'b0)                                           //              (terminated)
	);

	altera_merlin_axi_master_ni #(
		.ID_WIDTH                  (12),
		.ADDR_WIDTH                (21),
		.RDATA_WIDTH               (32),
		.WDATA_WIDTH               (32),
		.ADDR_USER_WIDTH           (1),
		.DATA_USER_WIDTH           (1),
		.AXI_BURST_LENGTH_WIDTH    (4),
		.AXI_LOCK_WIDTH            (2),
		.AXI_VERSION               ("AXI3"),
		.WRITE_ISSUING_CAPABILITY  (8),
		.READ_ISSUING_CAPABILITY   (8),
		.PKT_BEGIN_BURST           (95),
		.PKT_CACHE_H               (119),
		.PKT_CACHE_L               (116),
		.PKT_ADDR_SIDEBAND_H       (93),
		.PKT_ADDR_SIDEBAND_L       (93),
		.PKT_PROTECTION_H          (115),
		.PKT_PROTECTION_L          (113),
		.PKT_BURST_SIZE_H          (90),
		.PKT_BURST_SIZE_L          (88),
		.PKT_BURST_TYPE_H          (92),
		.PKT_BURST_TYPE_L          (91),
		.PKT_RESPONSE_STATUS_L     (120),
		.PKT_RESPONSE_STATUS_H     (121),
		.PKT_BURSTWRAP_H           (87),
		.PKT_BURSTWRAP_L           (81),
		.PKT_BYTE_CNT_H            (80),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_EXCLUSIVE       (73),
		.PKT_TRANS_LOCK            (72),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (98),
		.PKT_SRC_ID_L              (97),
		.PKT_DEST_ID_H             (100),
		.PKT_DEST_ID_L             (99),
		.PKT_THREAD_ID_H           (112),
		.PKT_THREAD_ID_L           (101),
		.PKT_QOS_L                 (96),
		.PKT_QOS_H                 (96),
		.PKT_ORI_BURST_SIZE_L      (122),
		.PKT_ORI_BURST_SIZE_H      (124),
		.PKT_DATA_SIDEBAND_H       (94),
		.PKT_DATA_SIDEBAND_L       (94),
		.ST_DATA_W                 (125),
		.ST_CHANNEL_W              (4),
		.ID                        (1)
	) hps_0_h2f_lw_axi_master_agent (
		.aclk                   (clk_0_clk_clk),                                                        //              clk.clk
		.aresetn                (~hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), //        clk_reset.reset_n
		.write_cp_valid         (hps_0_h2f_lw_axi_master_agent_write_cp_valid),                         //         write_cp.valid
		.write_cp_data          (hps_0_h2f_lw_axi_master_agent_write_cp_data),                          //                 .data
		.write_cp_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket),                 //                 .startofpacket
		.write_cp_endofpacket   (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket),                   //                 .endofpacket
		.write_cp_ready         (hps_0_h2f_lw_axi_master_agent_write_cp_ready),                         //                 .ready
		.write_rp_valid         (rsp_mux_src_valid),                                                    //         write_rp.valid
		.write_rp_data          (rsp_mux_src_data),                                                     //                 .data
		.write_rp_channel       (rsp_mux_src_channel),                                                  //                 .channel
		.write_rp_startofpacket (rsp_mux_src_startofpacket),                                            //                 .startofpacket
		.write_rp_endofpacket   (rsp_mux_src_endofpacket),                                              //                 .endofpacket
		.write_rp_ready         (rsp_mux_src_ready),                                                    //                 .ready
		.read_cp_valid          (hps_0_h2f_lw_axi_master_agent_read_cp_valid),                          //          read_cp.valid
		.read_cp_data           (hps_0_h2f_lw_axi_master_agent_read_cp_data),                           //                 .data
		.read_cp_startofpacket  (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket),                  //                 .startofpacket
		.read_cp_endofpacket    (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket),                    //                 .endofpacket
		.read_cp_ready          (hps_0_h2f_lw_axi_master_agent_read_cp_ready),                          //                 .ready
		.read_rp_valid          (rsp_mux_001_src_valid),                                                //          read_rp.valid
		.read_rp_data           (rsp_mux_001_src_data),                                                 //                 .data
		.read_rp_channel        (rsp_mux_001_src_channel),                                              //                 .channel
		.read_rp_startofpacket  (rsp_mux_001_src_startofpacket),                                        //                 .startofpacket
		.read_rp_endofpacket    (rsp_mux_001_src_endofpacket),                                          //                 .endofpacket
		.read_rp_ready          (rsp_mux_001_src_ready),                                                //                 .ready
		.awid                   (hps_0_h2f_lw_axi_master_awid),                                         // altera_axi_slave.awid
		.awaddr                 (hps_0_h2f_lw_axi_master_awaddr),                                       //                 .awaddr
		.awlen                  (hps_0_h2f_lw_axi_master_awlen),                                        //                 .awlen
		.awsize                 (hps_0_h2f_lw_axi_master_awsize),                                       //                 .awsize
		.awburst                (hps_0_h2f_lw_axi_master_awburst),                                      //                 .awburst
		.awlock                 (hps_0_h2f_lw_axi_master_awlock),                                       //                 .awlock
		.awcache                (hps_0_h2f_lw_axi_master_awcache),                                      //                 .awcache
		.awprot                 (hps_0_h2f_lw_axi_master_awprot),                                       //                 .awprot
		.awvalid                (hps_0_h2f_lw_axi_master_awvalid),                                      //                 .awvalid
		.awready                (hps_0_h2f_lw_axi_master_awready),                                      //                 .awready
		.wid                    (hps_0_h2f_lw_axi_master_wid),                                          //                 .wid
		.wdata                  (hps_0_h2f_lw_axi_master_wdata),                                        //                 .wdata
		.wstrb                  (hps_0_h2f_lw_axi_master_wstrb),                                        //                 .wstrb
		.wlast                  (hps_0_h2f_lw_axi_master_wlast),                                        //                 .wlast
		.wvalid                 (hps_0_h2f_lw_axi_master_wvalid),                                       //                 .wvalid
		.wready                 (hps_0_h2f_lw_axi_master_wready),                                       //                 .wready
		.bid                    (hps_0_h2f_lw_axi_master_bid),                                          //                 .bid
		.bresp                  (hps_0_h2f_lw_axi_master_bresp),                                        //                 .bresp
		.bvalid                 (hps_0_h2f_lw_axi_master_bvalid),                                       //                 .bvalid
		.bready                 (hps_0_h2f_lw_axi_master_bready),                                       //                 .bready
		.arid                   (hps_0_h2f_lw_axi_master_arid),                                         //                 .arid
		.araddr                 (hps_0_h2f_lw_axi_master_araddr),                                       //                 .araddr
		.arlen                  (hps_0_h2f_lw_axi_master_arlen),                                        //                 .arlen
		.arsize                 (hps_0_h2f_lw_axi_master_arsize),                                       //                 .arsize
		.arburst                (hps_0_h2f_lw_axi_master_arburst),                                      //                 .arburst
		.arlock                 (hps_0_h2f_lw_axi_master_arlock),                                       //                 .arlock
		.arcache                (hps_0_h2f_lw_axi_master_arcache),                                      //                 .arcache
		.arprot                 (hps_0_h2f_lw_axi_master_arprot),                                       //                 .arprot
		.arvalid                (hps_0_h2f_lw_axi_master_arvalid),                                      //                 .arvalid
		.arready                (hps_0_h2f_lw_axi_master_arready),                                      //                 .arready
		.rid                    (hps_0_h2f_lw_axi_master_rid),                                          //                 .rid
		.rdata                  (hps_0_h2f_lw_axi_master_rdata),                                        //                 .rdata
		.rresp                  (hps_0_h2f_lw_axi_master_rresp),                                        //                 .rresp
		.rlast                  (hps_0_h2f_lw_axi_master_rlast),                                        //                 .rlast
		.rvalid                 (hps_0_h2f_lw_axi_master_rvalid),                                       //                 .rvalid
		.rready                 (hps_0_h2f_lw_axi_master_rready),                                       //                 .rready
		.awuser                 (1'b0),                                                                 //      (terminated)
		.aruser                 (1'b0),                                                                 //      (terminated)
		.awqos                  (4'b0000),                                                              //      (terminated)
		.arqos                  (4'b0000),                                                              //      (terminated)
		.awregion               (4'b0000),                                                              //      (terminated)
		.arregion               (4'b0000),                                                              //      (terminated)
		.wuser                  (1'b0),                                                                 //      (terminated)
		.ruser                  (),                                                                     //      (terminated)
		.buser                  ()                                                                      //      (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (124),
		.PKT_ORI_BURST_SIZE_L      (122),
		.PKT_RESPONSE_STATUS_H     (121),
		.PKT_RESPONSE_STATUS_L     (120),
		.PKT_QOS_H                 (96),
		.PKT_QOS_L                 (96),
		.PKT_DATA_SIDEBAND_H       (94),
		.PKT_DATA_SIDEBAND_L       (94),
		.PKT_ADDR_SIDEBAND_H       (93),
		.PKT_ADDR_SIDEBAND_L       (93),
		.PKT_BURST_TYPE_H          (92),
		.PKT_BURST_TYPE_L          (91),
		.PKT_CACHE_H               (119),
		.PKT_CACHE_L               (116),
		.PKT_THREAD_ID_H           (112),
		.PKT_THREAD_ID_L           (101),
		.PKT_BURST_SIZE_H          (90),
		.PKT_BURST_SIZE_L          (88),
		.PKT_TRANS_EXCLUSIVE       (73),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (95),
		.PKT_PROTECTION_H          (115),
		.PKT_PROTECTION_L          (113),
		.PKT_BURSTWRAP_H           (87),
		.PKT_BURSTWRAP_L           (81),
		.PKT_BYTE_CNT_H            (80),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (98),
		.PKT_SRC_ID_L              (97),
		.PKT_DEST_ID_H             (100),
		.PKT_DEST_ID_L             (99),
		.ST_DATA_W                 (125),
		.ST_CHANNEL_W              (4),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (127),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) fpga_only_master_master_agent (
		.clk                   (clk_0_clk_clk),                                                              //       clk.clk
		.reset                 (mm_bridge_0_reset_reset_bridge_in_reset_reset),                              // clk_reset.reset
		.av_address            (fpga_only_master_master_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (fpga_only_master_master_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (fpga_only_master_master_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (fpga_only_master_master_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (fpga_only_master_master_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (fpga_only_master_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (fpga_only_master_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (fpga_only_master_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (fpga_only_master_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (fpga_only_master_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (fpga_only_master_master_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (fpga_only_master_master_agent_cp_valid),                                     //        cp.valid
		.cp_data               (fpga_only_master_master_agent_cp_data),                                      //          .data
		.cp_startofpacket      (fpga_only_master_master_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (fpga_only_master_master_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (fpga_only_master_master_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_002_src_valid),                                                      //        rp.valid
		.rp_data               (rsp_mux_002_src_data),                                                       //          .data
		.rp_channel            (rsp_mux_002_src_channel),                                                    //          .channel
		.rp_startofpacket      (rsp_mux_002_src_startofpacket),                                              //          .startofpacket
		.rp_endofpacket        (rsp_mux_002_src_endofpacket),                                                //          .endofpacket
		.rp_ready              (rsp_mux_002_src_ready),                                                      //          .ready
		.av_response           (),                                                                           // (terminated)
		.av_writeresponsevalid ()                                                                            // (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (124),
		.PKT_ORI_BURST_SIZE_L      (122),
		.PKT_RESPONSE_STATUS_H     (121),
		.PKT_RESPONSE_STATUS_L     (120),
		.PKT_QOS_H                 (96),
		.PKT_QOS_L                 (96),
		.PKT_DATA_SIDEBAND_H       (94),
		.PKT_DATA_SIDEBAND_L       (94),
		.PKT_ADDR_SIDEBAND_H       (93),
		.PKT_ADDR_SIDEBAND_L       (93),
		.PKT_BURST_TYPE_H          (92),
		.PKT_BURST_TYPE_L          (91),
		.PKT_CACHE_H               (119),
		.PKT_CACHE_L               (116),
		.PKT_THREAD_ID_H           (112),
		.PKT_THREAD_ID_L           (101),
		.PKT_BURST_SIZE_H          (90),
		.PKT_BURST_SIZE_L          (88),
		.PKT_TRANS_EXCLUSIVE       (73),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (95),
		.PKT_PROTECTION_H          (115),
		.PKT_PROTECTION_L          (113),
		.PKT_BURSTWRAP_H           (87),
		.PKT_BURSTWRAP_L           (81),
		.PKT_BYTE_CNT_H            (80),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (98),
		.PKT_SRC_ID_L              (97),
		.PKT_DEST_ID_H             (100),
		.PKT_DEST_ID_L             (99),
		.ST_DATA_W                 (125),
		.ST_CHANNEL_W              (4),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (2),
		.BURSTWRAP_VALUE           (127),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) sys_console_mst_master_agent (
		.clk                   (clk_0_clk_clk),                                                             //       clk.clk
		.reset                 (mm_bridge_0_reset_reset_bridge_in_reset_reset),                             // clk_reset.reset
		.av_address            (sys_console_mst_master_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (sys_console_mst_master_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (sys_console_mst_master_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (sys_console_mst_master_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (sys_console_mst_master_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (sys_console_mst_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (sys_console_mst_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (sys_console_mst_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (sys_console_mst_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (sys_console_mst_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (sys_console_mst_master_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (sys_console_mst_master_agent_cp_valid),                                     //        cp.valid
		.cp_data               (sys_console_mst_master_agent_cp_data),                                      //          .data
		.cp_startofpacket      (sys_console_mst_master_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (sys_console_mst_master_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (sys_console_mst_master_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_003_src_valid),                                                     //        rp.valid
		.rp_data               (rsp_mux_003_src_data),                                                      //          .data
		.rp_channel            (rsp_mux_003_src_channel),                                                   //          .channel
		.rp_startofpacket      (rsp_mux_003_src_startofpacket),                                             //          .startofpacket
		.rp_endofpacket        (rsp_mux_003_src_endofpacket),                                               //          .endofpacket
		.rp_ready              (rsp_mux_003_src_ready),                                                     //          .ready
		.av_response           (),                                                                          // (terminated)
		.av_writeresponsevalid ()                                                                           // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (124),
		.PKT_ORI_BURST_SIZE_L      (122),
		.PKT_RESPONSE_STATUS_H     (121),
		.PKT_RESPONSE_STATUS_L     (120),
		.PKT_BURST_SIZE_H          (90),
		.PKT_BURST_SIZE_L          (88),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (95),
		.PKT_PROTECTION_H          (115),
		.PKT_PROTECTION_L          (113),
		.PKT_BURSTWRAP_H           (87),
		.PKT_BURSTWRAP_L           (81),
		.PKT_BYTE_CNT_H            (80),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (98),
		.PKT_SRC_ID_L              (97),
		.PKT_DEST_ID_H             (100),
		.PKT_DEST_ID_L             (99),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (4),
		.ST_DATA_W                 (125),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) mm_bridge_0_s0_agent (
		.clk                     (clk_0_clk_clk),                                      //             clk.clk
		.reset                   (mm_bridge_0_reset_reset_bridge_in_reset_reset),      //       clk_reset.reset
		.m0_address              (mm_bridge_0_s0_agent_m0_address),                    //              m0.address
		.m0_burstcount           (mm_bridge_0_s0_agent_m0_burstcount),                 //                .burstcount
		.m0_byteenable           (mm_bridge_0_s0_agent_m0_byteenable),                 //                .byteenable
		.m0_debugaccess          (mm_bridge_0_s0_agent_m0_debugaccess),                //                .debugaccess
		.m0_lock                 (mm_bridge_0_s0_agent_m0_lock),                       //                .lock
		.m0_readdata             (mm_bridge_0_s0_agent_m0_readdata),                   //                .readdata
		.m0_readdatavalid        (mm_bridge_0_s0_agent_m0_readdatavalid),              //                .readdatavalid
		.m0_read                 (mm_bridge_0_s0_agent_m0_read),                       //                .read
		.m0_waitrequest          (mm_bridge_0_s0_agent_m0_waitrequest),                //                .waitrequest
		.m0_writedata            (mm_bridge_0_s0_agent_m0_writedata),                  //                .writedata
		.m0_write                (mm_bridge_0_s0_agent_m0_write),                      //                .write
		.rp_endofpacket          (mm_bridge_0_s0_agent_rp_endofpacket),                //              rp.endofpacket
		.rp_ready                (mm_bridge_0_s0_agent_rp_ready),                      //                .ready
		.rp_valid                (mm_bridge_0_s0_agent_rp_valid),                      //                .valid
		.rp_data                 (mm_bridge_0_s0_agent_rp_data),                       //                .data
		.rp_startofpacket        (mm_bridge_0_s0_agent_rp_startofpacket),              //                .startofpacket
		.cp_ready                (mm_bridge_0_s0_burst_adapter_source0_ready),         //              cp.ready
		.cp_valid                (mm_bridge_0_s0_burst_adapter_source0_valid),         //                .valid
		.cp_data                 (mm_bridge_0_s0_burst_adapter_source0_data),          //                .data
		.cp_startofpacket        (mm_bridge_0_s0_burst_adapter_source0_startofpacket), //                .startofpacket
		.cp_endofpacket          (mm_bridge_0_s0_burst_adapter_source0_endofpacket),   //                .endofpacket
		.cp_channel              (mm_bridge_0_s0_burst_adapter_source0_channel),       //                .channel
		.rf_sink_ready           (mm_bridge_0_s0_agent_rsp_fifo_out_ready),            //         rf_sink.ready
		.rf_sink_valid           (mm_bridge_0_s0_agent_rsp_fifo_out_valid),            //                .valid
		.rf_sink_startofpacket   (mm_bridge_0_s0_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
		.rf_sink_endofpacket     (mm_bridge_0_s0_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
		.rf_sink_data            (mm_bridge_0_s0_agent_rsp_fifo_out_data),             //                .data
		.rf_source_ready         (mm_bridge_0_s0_agent_rf_source_ready),               //       rf_source.ready
		.rf_source_valid         (mm_bridge_0_s0_agent_rf_source_valid),               //                .valid
		.rf_source_startofpacket (mm_bridge_0_s0_agent_rf_source_startofpacket),       //                .startofpacket
		.rf_source_endofpacket   (mm_bridge_0_s0_agent_rf_source_endofpacket),         //                .endofpacket
		.rf_source_data          (mm_bridge_0_s0_agent_rf_source_data),                //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                      // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                      //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                       //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                      //                .error
		.rdata_fifo_src_ready    (mm_bridge_0_s0_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (mm_bridge_0_s0_agent_rdata_fifo_src_valid),          //                .valid
		.rdata_fifo_src_data     (mm_bridge_0_s0_agent_rdata_fifo_src_data),           //                .data
		.m0_response             (2'b00),                                              //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (126),
		.FIFO_DEPTH          (5),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) mm_bridge_0_s0_agent_rsp_fifo (
		.clk               (clk_0_clk_clk),                                   //       clk.clk
		.reset             (mm_bridge_0_reset_reset_bridge_in_reset_reset),   // clk_reset.reset
		.in_data           (mm_bridge_0_s0_agent_rf_source_data),             //        in.data
		.in_valid          (mm_bridge_0_s0_agent_rf_source_valid),            //          .valid
		.in_ready          (mm_bridge_0_s0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (mm_bridge_0_s0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (mm_bridge_0_s0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (mm_bridge_0_s0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (mm_bridge_0_s0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (mm_bridge_0_s0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (mm_bridge_0_s0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (mm_bridge_0_s0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                           // (terminated)
		.csr_read          (1'b0),                                            // (terminated)
		.csr_write         (1'b0),                                            // (terminated)
		.csr_readdata      (),                                                // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),            // (terminated)
		.almost_full_data  (),                                                // (terminated)
		.almost_empty_data (),                                                // (terminated)
		.in_empty          (1'b0),                                            // (terminated)
		.out_empty         (),                                                // (terminated)
		.in_error          (1'b0),                                            // (terminated)
		.out_error         (),                                                // (terminated)
		.in_channel        (1'b0),                                            // (terminated)
		.out_channel       ()                                                 // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (8),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (3),
		.USE_MEMORY_BLOCKS   (1),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) mm_bridge_0_s0_agent_rdata_fifo (
		.clk               (clk_0_clk_clk),                                 //       clk.clk
		.reset             (mm_bridge_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (mm_bridge_0_s0_agent_rdata_fifo_src_data),      //        in.data
		.in_valid          (mm_bridge_0_s0_agent_rdata_fifo_src_valid),     //          .valid
		.in_ready          (mm_bridge_0_s0_agent_rdata_fifo_src_ready),     //          .ready
		.out_data          (mm_bridge_0_s0_agent_rdata_fifo_out_data),      //       out.data
		.out_valid         (mm_bridge_0_s0_agent_rdata_fifo_out_valid),     //          .valid
		.out_ready         (mm_bridge_0_s0_agent_rdata_fifo_out_ready),     //          .ready
		.csr_address       (2'b00),                                         // (terminated)
		.csr_read          (1'b0),                                          // (terminated)
		.csr_write         (1'b0),                                          // (terminated)
		.csr_readdata      (),                                              // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),          // (terminated)
		.almost_full_data  (),                                              // (terminated)
		.almost_empty_data (),                                              // (terminated)
		.in_startofpacket  (1'b0),                                          // (terminated)
		.in_endofpacket    (1'b0),                                          // (terminated)
		.out_startofpacket (),                                              // (terminated)
		.out_endofpacket   (),                                              // (terminated)
		.in_empty          (1'b0),                                          // (terminated)
		.out_empty         (),                                              // (terminated)
		.in_error          (1'b0),                                          // (terminated)
		.out_error         (),                                              // (terminated)
		.in_channel        (1'b0),                                          // (terminated)
		.out_channel       ()                                               // (terminated)
	);

	soc_system_mm_interconnect_2_router router (
		.sink_ready         (hps_0_h2f_lw_axi_master_agent_write_cp_ready),                        //      sink.ready
		.sink_valid         (hps_0_h2f_lw_axi_master_agent_write_cp_valid),                        //          .valid
		.sink_data          (hps_0_h2f_lw_axi_master_agent_write_cp_data),                         //          .data
		.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket),                //          .startofpacket
		.sink_endofpacket   (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket),                  //          .endofpacket
		.clk                (clk_0_clk_clk),                                                       //       clk.clk
		.reset              (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_src_ready),                                                    //       src.ready
		.src_valid          (router_src_valid),                                                    //          .valid
		.src_data           (router_src_data),                                                     //          .data
		.src_channel        (router_src_channel),                                                  //          .channel
		.src_startofpacket  (router_src_startofpacket),                                            //          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                               //          .endofpacket
	);

	soc_system_mm_interconnect_2_router router_001 (
		.sink_ready         (hps_0_h2f_lw_axi_master_agent_read_cp_ready),                         //      sink.ready
		.sink_valid         (hps_0_h2f_lw_axi_master_agent_read_cp_valid),                         //          .valid
		.sink_data          (hps_0_h2f_lw_axi_master_agent_read_cp_data),                          //          .data
		.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket),                   //          .endofpacket
		.clk                (clk_0_clk_clk),                                                       //       clk.clk
		.reset              (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_001_src_ready),                                                //       src.ready
		.src_valid          (router_001_src_valid),                                                //          .valid
		.src_data           (router_001_src_data),                                                 //          .data
		.src_channel        (router_001_src_channel),                                              //          .channel
		.src_startofpacket  (router_001_src_startofpacket),                                        //          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                                           //          .endofpacket
	);

	soc_system_mm_interconnect_2_router router_002 (
		.sink_ready         (fpga_only_master_master_agent_cp_ready),         //      sink.ready
		.sink_valid         (fpga_only_master_master_agent_cp_valid),         //          .valid
		.sink_data          (fpga_only_master_master_agent_cp_data),          //          .data
		.sink_startofpacket (fpga_only_master_master_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (fpga_only_master_master_agent_cp_endofpacket),   //          .endofpacket
		.clk                (clk_0_clk_clk),                                  //       clk.clk
		.reset              (mm_bridge_0_reset_reset_bridge_in_reset_reset),  // clk_reset.reset
		.src_ready          (router_002_src_ready),                           //       src.ready
		.src_valid          (router_002_src_valid),                           //          .valid
		.src_data           (router_002_src_data),                            //          .data
		.src_channel        (router_002_src_channel),                         //          .channel
		.src_startofpacket  (router_002_src_startofpacket),                   //          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                      //          .endofpacket
	);

	soc_system_mm_interconnect_2_router router_003 (
		.sink_ready         (sys_console_mst_master_agent_cp_ready),         //      sink.ready
		.sink_valid         (sys_console_mst_master_agent_cp_valid),         //          .valid
		.sink_data          (sys_console_mst_master_agent_cp_data),          //          .data
		.sink_startofpacket (sys_console_mst_master_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (sys_console_mst_master_agent_cp_endofpacket),   //          .endofpacket
		.clk                (clk_0_clk_clk),                                 //       clk.clk
		.reset              (mm_bridge_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_003_src_ready),                          //       src.ready
		.src_valid          (router_003_src_valid),                          //          .valid
		.src_data           (router_003_src_data),                           //          .data
		.src_channel        (router_003_src_channel),                        //          .channel
		.src_startofpacket  (router_003_src_startofpacket),                  //          .startofpacket
		.src_endofpacket    (router_003_src_endofpacket)                     //          .endofpacket
	);

	soc_system_mm_interconnect_2_router_004 router_004 (
		.sink_ready         (mm_bridge_0_s0_agent_rp_ready),                 //      sink.ready
		.sink_valid         (mm_bridge_0_s0_agent_rp_valid),                 //          .valid
		.sink_data          (mm_bridge_0_s0_agent_rp_data),                  //          .data
		.sink_startofpacket (mm_bridge_0_s0_agent_rp_startofpacket),         //          .startofpacket
		.sink_endofpacket   (mm_bridge_0_s0_agent_rp_endofpacket),           //          .endofpacket
		.clk                (clk_0_clk_clk),                                 //       clk.clk
		.reset              (mm_bridge_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_004_src_ready),                          //       src.ready
		.src_valid          (router_004_src_valid),                          //          .valid
		.src_data           (router_004_src_data),                           //          .data
		.src_channel        (router_004_src_channel),                        //          .channel
		.src_startofpacket  (router_004_src_startofpacket),                  //          .startofpacket
		.src_endofpacket    (router_004_src_endofpacket)                     //          .endofpacket
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (95),
		.PKT_BYTE_CNT_H            (80),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (90),
		.PKT_BURST_SIZE_L          (88),
		.PKT_BURST_TYPE_H          (92),
		.PKT_BURST_TYPE_L          (91),
		.PKT_BURSTWRAP_H           (87),
		.PKT_BURSTWRAP_L           (81),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (125),
		.ST_CHANNEL_W              (4),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (87),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1")
	) mm_bridge_0_s0_burst_adapter (
		.clk                   (clk_0_clk_clk),                                      //       cr0.clk
		.reset                 (mm_bridge_0_reset_reset_bridge_in_reset_reset),      // cr0_reset.reset
		.sink0_valid           (cmd_mux_src_valid),                                  //     sink0.valid
		.sink0_data            (cmd_mux_src_data),                                   //          .data
		.sink0_channel         (cmd_mux_src_channel),                                //          .channel
		.sink0_startofpacket   (cmd_mux_src_startofpacket),                          //          .startofpacket
		.sink0_endofpacket     (cmd_mux_src_endofpacket),                            //          .endofpacket
		.sink0_ready           (cmd_mux_src_ready),                                  //          .ready
		.source0_valid         (mm_bridge_0_s0_burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (mm_bridge_0_s0_burst_adapter_source0_data),          //          .data
		.source0_channel       (mm_bridge_0_s0_burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (mm_bridge_0_s0_burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (mm_bridge_0_s0_burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (mm_bridge_0_s0_burst_adapter_source0_ready)          //          .ready
	);

	soc_system_mm_interconnect_2_cmd_demux cmd_demux (
		.clk                (clk_0_clk_clk),                                                       //       clk.clk
		.reset              (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_src_ready),                                                    //      sink.ready
		.sink_channel       (router_src_channel),                                                  //          .channel
		.sink_data          (router_src_data),                                                     //          .data
		.sink_startofpacket (router_src_startofpacket),                                            //          .startofpacket
		.sink_endofpacket   (router_src_endofpacket),                                              //          .endofpacket
		.sink_valid         (router_src_valid),                                                    //          .valid
		.src0_ready         (cmd_demux_src0_ready),                                                //      src0.ready
		.src0_valid         (cmd_demux_src0_valid),                                                //          .valid
		.src0_data          (cmd_demux_src0_data),                                                 //          .data
		.src0_channel       (cmd_demux_src0_channel),                                              //          .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                                        //          .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket)                                           //          .endofpacket
	);

	soc_system_mm_interconnect_2_cmd_demux cmd_demux_001 (
		.clk                (clk_0_clk_clk),                                                       //       clk.clk
		.reset              (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_001_src_ready),                                                //      sink.ready
		.sink_channel       (router_001_src_channel),                                              //          .channel
		.sink_data          (router_001_src_data),                                                 //          .data
		.sink_startofpacket (router_001_src_startofpacket),                                        //          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),                                          //          .endofpacket
		.sink_valid         (router_001_src_valid),                                                //          .valid
		.src0_ready         (cmd_demux_001_src0_ready),                                            //      src0.ready
		.src0_valid         (cmd_demux_001_src0_valid),                                            //          .valid
		.src0_data          (cmd_demux_001_src0_data),                                             //          .data
		.src0_channel       (cmd_demux_001_src0_channel),                                          //          .channel
		.src0_startofpacket (cmd_demux_001_src0_startofpacket),                                    //          .startofpacket
		.src0_endofpacket   (cmd_demux_001_src0_endofpacket)                                       //          .endofpacket
	);

	soc_system_mm_interconnect_2_cmd_demux cmd_demux_002 (
		.clk                (clk_0_clk_clk),                                 //       clk.clk
		.reset              (mm_bridge_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_002_src_ready),                          //      sink.ready
		.sink_channel       (router_002_src_channel),                        //          .channel
		.sink_data          (router_002_src_data),                           //          .data
		.sink_startofpacket (router_002_src_startofpacket),                  //          .startofpacket
		.sink_endofpacket   (router_002_src_endofpacket),                    //          .endofpacket
		.sink_valid         (router_002_src_valid),                          //          .valid
		.src0_ready         (cmd_demux_002_src0_ready),                      //      src0.ready
		.src0_valid         (cmd_demux_002_src0_valid),                      //          .valid
		.src0_data          (cmd_demux_002_src0_data),                       //          .data
		.src0_channel       (cmd_demux_002_src0_channel),                    //          .channel
		.src0_startofpacket (cmd_demux_002_src0_startofpacket),              //          .startofpacket
		.src0_endofpacket   (cmd_demux_002_src0_endofpacket)                 //          .endofpacket
	);

	soc_system_mm_interconnect_2_cmd_demux cmd_demux_003 (
		.clk                (clk_0_clk_clk),                                 //       clk.clk
		.reset              (mm_bridge_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_003_src_ready),                          //      sink.ready
		.sink_channel       (router_003_src_channel),                        //          .channel
		.sink_data          (router_003_src_data),                           //          .data
		.sink_startofpacket (router_003_src_startofpacket),                  //          .startofpacket
		.sink_endofpacket   (router_003_src_endofpacket),                    //          .endofpacket
		.sink_valid         (router_003_src_valid),                          //          .valid
		.src0_ready         (cmd_demux_003_src0_ready),                      //      src0.ready
		.src0_valid         (cmd_demux_003_src0_valid),                      //          .valid
		.src0_data          (cmd_demux_003_src0_data),                       //          .data
		.src0_channel       (cmd_demux_003_src0_channel),                    //          .channel
		.src0_startofpacket (cmd_demux_003_src0_startofpacket),              //          .startofpacket
		.src0_endofpacket   (cmd_demux_003_src0_endofpacket)                 //          .endofpacket
	);

	soc_system_mm_interconnect_2_cmd_mux cmd_mux (
		.clk                 (clk_0_clk_clk),                                 //       clk.clk
		.reset               (mm_bridge_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                             //       src.ready
		.src_valid           (cmd_mux_src_valid),                             //          .valid
		.src_data            (cmd_mux_src_data),                              //          .data
		.src_channel         (cmd_mux_src_channel),                           //          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                     //          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                       //          .endofpacket
		.sink0_ready         (cmd_demux_src0_ready),                          //     sink0.ready
		.sink0_valid         (cmd_demux_src0_valid),                          //          .valid
		.sink0_channel       (cmd_demux_src0_channel),                        //          .channel
		.sink0_data          (cmd_demux_src0_data),                           //          .data
		.sink0_startofpacket (cmd_demux_src0_startofpacket),                  //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src0_endofpacket),                    //          .endofpacket
		.sink1_ready         (cmd_demux_001_src0_ready),                      //     sink1.ready
		.sink1_valid         (cmd_demux_001_src0_valid),                      //          .valid
		.sink1_channel       (cmd_demux_001_src0_channel),                    //          .channel
		.sink1_data          (cmd_demux_001_src0_data),                       //          .data
		.sink1_startofpacket (cmd_demux_001_src0_startofpacket),              //          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src0_endofpacket),                //          .endofpacket
		.sink2_ready         (cmd_demux_002_src0_ready),                      //     sink2.ready
		.sink2_valid         (cmd_demux_002_src0_valid),                      //          .valid
		.sink2_channel       (cmd_demux_002_src0_channel),                    //          .channel
		.sink2_data          (cmd_demux_002_src0_data),                       //          .data
		.sink2_startofpacket (cmd_demux_002_src0_startofpacket),              //          .startofpacket
		.sink2_endofpacket   (cmd_demux_002_src0_endofpacket),                //          .endofpacket
		.sink3_ready         (cmd_demux_003_src0_ready),                      //     sink3.ready
		.sink3_valid         (cmd_demux_003_src0_valid),                      //          .valid
		.sink3_channel       (cmd_demux_003_src0_channel),                    //          .channel
		.sink3_data          (cmd_demux_003_src0_data),                       //          .data
		.sink3_startofpacket (cmd_demux_003_src0_startofpacket),              //          .startofpacket
		.sink3_endofpacket   (cmd_demux_003_src0_endofpacket)                 //          .endofpacket
	);

	soc_system_mm_interconnect_2_rsp_demux rsp_demux (
		.clk                (clk_0_clk_clk),                                 //       clk.clk
		.reset              (mm_bridge_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_004_src_ready),                          //      sink.ready
		.sink_channel       (router_004_src_channel),                        //          .channel
		.sink_data          (router_004_src_data),                           //          .data
		.sink_startofpacket (router_004_src_startofpacket),                  //          .startofpacket
		.sink_endofpacket   (router_004_src_endofpacket),                    //          .endofpacket
		.sink_valid         (router_004_src_valid),                          //          .valid
		.src0_ready         (rsp_demux_src0_ready),                          //      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                          //          .valid
		.src0_data          (rsp_demux_src0_data),                           //          .data
		.src0_channel       (rsp_demux_src0_channel),                        //          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                  //          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket),                    //          .endofpacket
		.src1_ready         (rsp_demux_src1_ready),                          //      src1.ready
		.src1_valid         (rsp_demux_src1_valid),                          //          .valid
		.src1_data          (rsp_demux_src1_data),                           //          .data
		.src1_channel       (rsp_demux_src1_channel),                        //          .channel
		.src1_startofpacket (rsp_demux_src1_startofpacket),                  //          .startofpacket
		.src1_endofpacket   (rsp_demux_src1_endofpacket),                    //          .endofpacket
		.src2_ready         (rsp_demux_src2_ready),                          //      src2.ready
		.src2_valid         (rsp_demux_src2_valid),                          //          .valid
		.src2_data          (rsp_demux_src2_data),                           //          .data
		.src2_channel       (rsp_demux_src2_channel),                        //          .channel
		.src2_startofpacket (rsp_demux_src2_startofpacket),                  //          .startofpacket
		.src2_endofpacket   (rsp_demux_src2_endofpacket),                    //          .endofpacket
		.src3_ready         (rsp_demux_src3_ready),                          //      src3.ready
		.src3_valid         (rsp_demux_src3_valid),                          //          .valid
		.src3_data          (rsp_demux_src3_data),                           //          .data
		.src3_channel       (rsp_demux_src3_channel),                        //          .channel
		.src3_startofpacket (rsp_demux_src3_startofpacket),                  //          .startofpacket
		.src3_endofpacket   (rsp_demux_src3_endofpacket)                     //          .endofpacket
	);

	soc_system_mm_interconnect_2_rsp_mux rsp_mux (
		.clk                 (clk_0_clk_clk),                                                       //       clk.clk
		.reset               (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                                                   //       src.ready
		.src_valid           (rsp_mux_src_valid),                                                   //          .valid
		.src_data            (rsp_mux_src_data),                                                    //          .data
		.src_channel         (rsp_mux_src_channel),                                                 //          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                                           //          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                                             //          .endofpacket
		.sink0_ready         (rsp_demux_src0_ready),                                                //     sink0.ready
		.sink0_valid         (rsp_demux_src0_valid),                                                //          .valid
		.sink0_channel       (rsp_demux_src0_channel),                                              //          .channel
		.sink0_data          (rsp_demux_src0_data),                                                 //          .data
		.sink0_startofpacket (rsp_demux_src0_startofpacket),                                        //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src0_endofpacket)                                           //          .endofpacket
	);

	soc_system_mm_interconnect_2_rsp_mux rsp_mux_001 (
		.clk                 (clk_0_clk_clk),                                                       //       clk.clk
		.reset               (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_001_src_ready),                                               //       src.ready
		.src_valid           (rsp_mux_001_src_valid),                                               //          .valid
		.src_data            (rsp_mux_001_src_data),                                                //          .data
		.src_channel         (rsp_mux_001_src_channel),                                             //          .channel
		.src_startofpacket   (rsp_mux_001_src_startofpacket),                                       //          .startofpacket
		.src_endofpacket     (rsp_mux_001_src_endofpacket),                                         //          .endofpacket
		.sink0_ready         (rsp_demux_src1_ready),                                                //     sink0.ready
		.sink0_valid         (rsp_demux_src1_valid),                                                //          .valid
		.sink0_channel       (rsp_demux_src1_channel),                                              //          .channel
		.sink0_data          (rsp_demux_src1_data),                                                 //          .data
		.sink0_startofpacket (rsp_demux_src1_startofpacket),                                        //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src1_endofpacket)                                           //          .endofpacket
	);

	soc_system_mm_interconnect_2_rsp_mux rsp_mux_002 (
		.clk                 (clk_0_clk_clk),                                 //       clk.clk
		.reset               (mm_bridge_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_002_src_ready),                         //       src.ready
		.src_valid           (rsp_mux_002_src_valid),                         //          .valid
		.src_data            (rsp_mux_002_src_data),                          //          .data
		.src_channel         (rsp_mux_002_src_channel),                       //          .channel
		.src_startofpacket   (rsp_mux_002_src_startofpacket),                 //          .startofpacket
		.src_endofpacket     (rsp_mux_002_src_endofpacket),                   //          .endofpacket
		.sink0_ready         (rsp_demux_src2_ready),                          //     sink0.ready
		.sink0_valid         (rsp_demux_src2_valid),                          //          .valid
		.sink0_channel       (rsp_demux_src2_channel),                        //          .channel
		.sink0_data          (rsp_demux_src2_data),                           //          .data
		.sink0_startofpacket (rsp_demux_src2_startofpacket),                  //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src2_endofpacket)                     //          .endofpacket
	);

	soc_system_mm_interconnect_2_rsp_mux rsp_mux_003 (
		.clk                 (clk_0_clk_clk),                                 //       clk.clk
		.reset               (mm_bridge_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_003_src_ready),                         //       src.ready
		.src_valid           (rsp_mux_003_src_valid),                         //          .valid
		.src_data            (rsp_mux_003_src_data),                          //          .data
		.src_channel         (rsp_mux_003_src_channel),                       //          .channel
		.src_startofpacket   (rsp_mux_003_src_startofpacket),                 //          .startofpacket
		.src_endofpacket     (rsp_mux_003_src_endofpacket),                   //          .endofpacket
		.sink0_ready         (rsp_demux_src3_ready),                          //     sink0.ready
		.sink0_valid         (rsp_demux_src3_valid),                          //          .valid
		.sink0_channel       (rsp_demux_src3_channel),                        //          .channel
		.sink0_data          (rsp_demux_src3_data),                           //          .data
		.sink0_startofpacket (rsp_demux_src3_startofpacket),                  //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src3_endofpacket)                     //          .endofpacket
	);

	soc_system_mm_interconnect_2_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter (
		.in_clk_0_clk   (clk_0_clk_clk),                                 // in_clk_0.clk
		.in_rst_0_reset (mm_bridge_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (mm_bridge_0_s0_agent_rdata_fifo_out_data),      //     in_0.data
		.in_0_valid     (mm_bridge_0_s0_agent_rdata_fifo_out_valid),     //         .valid
		.in_0_ready     (mm_bridge_0_s0_agent_rdata_fifo_out_ready),     //         .ready
		.out_0_data     (avalon_st_adapter_out_0_data),                  //    out_0.data
		.out_0_valid    (avalon_st_adapter_out_0_valid),                 //         .valid
		.out_0_ready    (avalon_st_adapter_out_0_ready),                 //         .ready
		.out_0_error    (avalon_st_adapter_out_0_error)                  //         .error
	);

endmodule
