// soc_system_pcie_0_mm_interconnect_1.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 18.1 646

`timescale 1 ps / 1 ps
module soc_system_pcie_0_mm_interconnect_1 (
		input  wire         clk_clk_clk,                                                    //                                                  clk_clk.clk
		input  wire         custom_reset_synchronizer_0_clock_out_clk,                      //                    custom_reset_synchronizer_0_clock_out.clk
		input  wire         pcie_hip_avmm_coreclkout_clk,                                   //                                 pcie_hip_avmm_coreclkout.clk
		input  wire         pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset,                //                pb_lwh2f_pcie_reset_reset_bridge_in_reset.reset
		input  wire         pcie_hip_avmm_Cra_translator_reset_reset_bridge_in_reset_reset, // pcie_hip_avmm_Cra_translator_reset_reset_bridge_in_reset.reset
		input  wire         performance_counter_0_reset_reset_bridge_in_reset_reset,        //        performance_counter_0_reset_reset_bridge_in_reset.reset
		input  wire [14:0]  pb_lwh2f_pcie_m0_address,                                       //                                         pb_lwh2f_pcie_m0.address
		output wire         pb_lwh2f_pcie_m0_waitrequest,                                   //                                                         .waitrequest
		input  wire [0:0]   pb_lwh2f_pcie_m0_burstcount,                                    //                                                         .burstcount
		input  wire [3:0]   pb_lwh2f_pcie_m0_byteenable,                                    //                                                         .byteenable
		input  wire         pb_lwh2f_pcie_m0_read,                                          //                                                         .read
		output wire [31:0]  pb_lwh2f_pcie_m0_readdata,                                      //                                                         .readdata
		output wire         pb_lwh2f_pcie_m0_readdatavalid,                                 //                                                         .readdatavalid
		input  wire         pb_lwh2f_pcie_m0_write,                                         //                                                         .write
		input  wire [31:0]  pb_lwh2f_pcie_m0_writedata,                                     //                                                         .writedata
		input  wire         pb_lwh2f_pcie_m0_debugaccess,                                   //                                                         .debugaccess
		input  wire [14:0]  pb_rxm_2_msi_m0_address,                                        //                                          pb_rxm_2_msi_m0.address
		output wire         pb_rxm_2_msi_m0_waitrequest,                                    //                                                         .waitrequest
		input  wire [0:0]   pb_rxm_2_msi_m0_burstcount,                                     //                                                         .burstcount
		input  wire [3:0]   pb_rxm_2_msi_m0_byteenable,                                     //                                                         .byteenable
		input  wire         pb_rxm_2_msi_m0_read,                                           //                                                         .read
		output wire [31:0]  pb_rxm_2_msi_m0_readdata,                                       //                                                         .readdata
		output wire         pb_rxm_2_msi_m0_readdatavalid,                                  //                                                         .readdatavalid
		input  wire         pb_rxm_2_msi_m0_write,                                          //                                                         .write
		input  wire [31:0]  pb_rxm_2_msi_m0_writedata,                                      //                                                         .writedata
		input  wire         pb_rxm_2_msi_m0_debugaccess,                                    //                                                         .debugaccess
		output wire [2:0]   msgdma_0_csr_address,                                           //                                             msgdma_0_csr.address
		output wire         msgdma_0_csr_write,                                             //                                                         .write
		output wire         msgdma_0_csr_read,                                              //                                                         .read
		input  wire [31:0]  msgdma_0_csr_readdata,                                          //                                                         .readdata
		output wire [31:0]  msgdma_0_csr_writedata,                                         //                                                         .writedata
		output wire [3:0]   msgdma_0_csr_byteenable,                                        //                                                         .byteenable
		output wire         msgdma_0_descriptor_slave_write,                                //                                msgdma_0_descriptor_slave.write
		output wire [127:0] msgdma_0_descriptor_slave_writedata,                            //                                                         .writedata
		output wire [15:0]  msgdma_0_descriptor_slave_byteenable,                           //                                                         .byteenable
		input  wire         msgdma_0_descriptor_slave_waitrequest,                          //                                                         .waitrequest
		output wire [1:0]   msi_to_gic_gen_0_csr_address,                                   //                                     msi_to_gic_gen_0_csr.address
		output wire         msi_to_gic_gen_0_csr_write,                                     //                                                         .write
		output wire         msi_to_gic_gen_0_csr_read,                                      //                                                         .read
		input  wire [31:0]  msi_to_gic_gen_0_csr_readdata,                                  //                                                         .readdata
		output wire [31:0]  msi_to_gic_gen_0_csr_writedata,                                 //                                                         .writedata
		output wire [4:0]   msi_to_gic_gen_0_vector_slave_address,                          //                            msi_to_gic_gen_0_vector_slave.address
		output wire         msi_to_gic_gen_0_vector_slave_write,                            //                                                         .write
		output wire         msi_to_gic_gen_0_vector_slave_read,                             //                                                         .read
		input  wire [31:0]  msi_to_gic_gen_0_vector_slave_readdata,                         //                                                         .readdata
		output wire [31:0]  msi_to_gic_gen_0_vector_slave_writedata,                        //                                                         .writedata
		output wire [13:0]  pcie_hip_avmm_Cra_address,                                      //                                        pcie_hip_avmm_Cra.address
		output wire         pcie_hip_avmm_Cra_write,                                        //                                                         .write
		output wire         pcie_hip_avmm_Cra_read,                                         //                                                         .read
		input  wire [31:0]  pcie_hip_avmm_Cra_readdata,                                     //                                                         .readdata
		output wire [31:0]  pcie_hip_avmm_Cra_writedata,                                    //                                                         .writedata
		output wire [3:0]   pcie_hip_avmm_Cra_byteenable,                                   //                                                         .byteenable
		input  wire         pcie_hip_avmm_Cra_waitrequest,                                  //                                                         .waitrequest
		output wire         pcie_hip_avmm_Cra_chipselect,                                   //                                                         .chipselect
		output wire [2:0]   performance_counter_0_control_slave_address,                    //                      performance_counter_0_control_slave.address
		output wire         performance_counter_0_control_slave_write,                      //                                                         .write
		input  wire [31:0]  performance_counter_0_control_slave_readdata,                   //                                                         .readdata
		output wire [31:0]  performance_counter_0_control_slave_writedata,                  //                                                         .writedata
		output wire         performance_counter_0_control_slave_begintransfer               //                                                         .begintransfer
	);

	wire          pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_waitrequest;    // pb_lwh2f_pcie_m0_agent:av_waitrequest -> pb_lwh2f_pcie_m0_translator:uav_waitrequest
	wire   [31:0] pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_readdata;       // pb_lwh2f_pcie_m0_agent:av_readdata -> pb_lwh2f_pcie_m0_translator:uav_readdata
	wire          pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_debugaccess;    // pb_lwh2f_pcie_m0_translator:uav_debugaccess -> pb_lwh2f_pcie_m0_agent:av_debugaccess
	wire   [14:0] pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_address;        // pb_lwh2f_pcie_m0_translator:uav_address -> pb_lwh2f_pcie_m0_agent:av_address
	wire          pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_read;           // pb_lwh2f_pcie_m0_translator:uav_read -> pb_lwh2f_pcie_m0_agent:av_read
	wire    [3:0] pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_byteenable;     // pb_lwh2f_pcie_m0_translator:uav_byteenable -> pb_lwh2f_pcie_m0_agent:av_byteenable
	wire          pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_readdatavalid;  // pb_lwh2f_pcie_m0_agent:av_readdatavalid -> pb_lwh2f_pcie_m0_translator:uav_readdatavalid
	wire          pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_lock;           // pb_lwh2f_pcie_m0_translator:uav_lock -> pb_lwh2f_pcie_m0_agent:av_lock
	wire          pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_write;          // pb_lwh2f_pcie_m0_translator:uav_write -> pb_lwh2f_pcie_m0_agent:av_write
	wire   [31:0] pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_writedata;      // pb_lwh2f_pcie_m0_translator:uav_writedata -> pb_lwh2f_pcie_m0_agent:av_writedata
	wire    [2:0] pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_burstcount;     // pb_lwh2f_pcie_m0_translator:uav_burstcount -> pb_lwh2f_pcie_m0_agent:av_burstcount
	wire          pb_rxm_2_msi_m0_translator_avalon_universal_master_0_waitrequest;     // pb_rxm_2_msi_m0_agent:av_waitrequest -> pb_rxm_2_msi_m0_translator:uav_waitrequest
	wire   [31:0] pb_rxm_2_msi_m0_translator_avalon_universal_master_0_readdata;        // pb_rxm_2_msi_m0_agent:av_readdata -> pb_rxm_2_msi_m0_translator:uav_readdata
	wire          pb_rxm_2_msi_m0_translator_avalon_universal_master_0_debugaccess;     // pb_rxm_2_msi_m0_translator:uav_debugaccess -> pb_rxm_2_msi_m0_agent:av_debugaccess
	wire   [14:0] pb_rxm_2_msi_m0_translator_avalon_universal_master_0_address;         // pb_rxm_2_msi_m0_translator:uav_address -> pb_rxm_2_msi_m0_agent:av_address
	wire          pb_rxm_2_msi_m0_translator_avalon_universal_master_0_read;            // pb_rxm_2_msi_m0_translator:uav_read -> pb_rxm_2_msi_m0_agent:av_read
	wire    [3:0] pb_rxm_2_msi_m0_translator_avalon_universal_master_0_byteenable;      // pb_rxm_2_msi_m0_translator:uav_byteenable -> pb_rxm_2_msi_m0_agent:av_byteenable
	wire          pb_rxm_2_msi_m0_translator_avalon_universal_master_0_readdatavalid;   // pb_rxm_2_msi_m0_agent:av_readdatavalid -> pb_rxm_2_msi_m0_translator:uav_readdatavalid
	wire          pb_rxm_2_msi_m0_translator_avalon_universal_master_0_lock;            // pb_rxm_2_msi_m0_translator:uav_lock -> pb_rxm_2_msi_m0_agent:av_lock
	wire          pb_rxm_2_msi_m0_translator_avalon_universal_master_0_write;           // pb_rxm_2_msi_m0_translator:uav_write -> pb_rxm_2_msi_m0_agent:av_write
	wire   [31:0] pb_rxm_2_msi_m0_translator_avalon_universal_master_0_writedata;       // pb_rxm_2_msi_m0_translator:uav_writedata -> pb_rxm_2_msi_m0_agent:av_writedata
	wire    [2:0] pb_rxm_2_msi_m0_translator_avalon_universal_master_0_burstcount;      // pb_rxm_2_msi_m0_translator:uav_burstcount -> pb_rxm_2_msi_m0_agent:av_burstcount
	wire          rsp_mux_001_src_valid;                                                // rsp_mux_001:src_valid -> pb_rxm_2_msi_m0_agent:rp_valid
	wire   [90:0] rsp_mux_001_src_data;                                                 // rsp_mux_001:src_data -> pb_rxm_2_msi_m0_agent:rp_data
	wire          rsp_mux_001_src_ready;                                                // pb_rxm_2_msi_m0_agent:rp_ready -> rsp_mux_001:src_ready
	wire    [5:0] rsp_mux_001_src_channel;                                              // rsp_mux_001:src_channel -> pb_rxm_2_msi_m0_agent:rp_channel
	wire          rsp_mux_001_src_startofpacket;                                        // rsp_mux_001:src_startofpacket -> pb_rxm_2_msi_m0_agent:rp_startofpacket
	wire          rsp_mux_001_src_endofpacket;                                          // rsp_mux_001:src_endofpacket -> pb_rxm_2_msi_m0_agent:rp_endofpacket
	wire   [31:0] pcie_hip_avmm_cra_agent_m0_readdata;                                  // pcie_hip_avmm_Cra_translator:uav_readdata -> pcie_hip_avmm_Cra_agent:m0_readdata
	wire          pcie_hip_avmm_cra_agent_m0_waitrequest;                               // pcie_hip_avmm_Cra_translator:uav_waitrequest -> pcie_hip_avmm_Cra_agent:m0_waitrequest
	wire          pcie_hip_avmm_cra_agent_m0_debugaccess;                               // pcie_hip_avmm_Cra_agent:m0_debugaccess -> pcie_hip_avmm_Cra_translator:uav_debugaccess
	wire   [14:0] pcie_hip_avmm_cra_agent_m0_address;                                   // pcie_hip_avmm_Cra_agent:m0_address -> pcie_hip_avmm_Cra_translator:uav_address
	wire    [3:0] pcie_hip_avmm_cra_agent_m0_byteenable;                                // pcie_hip_avmm_Cra_agent:m0_byteenable -> pcie_hip_avmm_Cra_translator:uav_byteenable
	wire          pcie_hip_avmm_cra_agent_m0_read;                                      // pcie_hip_avmm_Cra_agent:m0_read -> pcie_hip_avmm_Cra_translator:uav_read
	wire          pcie_hip_avmm_cra_agent_m0_readdatavalid;                             // pcie_hip_avmm_Cra_translator:uav_readdatavalid -> pcie_hip_avmm_Cra_agent:m0_readdatavalid
	wire          pcie_hip_avmm_cra_agent_m0_lock;                                      // pcie_hip_avmm_Cra_agent:m0_lock -> pcie_hip_avmm_Cra_translator:uav_lock
	wire   [31:0] pcie_hip_avmm_cra_agent_m0_writedata;                                 // pcie_hip_avmm_Cra_agent:m0_writedata -> pcie_hip_avmm_Cra_translator:uav_writedata
	wire          pcie_hip_avmm_cra_agent_m0_write;                                     // pcie_hip_avmm_Cra_agent:m0_write -> pcie_hip_avmm_Cra_translator:uav_write
	wire    [2:0] pcie_hip_avmm_cra_agent_m0_burstcount;                                // pcie_hip_avmm_Cra_agent:m0_burstcount -> pcie_hip_avmm_Cra_translator:uav_burstcount
	wire          pcie_hip_avmm_cra_agent_rf_source_valid;                              // pcie_hip_avmm_Cra_agent:rf_source_valid -> pcie_hip_avmm_Cra_agent_rsp_fifo:in_valid
	wire   [91:0] pcie_hip_avmm_cra_agent_rf_source_data;                               // pcie_hip_avmm_Cra_agent:rf_source_data -> pcie_hip_avmm_Cra_agent_rsp_fifo:in_data
	wire          pcie_hip_avmm_cra_agent_rf_source_ready;                              // pcie_hip_avmm_Cra_agent_rsp_fifo:in_ready -> pcie_hip_avmm_Cra_agent:rf_source_ready
	wire          pcie_hip_avmm_cra_agent_rf_source_startofpacket;                      // pcie_hip_avmm_Cra_agent:rf_source_startofpacket -> pcie_hip_avmm_Cra_agent_rsp_fifo:in_startofpacket
	wire          pcie_hip_avmm_cra_agent_rf_source_endofpacket;                        // pcie_hip_avmm_Cra_agent:rf_source_endofpacket -> pcie_hip_avmm_Cra_agent_rsp_fifo:in_endofpacket
	wire          pcie_hip_avmm_cra_agent_rsp_fifo_out_valid;                           // pcie_hip_avmm_Cra_agent_rsp_fifo:out_valid -> pcie_hip_avmm_Cra_agent:rf_sink_valid
	wire   [91:0] pcie_hip_avmm_cra_agent_rsp_fifo_out_data;                            // pcie_hip_avmm_Cra_agent_rsp_fifo:out_data -> pcie_hip_avmm_Cra_agent:rf_sink_data
	wire          pcie_hip_avmm_cra_agent_rsp_fifo_out_ready;                           // pcie_hip_avmm_Cra_agent:rf_sink_ready -> pcie_hip_avmm_Cra_agent_rsp_fifo:out_ready
	wire          pcie_hip_avmm_cra_agent_rsp_fifo_out_startofpacket;                   // pcie_hip_avmm_Cra_agent_rsp_fifo:out_startofpacket -> pcie_hip_avmm_Cra_agent:rf_sink_startofpacket
	wire          pcie_hip_avmm_cra_agent_rsp_fifo_out_endofpacket;                     // pcie_hip_avmm_Cra_agent_rsp_fifo:out_endofpacket -> pcie_hip_avmm_Cra_agent:rf_sink_endofpacket
	wire          pcie_hip_avmm_cra_agent_rdata_fifo_src_valid;                         // pcie_hip_avmm_Cra_agent:rdata_fifo_src_valid -> pcie_hip_avmm_Cra_agent_rdata_fifo:in_valid
	wire   [33:0] pcie_hip_avmm_cra_agent_rdata_fifo_src_data;                          // pcie_hip_avmm_Cra_agent:rdata_fifo_src_data -> pcie_hip_avmm_Cra_agent_rdata_fifo:in_data
	wire          pcie_hip_avmm_cra_agent_rdata_fifo_src_ready;                         // pcie_hip_avmm_Cra_agent_rdata_fifo:in_ready -> pcie_hip_avmm_Cra_agent:rdata_fifo_src_ready
	wire   [31:0] performance_counter_0_control_slave_agent_m0_readdata;                // performance_counter_0_control_slave_translator:uav_readdata -> performance_counter_0_control_slave_agent:m0_readdata
	wire          performance_counter_0_control_slave_agent_m0_waitrequest;             // performance_counter_0_control_slave_translator:uav_waitrequest -> performance_counter_0_control_slave_agent:m0_waitrequest
	wire          performance_counter_0_control_slave_agent_m0_debugaccess;             // performance_counter_0_control_slave_agent:m0_debugaccess -> performance_counter_0_control_slave_translator:uav_debugaccess
	wire   [14:0] performance_counter_0_control_slave_agent_m0_address;                 // performance_counter_0_control_slave_agent:m0_address -> performance_counter_0_control_slave_translator:uav_address
	wire    [3:0] performance_counter_0_control_slave_agent_m0_byteenable;              // performance_counter_0_control_slave_agent:m0_byteenable -> performance_counter_0_control_slave_translator:uav_byteenable
	wire          performance_counter_0_control_slave_agent_m0_read;                    // performance_counter_0_control_slave_agent:m0_read -> performance_counter_0_control_slave_translator:uav_read
	wire          performance_counter_0_control_slave_agent_m0_readdatavalid;           // performance_counter_0_control_slave_translator:uav_readdatavalid -> performance_counter_0_control_slave_agent:m0_readdatavalid
	wire          performance_counter_0_control_slave_agent_m0_lock;                    // performance_counter_0_control_slave_agent:m0_lock -> performance_counter_0_control_slave_translator:uav_lock
	wire   [31:0] performance_counter_0_control_slave_agent_m0_writedata;               // performance_counter_0_control_slave_agent:m0_writedata -> performance_counter_0_control_slave_translator:uav_writedata
	wire          performance_counter_0_control_slave_agent_m0_write;                   // performance_counter_0_control_slave_agent:m0_write -> performance_counter_0_control_slave_translator:uav_write
	wire    [2:0] performance_counter_0_control_slave_agent_m0_burstcount;              // performance_counter_0_control_slave_agent:m0_burstcount -> performance_counter_0_control_slave_translator:uav_burstcount
	wire          performance_counter_0_control_slave_agent_rf_source_valid;            // performance_counter_0_control_slave_agent:rf_source_valid -> performance_counter_0_control_slave_agent_rsp_fifo:in_valid
	wire   [91:0] performance_counter_0_control_slave_agent_rf_source_data;             // performance_counter_0_control_slave_agent:rf_source_data -> performance_counter_0_control_slave_agent_rsp_fifo:in_data
	wire          performance_counter_0_control_slave_agent_rf_source_ready;            // performance_counter_0_control_slave_agent_rsp_fifo:in_ready -> performance_counter_0_control_slave_agent:rf_source_ready
	wire          performance_counter_0_control_slave_agent_rf_source_startofpacket;    // performance_counter_0_control_slave_agent:rf_source_startofpacket -> performance_counter_0_control_slave_agent_rsp_fifo:in_startofpacket
	wire          performance_counter_0_control_slave_agent_rf_source_endofpacket;      // performance_counter_0_control_slave_agent:rf_source_endofpacket -> performance_counter_0_control_slave_agent_rsp_fifo:in_endofpacket
	wire          performance_counter_0_control_slave_agent_rsp_fifo_out_valid;         // performance_counter_0_control_slave_agent_rsp_fifo:out_valid -> performance_counter_0_control_slave_agent:rf_sink_valid
	wire   [91:0] performance_counter_0_control_slave_agent_rsp_fifo_out_data;          // performance_counter_0_control_slave_agent_rsp_fifo:out_data -> performance_counter_0_control_slave_agent:rf_sink_data
	wire          performance_counter_0_control_slave_agent_rsp_fifo_out_ready;         // performance_counter_0_control_slave_agent:rf_sink_ready -> performance_counter_0_control_slave_agent_rsp_fifo:out_ready
	wire          performance_counter_0_control_slave_agent_rsp_fifo_out_startofpacket; // performance_counter_0_control_slave_agent_rsp_fifo:out_startofpacket -> performance_counter_0_control_slave_agent:rf_sink_startofpacket
	wire          performance_counter_0_control_slave_agent_rsp_fifo_out_endofpacket;   // performance_counter_0_control_slave_agent_rsp_fifo:out_endofpacket -> performance_counter_0_control_slave_agent:rf_sink_endofpacket
	wire          performance_counter_0_control_slave_agent_rdata_fifo_src_valid;       // performance_counter_0_control_slave_agent:rdata_fifo_src_valid -> performance_counter_0_control_slave_agent_rdata_fifo:in_valid
	wire   [33:0] performance_counter_0_control_slave_agent_rdata_fifo_src_data;        // performance_counter_0_control_slave_agent:rdata_fifo_src_data -> performance_counter_0_control_slave_agent_rdata_fifo:in_data
	wire          performance_counter_0_control_slave_agent_rdata_fifo_src_ready;       // performance_counter_0_control_slave_agent_rdata_fifo:in_ready -> performance_counter_0_control_slave_agent:rdata_fifo_src_ready
	wire   [31:0] msgdma_0_csr_agent_m0_readdata;                                       // msgdma_0_csr_translator:uav_readdata -> msgdma_0_csr_agent:m0_readdata
	wire          msgdma_0_csr_agent_m0_waitrequest;                                    // msgdma_0_csr_translator:uav_waitrequest -> msgdma_0_csr_agent:m0_waitrequest
	wire          msgdma_0_csr_agent_m0_debugaccess;                                    // msgdma_0_csr_agent:m0_debugaccess -> msgdma_0_csr_translator:uav_debugaccess
	wire   [14:0] msgdma_0_csr_agent_m0_address;                                        // msgdma_0_csr_agent:m0_address -> msgdma_0_csr_translator:uav_address
	wire    [3:0] msgdma_0_csr_agent_m0_byteenable;                                     // msgdma_0_csr_agent:m0_byteenable -> msgdma_0_csr_translator:uav_byteenable
	wire          msgdma_0_csr_agent_m0_read;                                           // msgdma_0_csr_agent:m0_read -> msgdma_0_csr_translator:uav_read
	wire          msgdma_0_csr_agent_m0_readdatavalid;                                  // msgdma_0_csr_translator:uav_readdatavalid -> msgdma_0_csr_agent:m0_readdatavalid
	wire          msgdma_0_csr_agent_m0_lock;                                           // msgdma_0_csr_agent:m0_lock -> msgdma_0_csr_translator:uav_lock
	wire   [31:0] msgdma_0_csr_agent_m0_writedata;                                      // msgdma_0_csr_agent:m0_writedata -> msgdma_0_csr_translator:uav_writedata
	wire          msgdma_0_csr_agent_m0_write;                                          // msgdma_0_csr_agent:m0_write -> msgdma_0_csr_translator:uav_write
	wire    [2:0] msgdma_0_csr_agent_m0_burstcount;                                     // msgdma_0_csr_agent:m0_burstcount -> msgdma_0_csr_translator:uav_burstcount
	wire          msgdma_0_csr_agent_rf_source_valid;                                   // msgdma_0_csr_agent:rf_source_valid -> msgdma_0_csr_agent_rsp_fifo:in_valid
	wire   [91:0] msgdma_0_csr_agent_rf_source_data;                                    // msgdma_0_csr_agent:rf_source_data -> msgdma_0_csr_agent_rsp_fifo:in_data
	wire          msgdma_0_csr_agent_rf_source_ready;                                   // msgdma_0_csr_agent_rsp_fifo:in_ready -> msgdma_0_csr_agent:rf_source_ready
	wire          msgdma_0_csr_agent_rf_source_startofpacket;                           // msgdma_0_csr_agent:rf_source_startofpacket -> msgdma_0_csr_agent_rsp_fifo:in_startofpacket
	wire          msgdma_0_csr_agent_rf_source_endofpacket;                             // msgdma_0_csr_agent:rf_source_endofpacket -> msgdma_0_csr_agent_rsp_fifo:in_endofpacket
	wire          msgdma_0_csr_agent_rsp_fifo_out_valid;                                // msgdma_0_csr_agent_rsp_fifo:out_valid -> msgdma_0_csr_agent:rf_sink_valid
	wire   [91:0] msgdma_0_csr_agent_rsp_fifo_out_data;                                 // msgdma_0_csr_agent_rsp_fifo:out_data -> msgdma_0_csr_agent:rf_sink_data
	wire          msgdma_0_csr_agent_rsp_fifo_out_ready;                                // msgdma_0_csr_agent:rf_sink_ready -> msgdma_0_csr_agent_rsp_fifo:out_ready
	wire          msgdma_0_csr_agent_rsp_fifo_out_startofpacket;                        // msgdma_0_csr_agent_rsp_fifo:out_startofpacket -> msgdma_0_csr_agent:rf_sink_startofpacket
	wire          msgdma_0_csr_agent_rsp_fifo_out_endofpacket;                          // msgdma_0_csr_agent_rsp_fifo:out_endofpacket -> msgdma_0_csr_agent:rf_sink_endofpacket
	wire   [31:0] msi_to_gic_gen_0_csr_agent_m0_readdata;                               // msi_to_gic_gen_0_csr_translator:uav_readdata -> msi_to_gic_gen_0_csr_agent:m0_readdata
	wire          msi_to_gic_gen_0_csr_agent_m0_waitrequest;                            // msi_to_gic_gen_0_csr_translator:uav_waitrequest -> msi_to_gic_gen_0_csr_agent:m0_waitrequest
	wire          msi_to_gic_gen_0_csr_agent_m0_debugaccess;                            // msi_to_gic_gen_0_csr_agent:m0_debugaccess -> msi_to_gic_gen_0_csr_translator:uav_debugaccess
	wire   [14:0] msi_to_gic_gen_0_csr_agent_m0_address;                                // msi_to_gic_gen_0_csr_agent:m0_address -> msi_to_gic_gen_0_csr_translator:uav_address
	wire    [3:0] msi_to_gic_gen_0_csr_agent_m0_byteenable;                             // msi_to_gic_gen_0_csr_agent:m0_byteenable -> msi_to_gic_gen_0_csr_translator:uav_byteenable
	wire          msi_to_gic_gen_0_csr_agent_m0_read;                                   // msi_to_gic_gen_0_csr_agent:m0_read -> msi_to_gic_gen_0_csr_translator:uav_read
	wire          msi_to_gic_gen_0_csr_agent_m0_readdatavalid;                          // msi_to_gic_gen_0_csr_translator:uav_readdatavalid -> msi_to_gic_gen_0_csr_agent:m0_readdatavalid
	wire          msi_to_gic_gen_0_csr_agent_m0_lock;                                   // msi_to_gic_gen_0_csr_agent:m0_lock -> msi_to_gic_gen_0_csr_translator:uav_lock
	wire   [31:0] msi_to_gic_gen_0_csr_agent_m0_writedata;                              // msi_to_gic_gen_0_csr_agent:m0_writedata -> msi_to_gic_gen_0_csr_translator:uav_writedata
	wire          msi_to_gic_gen_0_csr_agent_m0_write;                                  // msi_to_gic_gen_0_csr_agent:m0_write -> msi_to_gic_gen_0_csr_translator:uav_write
	wire    [2:0] msi_to_gic_gen_0_csr_agent_m0_burstcount;                             // msi_to_gic_gen_0_csr_agent:m0_burstcount -> msi_to_gic_gen_0_csr_translator:uav_burstcount
	wire          msi_to_gic_gen_0_csr_agent_rf_source_valid;                           // msi_to_gic_gen_0_csr_agent:rf_source_valid -> msi_to_gic_gen_0_csr_agent_rsp_fifo:in_valid
	wire   [91:0] msi_to_gic_gen_0_csr_agent_rf_source_data;                            // msi_to_gic_gen_0_csr_agent:rf_source_data -> msi_to_gic_gen_0_csr_agent_rsp_fifo:in_data
	wire          msi_to_gic_gen_0_csr_agent_rf_source_ready;                           // msi_to_gic_gen_0_csr_agent_rsp_fifo:in_ready -> msi_to_gic_gen_0_csr_agent:rf_source_ready
	wire          msi_to_gic_gen_0_csr_agent_rf_source_startofpacket;                   // msi_to_gic_gen_0_csr_agent:rf_source_startofpacket -> msi_to_gic_gen_0_csr_agent_rsp_fifo:in_startofpacket
	wire          msi_to_gic_gen_0_csr_agent_rf_source_endofpacket;                     // msi_to_gic_gen_0_csr_agent:rf_source_endofpacket -> msi_to_gic_gen_0_csr_agent_rsp_fifo:in_endofpacket
	wire          msi_to_gic_gen_0_csr_agent_rsp_fifo_out_valid;                        // msi_to_gic_gen_0_csr_agent_rsp_fifo:out_valid -> msi_to_gic_gen_0_csr_agent:rf_sink_valid
	wire   [91:0] msi_to_gic_gen_0_csr_agent_rsp_fifo_out_data;                         // msi_to_gic_gen_0_csr_agent_rsp_fifo:out_data -> msi_to_gic_gen_0_csr_agent:rf_sink_data
	wire          msi_to_gic_gen_0_csr_agent_rsp_fifo_out_ready;                        // msi_to_gic_gen_0_csr_agent:rf_sink_ready -> msi_to_gic_gen_0_csr_agent_rsp_fifo:out_ready
	wire          msi_to_gic_gen_0_csr_agent_rsp_fifo_out_startofpacket;                // msi_to_gic_gen_0_csr_agent_rsp_fifo:out_startofpacket -> msi_to_gic_gen_0_csr_agent:rf_sink_startofpacket
	wire          msi_to_gic_gen_0_csr_agent_rsp_fifo_out_endofpacket;                  // msi_to_gic_gen_0_csr_agent_rsp_fifo:out_endofpacket -> msi_to_gic_gen_0_csr_agent:rf_sink_endofpacket
	wire          msi_to_gic_gen_0_csr_agent_rdata_fifo_src_valid;                      // msi_to_gic_gen_0_csr_agent:rdata_fifo_src_valid -> msi_to_gic_gen_0_csr_agent_rdata_fifo:in_valid
	wire   [33:0] msi_to_gic_gen_0_csr_agent_rdata_fifo_src_data;                       // msi_to_gic_gen_0_csr_agent:rdata_fifo_src_data -> msi_to_gic_gen_0_csr_agent_rdata_fifo:in_data
	wire          msi_to_gic_gen_0_csr_agent_rdata_fifo_src_ready;                      // msi_to_gic_gen_0_csr_agent_rdata_fifo:in_ready -> msi_to_gic_gen_0_csr_agent:rdata_fifo_src_ready
	wire  [127:0] msgdma_0_descriptor_slave_agent_m0_readdata;                          // msgdma_0_descriptor_slave_translator:uav_readdata -> msgdma_0_descriptor_slave_agent:m0_readdata
	wire          msgdma_0_descriptor_slave_agent_m0_waitrequest;                       // msgdma_0_descriptor_slave_translator:uav_waitrequest -> msgdma_0_descriptor_slave_agent:m0_waitrequest
	wire          msgdma_0_descriptor_slave_agent_m0_debugaccess;                       // msgdma_0_descriptor_slave_agent:m0_debugaccess -> msgdma_0_descriptor_slave_translator:uav_debugaccess
	wire   [14:0] msgdma_0_descriptor_slave_agent_m0_address;                           // msgdma_0_descriptor_slave_agent:m0_address -> msgdma_0_descriptor_slave_translator:uav_address
	wire   [15:0] msgdma_0_descriptor_slave_agent_m0_byteenable;                        // msgdma_0_descriptor_slave_agent:m0_byteenable -> msgdma_0_descriptor_slave_translator:uav_byteenable
	wire          msgdma_0_descriptor_slave_agent_m0_read;                              // msgdma_0_descriptor_slave_agent:m0_read -> msgdma_0_descriptor_slave_translator:uav_read
	wire          msgdma_0_descriptor_slave_agent_m0_readdatavalid;                     // msgdma_0_descriptor_slave_translator:uav_readdatavalid -> msgdma_0_descriptor_slave_agent:m0_readdatavalid
	wire          msgdma_0_descriptor_slave_agent_m0_lock;                              // msgdma_0_descriptor_slave_agent:m0_lock -> msgdma_0_descriptor_slave_translator:uav_lock
	wire  [127:0] msgdma_0_descriptor_slave_agent_m0_writedata;                         // msgdma_0_descriptor_slave_agent:m0_writedata -> msgdma_0_descriptor_slave_translator:uav_writedata
	wire          msgdma_0_descriptor_slave_agent_m0_write;                             // msgdma_0_descriptor_slave_agent:m0_write -> msgdma_0_descriptor_slave_translator:uav_write
	wire    [4:0] msgdma_0_descriptor_slave_agent_m0_burstcount;                        // msgdma_0_descriptor_slave_agent:m0_burstcount -> msgdma_0_descriptor_slave_translator:uav_burstcount
	wire          msgdma_0_descriptor_slave_agent_rf_source_valid;                      // msgdma_0_descriptor_slave_agent:rf_source_valid -> msgdma_0_descriptor_slave_agent_rsp_fifo:in_valid
	wire  [199:0] msgdma_0_descriptor_slave_agent_rf_source_data;                       // msgdma_0_descriptor_slave_agent:rf_source_data -> msgdma_0_descriptor_slave_agent_rsp_fifo:in_data
	wire          msgdma_0_descriptor_slave_agent_rf_source_ready;                      // msgdma_0_descriptor_slave_agent_rsp_fifo:in_ready -> msgdma_0_descriptor_slave_agent:rf_source_ready
	wire          msgdma_0_descriptor_slave_agent_rf_source_startofpacket;              // msgdma_0_descriptor_slave_agent:rf_source_startofpacket -> msgdma_0_descriptor_slave_agent_rsp_fifo:in_startofpacket
	wire          msgdma_0_descriptor_slave_agent_rf_source_endofpacket;                // msgdma_0_descriptor_slave_agent:rf_source_endofpacket -> msgdma_0_descriptor_slave_agent_rsp_fifo:in_endofpacket
	wire          msgdma_0_descriptor_slave_agent_rsp_fifo_out_valid;                   // msgdma_0_descriptor_slave_agent_rsp_fifo:out_valid -> msgdma_0_descriptor_slave_agent:rf_sink_valid
	wire  [199:0] msgdma_0_descriptor_slave_agent_rsp_fifo_out_data;                    // msgdma_0_descriptor_slave_agent_rsp_fifo:out_data -> msgdma_0_descriptor_slave_agent:rf_sink_data
	wire          msgdma_0_descriptor_slave_agent_rsp_fifo_out_ready;                   // msgdma_0_descriptor_slave_agent:rf_sink_ready -> msgdma_0_descriptor_slave_agent_rsp_fifo:out_ready
	wire          msgdma_0_descriptor_slave_agent_rsp_fifo_out_startofpacket;           // msgdma_0_descriptor_slave_agent_rsp_fifo:out_startofpacket -> msgdma_0_descriptor_slave_agent:rf_sink_startofpacket
	wire          msgdma_0_descriptor_slave_agent_rsp_fifo_out_endofpacket;             // msgdma_0_descriptor_slave_agent_rsp_fifo:out_endofpacket -> msgdma_0_descriptor_slave_agent:rf_sink_endofpacket
	wire   [31:0] msi_to_gic_gen_0_vector_slave_agent_m0_readdata;                      // msi_to_gic_gen_0_vector_slave_translator:uav_readdata -> msi_to_gic_gen_0_vector_slave_agent:m0_readdata
	wire          msi_to_gic_gen_0_vector_slave_agent_m0_waitrequest;                   // msi_to_gic_gen_0_vector_slave_translator:uav_waitrequest -> msi_to_gic_gen_0_vector_slave_agent:m0_waitrequest
	wire          msi_to_gic_gen_0_vector_slave_agent_m0_debugaccess;                   // msi_to_gic_gen_0_vector_slave_agent:m0_debugaccess -> msi_to_gic_gen_0_vector_slave_translator:uav_debugaccess
	wire   [14:0] msi_to_gic_gen_0_vector_slave_agent_m0_address;                       // msi_to_gic_gen_0_vector_slave_agent:m0_address -> msi_to_gic_gen_0_vector_slave_translator:uav_address
	wire    [3:0] msi_to_gic_gen_0_vector_slave_agent_m0_byteenable;                    // msi_to_gic_gen_0_vector_slave_agent:m0_byteenable -> msi_to_gic_gen_0_vector_slave_translator:uav_byteenable
	wire          msi_to_gic_gen_0_vector_slave_agent_m0_read;                          // msi_to_gic_gen_0_vector_slave_agent:m0_read -> msi_to_gic_gen_0_vector_slave_translator:uav_read
	wire          msi_to_gic_gen_0_vector_slave_agent_m0_readdatavalid;                 // msi_to_gic_gen_0_vector_slave_translator:uav_readdatavalid -> msi_to_gic_gen_0_vector_slave_agent:m0_readdatavalid
	wire          msi_to_gic_gen_0_vector_slave_agent_m0_lock;                          // msi_to_gic_gen_0_vector_slave_agent:m0_lock -> msi_to_gic_gen_0_vector_slave_translator:uav_lock
	wire   [31:0] msi_to_gic_gen_0_vector_slave_agent_m0_writedata;                     // msi_to_gic_gen_0_vector_slave_agent:m0_writedata -> msi_to_gic_gen_0_vector_slave_translator:uav_writedata
	wire          msi_to_gic_gen_0_vector_slave_agent_m0_write;                         // msi_to_gic_gen_0_vector_slave_agent:m0_write -> msi_to_gic_gen_0_vector_slave_translator:uav_write
	wire    [2:0] msi_to_gic_gen_0_vector_slave_agent_m0_burstcount;                    // msi_to_gic_gen_0_vector_slave_agent:m0_burstcount -> msi_to_gic_gen_0_vector_slave_translator:uav_burstcount
	wire          msi_to_gic_gen_0_vector_slave_agent_rf_source_valid;                  // msi_to_gic_gen_0_vector_slave_agent:rf_source_valid -> msi_to_gic_gen_0_vector_slave_agent_rsp_fifo:in_valid
	wire   [91:0] msi_to_gic_gen_0_vector_slave_agent_rf_source_data;                   // msi_to_gic_gen_0_vector_slave_agent:rf_source_data -> msi_to_gic_gen_0_vector_slave_agent_rsp_fifo:in_data
	wire          msi_to_gic_gen_0_vector_slave_agent_rf_source_ready;                  // msi_to_gic_gen_0_vector_slave_agent_rsp_fifo:in_ready -> msi_to_gic_gen_0_vector_slave_agent:rf_source_ready
	wire          msi_to_gic_gen_0_vector_slave_agent_rf_source_startofpacket;          // msi_to_gic_gen_0_vector_slave_agent:rf_source_startofpacket -> msi_to_gic_gen_0_vector_slave_agent_rsp_fifo:in_startofpacket
	wire          msi_to_gic_gen_0_vector_slave_agent_rf_source_endofpacket;            // msi_to_gic_gen_0_vector_slave_agent:rf_source_endofpacket -> msi_to_gic_gen_0_vector_slave_agent_rsp_fifo:in_endofpacket
	wire          msi_to_gic_gen_0_vector_slave_agent_rsp_fifo_out_valid;               // msi_to_gic_gen_0_vector_slave_agent_rsp_fifo:out_valid -> msi_to_gic_gen_0_vector_slave_agent:rf_sink_valid
	wire   [91:0] msi_to_gic_gen_0_vector_slave_agent_rsp_fifo_out_data;                // msi_to_gic_gen_0_vector_slave_agent_rsp_fifo:out_data -> msi_to_gic_gen_0_vector_slave_agent:rf_sink_data
	wire          msi_to_gic_gen_0_vector_slave_agent_rsp_fifo_out_ready;               // msi_to_gic_gen_0_vector_slave_agent:rf_sink_ready -> msi_to_gic_gen_0_vector_slave_agent_rsp_fifo:out_ready
	wire          msi_to_gic_gen_0_vector_slave_agent_rsp_fifo_out_startofpacket;       // msi_to_gic_gen_0_vector_slave_agent_rsp_fifo:out_startofpacket -> msi_to_gic_gen_0_vector_slave_agent:rf_sink_startofpacket
	wire          msi_to_gic_gen_0_vector_slave_agent_rsp_fifo_out_endofpacket;         // msi_to_gic_gen_0_vector_slave_agent_rsp_fifo:out_endofpacket -> msi_to_gic_gen_0_vector_slave_agent:rf_sink_endofpacket
	wire          msi_to_gic_gen_0_vector_slave_agent_rdata_fifo_src_valid;             // msi_to_gic_gen_0_vector_slave_agent:rdata_fifo_src_valid -> msi_to_gic_gen_0_vector_slave_agent_rdata_fifo:in_valid
	wire   [33:0] msi_to_gic_gen_0_vector_slave_agent_rdata_fifo_src_data;              // msi_to_gic_gen_0_vector_slave_agent:rdata_fifo_src_data -> msi_to_gic_gen_0_vector_slave_agent_rdata_fifo:in_data
	wire          msi_to_gic_gen_0_vector_slave_agent_rdata_fifo_src_ready;             // msi_to_gic_gen_0_vector_slave_agent_rdata_fifo:in_ready -> msi_to_gic_gen_0_vector_slave_agent:rdata_fifo_src_ready
	wire          pb_lwh2f_pcie_m0_agent_cp_valid;                                      // pb_lwh2f_pcie_m0_agent:cp_valid -> router:sink_valid
	wire   [90:0] pb_lwh2f_pcie_m0_agent_cp_data;                                       // pb_lwh2f_pcie_m0_agent:cp_data -> router:sink_data
	wire          pb_lwh2f_pcie_m0_agent_cp_ready;                                      // router:sink_ready -> pb_lwh2f_pcie_m0_agent:cp_ready
	wire          pb_lwh2f_pcie_m0_agent_cp_startofpacket;                              // pb_lwh2f_pcie_m0_agent:cp_startofpacket -> router:sink_startofpacket
	wire          pb_lwh2f_pcie_m0_agent_cp_endofpacket;                                // pb_lwh2f_pcie_m0_agent:cp_endofpacket -> router:sink_endofpacket
	wire          pb_rxm_2_msi_m0_agent_cp_valid;                                       // pb_rxm_2_msi_m0_agent:cp_valid -> router_001:sink_valid
	wire   [90:0] pb_rxm_2_msi_m0_agent_cp_data;                                        // pb_rxm_2_msi_m0_agent:cp_data -> router_001:sink_data
	wire          pb_rxm_2_msi_m0_agent_cp_ready;                                       // router_001:sink_ready -> pb_rxm_2_msi_m0_agent:cp_ready
	wire          pb_rxm_2_msi_m0_agent_cp_startofpacket;                               // pb_rxm_2_msi_m0_agent:cp_startofpacket -> router_001:sink_startofpacket
	wire          pb_rxm_2_msi_m0_agent_cp_endofpacket;                                 // pb_rxm_2_msi_m0_agent:cp_endofpacket -> router_001:sink_endofpacket
	wire          router_001_src_valid;                                                 // router_001:src_valid -> cmd_demux_001:sink_valid
	wire   [90:0] router_001_src_data;                                                  // router_001:src_data -> cmd_demux_001:sink_data
	wire          router_001_src_ready;                                                 // cmd_demux_001:sink_ready -> router_001:src_ready
	wire    [5:0] router_001_src_channel;                                               // router_001:src_channel -> cmd_demux_001:sink_channel
	wire          router_001_src_startofpacket;                                         // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
	wire          router_001_src_endofpacket;                                           // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
	wire          router_002_src_valid;                                                 // router_002:src_valid -> rsp_demux:sink_valid
	wire   [90:0] router_002_src_data;                                                  // router_002:src_data -> rsp_demux:sink_data
	wire          router_002_src_ready;                                                 // rsp_demux:sink_ready -> router_002:src_ready
	wire    [5:0] router_002_src_channel;                                               // router_002:src_channel -> rsp_demux:sink_channel
	wire          router_002_src_startofpacket;                                         // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_002_src_endofpacket;                                           // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          router_003_src_valid;                                                 // router_003:src_valid -> rsp_demux_001:sink_valid
	wire   [90:0] router_003_src_data;                                                  // router_003:src_data -> rsp_demux_001:sink_data
	wire          router_003_src_ready;                                                 // rsp_demux_001:sink_ready -> router_003:src_ready
	wire    [5:0] router_003_src_channel;                                               // router_003:src_channel -> rsp_demux_001:sink_channel
	wire          router_003_src_startofpacket;                                         // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
	wire          router_003_src_endofpacket;                                           // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
	wire          router_004_src_valid;                                                 // router_004:src_valid -> rsp_demux_002:sink_valid
	wire   [90:0] router_004_src_data;                                                  // router_004:src_data -> rsp_demux_002:sink_data
	wire          router_004_src_ready;                                                 // rsp_demux_002:sink_ready -> router_004:src_ready
	wire    [5:0] router_004_src_channel;                                               // router_004:src_channel -> rsp_demux_002:sink_channel
	wire          router_004_src_startofpacket;                                         // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
	wire          router_004_src_endofpacket;                                           // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
	wire          router_005_src_valid;                                                 // router_005:src_valid -> rsp_demux_003:sink_valid
	wire   [90:0] router_005_src_data;                                                  // router_005:src_data -> rsp_demux_003:sink_data
	wire          router_005_src_ready;                                                 // rsp_demux_003:sink_ready -> router_005:src_ready
	wire    [5:0] router_005_src_channel;                                               // router_005:src_channel -> rsp_demux_003:sink_channel
	wire          router_005_src_startofpacket;                                         // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
	wire          router_005_src_endofpacket;                                           // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
	wire          router_007_src_valid;                                                 // router_007:src_valid -> rsp_demux_005:sink_valid
	wire   [90:0] router_007_src_data;                                                  // router_007:src_data -> rsp_demux_005:sink_data
	wire          router_007_src_ready;                                                 // rsp_demux_005:sink_ready -> router_007:src_ready
	wire    [5:0] router_007_src_channel;                                               // router_007:src_channel -> rsp_demux_005:sink_channel
	wire          router_007_src_startofpacket;                                         // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
	wire          router_007_src_endofpacket;                                           // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
	wire          router_src_valid;                                                     // router:src_valid -> pb_lwh2f_pcie_m0_limiter:cmd_sink_valid
	wire   [90:0] router_src_data;                                                      // router:src_data -> pb_lwh2f_pcie_m0_limiter:cmd_sink_data
	wire          router_src_ready;                                                     // pb_lwh2f_pcie_m0_limiter:cmd_sink_ready -> router:src_ready
	wire    [5:0] router_src_channel;                                                   // router:src_channel -> pb_lwh2f_pcie_m0_limiter:cmd_sink_channel
	wire          router_src_startofpacket;                                             // router:src_startofpacket -> pb_lwh2f_pcie_m0_limiter:cmd_sink_startofpacket
	wire          router_src_endofpacket;                                               // router:src_endofpacket -> pb_lwh2f_pcie_m0_limiter:cmd_sink_endofpacket
	wire          pb_lwh2f_pcie_m0_limiter_rsp_src_valid;                               // pb_lwh2f_pcie_m0_limiter:rsp_src_valid -> pb_lwh2f_pcie_m0_agent:rp_valid
	wire   [90:0] pb_lwh2f_pcie_m0_limiter_rsp_src_data;                                // pb_lwh2f_pcie_m0_limiter:rsp_src_data -> pb_lwh2f_pcie_m0_agent:rp_data
	wire          pb_lwh2f_pcie_m0_limiter_rsp_src_ready;                               // pb_lwh2f_pcie_m0_agent:rp_ready -> pb_lwh2f_pcie_m0_limiter:rsp_src_ready
	wire    [5:0] pb_lwh2f_pcie_m0_limiter_rsp_src_channel;                             // pb_lwh2f_pcie_m0_limiter:rsp_src_channel -> pb_lwh2f_pcie_m0_agent:rp_channel
	wire          pb_lwh2f_pcie_m0_limiter_rsp_src_startofpacket;                       // pb_lwh2f_pcie_m0_limiter:rsp_src_startofpacket -> pb_lwh2f_pcie_m0_agent:rp_startofpacket
	wire          pb_lwh2f_pcie_m0_limiter_rsp_src_endofpacket;                         // pb_lwh2f_pcie_m0_limiter:rsp_src_endofpacket -> pb_lwh2f_pcie_m0_agent:rp_endofpacket
	wire          cmd_demux_src2_valid;                                                 // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
	wire   [90:0] cmd_demux_src2_data;                                                  // cmd_demux:src2_data -> cmd_mux_002:sink0_data
	wire          cmd_demux_src2_ready;                                                 // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
	wire    [5:0] cmd_demux_src2_channel;                                               // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
	wire          cmd_demux_src2_startofpacket;                                         // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
	wire          cmd_demux_src2_endofpacket;                                           // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
	wire          cmd_demux_src4_valid;                                                 // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
	wire   [90:0] cmd_demux_src4_data;                                                  // cmd_demux:src4_data -> cmd_mux_004:sink0_data
	wire          cmd_demux_src4_ready;                                                 // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
	wire    [5:0] cmd_demux_src4_channel;                                               // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
	wire          cmd_demux_src4_startofpacket;                                         // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
	wire          cmd_demux_src4_endofpacket;                                           // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
	wire          rsp_demux_002_src0_valid;                                             // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
	wire   [90:0] rsp_demux_002_src0_data;                                              // rsp_demux_002:src0_data -> rsp_mux:sink2_data
	wire          rsp_demux_002_src0_ready;                                             // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
	wire    [5:0] rsp_demux_002_src0_channel;                                           // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
	wire          rsp_demux_002_src0_startofpacket;                                     // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
	wire          rsp_demux_002_src0_endofpacket;                                       // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
	wire          rsp_demux_004_src0_valid;                                             // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
	wire   [90:0] rsp_demux_004_src0_data;                                              // rsp_demux_004:src0_data -> rsp_mux:sink4_data
	wire          rsp_demux_004_src0_ready;                                             // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
	wire    [5:0] rsp_demux_004_src0_channel;                                           // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
	wire          rsp_demux_004_src0_startofpacket;                                     // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
	wire          rsp_demux_004_src0_endofpacket;                                       // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
	wire          cmd_mux_004_src_valid;                                                // cmd_mux_004:src_valid -> msgdma_0_descriptor_slave_cmd_width_adapter:in_valid
	wire   [90:0] cmd_mux_004_src_data;                                                 // cmd_mux_004:src_data -> msgdma_0_descriptor_slave_cmd_width_adapter:in_data
	wire          cmd_mux_004_src_ready;                                                // msgdma_0_descriptor_slave_cmd_width_adapter:in_ready -> cmd_mux_004:src_ready
	wire    [5:0] cmd_mux_004_src_channel;                                              // cmd_mux_004:src_channel -> msgdma_0_descriptor_slave_cmd_width_adapter:in_channel
	wire          cmd_mux_004_src_startofpacket;                                        // cmd_mux_004:src_startofpacket -> msgdma_0_descriptor_slave_cmd_width_adapter:in_startofpacket
	wire          cmd_mux_004_src_endofpacket;                                          // cmd_mux_004:src_endofpacket -> msgdma_0_descriptor_slave_cmd_width_adapter:in_endofpacket
	wire          router_006_src_valid;                                                 // router_006:src_valid -> msgdma_0_descriptor_slave_rsp_width_adapter:in_valid
	wire  [198:0] router_006_src_data;                                                  // router_006:src_data -> msgdma_0_descriptor_slave_rsp_width_adapter:in_data
	wire          router_006_src_ready;                                                 // msgdma_0_descriptor_slave_rsp_width_adapter:in_ready -> router_006:src_ready
	wire    [5:0] router_006_src_channel;                                               // router_006:src_channel -> msgdma_0_descriptor_slave_rsp_width_adapter:in_channel
	wire          router_006_src_startofpacket;                                         // router_006:src_startofpacket -> msgdma_0_descriptor_slave_rsp_width_adapter:in_startofpacket
	wire          router_006_src_endofpacket;                                           // router_006:src_endofpacket -> msgdma_0_descriptor_slave_rsp_width_adapter:in_endofpacket
	wire          msgdma_0_descriptor_slave_rsp_width_adapter_src_valid;                // msgdma_0_descriptor_slave_rsp_width_adapter:out_valid -> rsp_demux_004:sink_valid
	wire   [90:0] msgdma_0_descriptor_slave_rsp_width_adapter_src_data;                 // msgdma_0_descriptor_slave_rsp_width_adapter:out_data -> rsp_demux_004:sink_data
	wire          msgdma_0_descriptor_slave_rsp_width_adapter_src_ready;                // rsp_demux_004:sink_ready -> msgdma_0_descriptor_slave_rsp_width_adapter:out_ready
	wire    [5:0] msgdma_0_descriptor_slave_rsp_width_adapter_src_channel;              // msgdma_0_descriptor_slave_rsp_width_adapter:out_channel -> rsp_demux_004:sink_channel
	wire          msgdma_0_descriptor_slave_rsp_width_adapter_src_startofpacket;        // msgdma_0_descriptor_slave_rsp_width_adapter:out_startofpacket -> rsp_demux_004:sink_startofpacket
	wire          msgdma_0_descriptor_slave_rsp_width_adapter_src_endofpacket;          // msgdma_0_descriptor_slave_rsp_width_adapter:out_endofpacket -> rsp_demux_004:sink_endofpacket
	wire          cmd_demux_src0_valid;                                                 // cmd_demux:src0_valid -> crosser:in_valid
	wire   [90:0] cmd_demux_src0_data;                                                  // cmd_demux:src0_data -> crosser:in_data
	wire          cmd_demux_src0_ready;                                                 // crosser:in_ready -> cmd_demux:src0_ready
	wire    [5:0] cmd_demux_src0_channel;                                               // cmd_demux:src0_channel -> crosser:in_channel
	wire          cmd_demux_src0_startofpacket;                                         // cmd_demux:src0_startofpacket -> crosser:in_startofpacket
	wire          cmd_demux_src0_endofpacket;                                           // cmd_demux:src0_endofpacket -> crosser:in_endofpacket
	wire          crosser_out_valid;                                                    // crosser:out_valid -> cmd_mux:sink0_valid
	wire   [90:0] crosser_out_data;                                                     // crosser:out_data -> cmd_mux:sink0_data
	wire          crosser_out_ready;                                                    // cmd_mux:sink0_ready -> crosser:out_ready
	wire    [5:0] crosser_out_channel;                                                  // crosser:out_channel -> cmd_mux:sink0_channel
	wire          crosser_out_startofpacket;                                            // crosser:out_startofpacket -> cmd_mux:sink0_startofpacket
	wire          crosser_out_endofpacket;                                              // crosser:out_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_src1_valid;                                                 // cmd_demux:src1_valid -> crosser_001:in_valid
	wire   [90:0] cmd_demux_src1_data;                                                  // cmd_demux:src1_data -> crosser_001:in_data
	wire          cmd_demux_src1_ready;                                                 // crosser_001:in_ready -> cmd_demux:src1_ready
	wire    [5:0] cmd_demux_src1_channel;                                               // cmd_demux:src1_channel -> crosser_001:in_channel
	wire          cmd_demux_src1_startofpacket;                                         // cmd_demux:src1_startofpacket -> crosser_001:in_startofpacket
	wire          cmd_demux_src1_endofpacket;                                           // cmd_demux:src1_endofpacket -> crosser_001:in_endofpacket
	wire          crosser_001_out_valid;                                                // crosser_001:out_valid -> cmd_mux_001:sink0_valid
	wire   [90:0] crosser_001_out_data;                                                 // crosser_001:out_data -> cmd_mux_001:sink0_data
	wire          crosser_001_out_ready;                                                // cmd_mux_001:sink0_ready -> crosser_001:out_ready
	wire    [5:0] crosser_001_out_channel;                                              // crosser_001:out_channel -> cmd_mux_001:sink0_channel
	wire          crosser_001_out_startofpacket;                                        // crosser_001:out_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire          crosser_001_out_endofpacket;                                          // crosser_001:out_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire          cmd_demux_src3_valid;                                                 // cmd_demux:src3_valid -> crosser_002:in_valid
	wire   [90:0] cmd_demux_src3_data;                                                  // cmd_demux:src3_data -> crosser_002:in_data
	wire          cmd_demux_src3_ready;                                                 // crosser_002:in_ready -> cmd_demux:src3_ready
	wire    [5:0] cmd_demux_src3_channel;                                               // cmd_demux:src3_channel -> crosser_002:in_channel
	wire          cmd_demux_src3_startofpacket;                                         // cmd_demux:src3_startofpacket -> crosser_002:in_startofpacket
	wire          cmd_demux_src3_endofpacket;                                           // cmd_demux:src3_endofpacket -> crosser_002:in_endofpacket
	wire          crosser_002_out_valid;                                                // crosser_002:out_valid -> cmd_mux_003:sink0_valid
	wire   [90:0] crosser_002_out_data;                                                 // crosser_002:out_data -> cmd_mux_003:sink0_data
	wire          crosser_002_out_ready;                                                // cmd_mux_003:sink0_ready -> crosser_002:out_ready
	wire    [5:0] crosser_002_out_channel;                                              // crosser_002:out_channel -> cmd_mux_003:sink0_channel
	wire          crosser_002_out_startofpacket;                                        // crosser_002:out_startofpacket -> cmd_mux_003:sink0_startofpacket
	wire          crosser_002_out_endofpacket;                                          // crosser_002:out_endofpacket -> cmd_mux_003:sink0_endofpacket
	wire          cmd_demux_src5_valid;                                                 // cmd_demux:src5_valid -> crosser_003:in_valid
	wire   [90:0] cmd_demux_src5_data;                                                  // cmd_demux:src5_data -> crosser_003:in_data
	wire          cmd_demux_src5_ready;                                                 // crosser_003:in_ready -> cmd_demux:src5_ready
	wire    [5:0] cmd_demux_src5_channel;                                               // cmd_demux:src5_channel -> crosser_003:in_channel
	wire          cmd_demux_src5_startofpacket;                                         // cmd_demux:src5_startofpacket -> crosser_003:in_startofpacket
	wire          cmd_demux_src5_endofpacket;                                           // cmd_demux:src5_endofpacket -> crosser_003:in_endofpacket
	wire          crosser_003_out_valid;                                                // crosser_003:out_valid -> cmd_mux_005:sink0_valid
	wire   [90:0] crosser_003_out_data;                                                 // crosser_003:out_data -> cmd_mux_005:sink0_data
	wire          crosser_003_out_ready;                                                // cmd_mux_005:sink0_ready -> crosser_003:out_ready
	wire    [5:0] crosser_003_out_channel;                                              // crosser_003:out_channel -> cmd_mux_005:sink0_channel
	wire          crosser_003_out_startofpacket;                                        // crosser_003:out_startofpacket -> cmd_mux_005:sink0_startofpacket
	wire          crosser_003_out_endofpacket;                                          // crosser_003:out_endofpacket -> cmd_mux_005:sink0_endofpacket
	wire          cmd_demux_001_src0_valid;                                             // cmd_demux_001:src0_valid -> crosser_004:in_valid
	wire   [90:0] cmd_demux_001_src0_data;                                              // cmd_demux_001:src0_data -> crosser_004:in_data
	wire          cmd_demux_001_src0_ready;                                             // crosser_004:in_ready -> cmd_demux_001:src0_ready
	wire    [5:0] cmd_demux_001_src0_channel;                                           // cmd_demux_001:src0_channel -> crosser_004:in_channel
	wire          cmd_demux_001_src0_startofpacket;                                     // cmd_demux_001:src0_startofpacket -> crosser_004:in_startofpacket
	wire          cmd_demux_001_src0_endofpacket;                                       // cmd_demux_001:src0_endofpacket -> crosser_004:in_endofpacket
	wire          crosser_004_out_valid;                                                // crosser_004:out_valid -> cmd_mux_005:sink1_valid
	wire   [90:0] crosser_004_out_data;                                                 // crosser_004:out_data -> cmd_mux_005:sink1_data
	wire          crosser_004_out_ready;                                                // cmd_mux_005:sink1_ready -> crosser_004:out_ready
	wire    [5:0] crosser_004_out_channel;                                              // crosser_004:out_channel -> cmd_mux_005:sink1_channel
	wire          crosser_004_out_startofpacket;                                        // crosser_004:out_startofpacket -> cmd_mux_005:sink1_startofpacket
	wire          crosser_004_out_endofpacket;                                          // crosser_004:out_endofpacket -> cmd_mux_005:sink1_endofpacket
	wire          rsp_demux_src0_valid;                                                 // rsp_demux:src0_valid -> crosser_005:in_valid
	wire   [90:0] rsp_demux_src0_data;                                                  // rsp_demux:src0_data -> crosser_005:in_data
	wire          rsp_demux_src0_ready;                                                 // crosser_005:in_ready -> rsp_demux:src0_ready
	wire    [5:0] rsp_demux_src0_channel;                                               // rsp_demux:src0_channel -> crosser_005:in_channel
	wire          rsp_demux_src0_startofpacket;                                         // rsp_demux:src0_startofpacket -> crosser_005:in_startofpacket
	wire          rsp_demux_src0_endofpacket;                                           // rsp_demux:src0_endofpacket -> crosser_005:in_endofpacket
	wire          crosser_005_out_valid;                                                // crosser_005:out_valid -> rsp_mux:sink0_valid
	wire   [90:0] crosser_005_out_data;                                                 // crosser_005:out_data -> rsp_mux:sink0_data
	wire          crosser_005_out_ready;                                                // rsp_mux:sink0_ready -> crosser_005:out_ready
	wire    [5:0] crosser_005_out_channel;                                              // crosser_005:out_channel -> rsp_mux:sink0_channel
	wire          crosser_005_out_startofpacket;                                        // crosser_005:out_startofpacket -> rsp_mux:sink0_startofpacket
	wire          crosser_005_out_endofpacket;                                          // crosser_005:out_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_001_src0_valid;                                             // rsp_demux_001:src0_valid -> crosser_006:in_valid
	wire   [90:0] rsp_demux_001_src0_data;                                              // rsp_demux_001:src0_data -> crosser_006:in_data
	wire          rsp_demux_001_src0_ready;                                             // crosser_006:in_ready -> rsp_demux_001:src0_ready
	wire    [5:0] rsp_demux_001_src0_channel;                                           // rsp_demux_001:src0_channel -> crosser_006:in_channel
	wire          rsp_demux_001_src0_startofpacket;                                     // rsp_demux_001:src0_startofpacket -> crosser_006:in_startofpacket
	wire          rsp_demux_001_src0_endofpacket;                                       // rsp_demux_001:src0_endofpacket -> crosser_006:in_endofpacket
	wire          crosser_006_out_valid;                                                // crosser_006:out_valid -> rsp_mux:sink1_valid
	wire   [90:0] crosser_006_out_data;                                                 // crosser_006:out_data -> rsp_mux:sink1_data
	wire          crosser_006_out_ready;                                                // rsp_mux:sink1_ready -> crosser_006:out_ready
	wire    [5:0] crosser_006_out_channel;                                              // crosser_006:out_channel -> rsp_mux:sink1_channel
	wire          crosser_006_out_startofpacket;                                        // crosser_006:out_startofpacket -> rsp_mux:sink1_startofpacket
	wire          crosser_006_out_endofpacket;                                          // crosser_006:out_endofpacket -> rsp_mux:sink1_endofpacket
	wire          rsp_demux_003_src0_valid;                                             // rsp_demux_003:src0_valid -> crosser_007:in_valid
	wire   [90:0] rsp_demux_003_src0_data;                                              // rsp_demux_003:src0_data -> crosser_007:in_data
	wire          rsp_demux_003_src0_ready;                                             // crosser_007:in_ready -> rsp_demux_003:src0_ready
	wire    [5:0] rsp_demux_003_src0_channel;                                           // rsp_demux_003:src0_channel -> crosser_007:in_channel
	wire          rsp_demux_003_src0_startofpacket;                                     // rsp_demux_003:src0_startofpacket -> crosser_007:in_startofpacket
	wire          rsp_demux_003_src0_endofpacket;                                       // rsp_demux_003:src0_endofpacket -> crosser_007:in_endofpacket
	wire          crosser_007_out_valid;                                                // crosser_007:out_valid -> rsp_mux:sink3_valid
	wire   [90:0] crosser_007_out_data;                                                 // crosser_007:out_data -> rsp_mux:sink3_data
	wire          crosser_007_out_ready;                                                // rsp_mux:sink3_ready -> crosser_007:out_ready
	wire    [5:0] crosser_007_out_channel;                                              // crosser_007:out_channel -> rsp_mux:sink3_channel
	wire          crosser_007_out_startofpacket;                                        // crosser_007:out_startofpacket -> rsp_mux:sink3_startofpacket
	wire          crosser_007_out_endofpacket;                                          // crosser_007:out_endofpacket -> rsp_mux:sink3_endofpacket
	wire          rsp_demux_005_src0_valid;                                             // rsp_demux_005:src0_valid -> crosser_008:in_valid
	wire   [90:0] rsp_demux_005_src0_data;                                              // rsp_demux_005:src0_data -> crosser_008:in_data
	wire          rsp_demux_005_src0_ready;                                             // crosser_008:in_ready -> rsp_demux_005:src0_ready
	wire    [5:0] rsp_demux_005_src0_channel;                                           // rsp_demux_005:src0_channel -> crosser_008:in_channel
	wire          rsp_demux_005_src0_startofpacket;                                     // rsp_demux_005:src0_startofpacket -> crosser_008:in_startofpacket
	wire          rsp_demux_005_src0_endofpacket;                                       // rsp_demux_005:src0_endofpacket -> crosser_008:in_endofpacket
	wire          crosser_008_out_valid;                                                // crosser_008:out_valid -> rsp_mux:sink5_valid
	wire   [90:0] crosser_008_out_data;                                                 // crosser_008:out_data -> rsp_mux:sink5_data
	wire          crosser_008_out_ready;                                                // rsp_mux:sink5_ready -> crosser_008:out_ready
	wire    [5:0] crosser_008_out_channel;                                              // crosser_008:out_channel -> rsp_mux:sink5_channel
	wire          crosser_008_out_startofpacket;                                        // crosser_008:out_startofpacket -> rsp_mux:sink5_startofpacket
	wire          crosser_008_out_endofpacket;                                          // crosser_008:out_endofpacket -> rsp_mux:sink5_endofpacket
	wire          rsp_demux_005_src1_valid;                                             // rsp_demux_005:src1_valid -> crosser_009:in_valid
	wire   [90:0] rsp_demux_005_src1_data;                                              // rsp_demux_005:src1_data -> crosser_009:in_data
	wire          rsp_demux_005_src1_ready;                                             // crosser_009:in_ready -> rsp_demux_005:src1_ready
	wire    [5:0] rsp_demux_005_src1_channel;                                           // rsp_demux_005:src1_channel -> crosser_009:in_channel
	wire          rsp_demux_005_src1_startofpacket;                                     // rsp_demux_005:src1_startofpacket -> crosser_009:in_startofpacket
	wire          rsp_demux_005_src1_endofpacket;                                       // rsp_demux_005:src1_endofpacket -> crosser_009:in_endofpacket
	wire          crosser_009_out_valid;                                                // crosser_009:out_valid -> rsp_mux_001:sink0_valid
	wire   [90:0] crosser_009_out_data;                                                 // crosser_009:out_data -> rsp_mux_001:sink0_data
	wire          crosser_009_out_ready;                                                // rsp_mux_001:sink0_ready -> crosser_009:out_ready
	wire    [5:0] crosser_009_out_channel;                                              // crosser_009:out_channel -> rsp_mux_001:sink0_channel
	wire          crosser_009_out_startofpacket;                                        // crosser_009:out_startofpacket -> rsp_mux_001:sink0_startofpacket
	wire          crosser_009_out_endofpacket;                                          // crosser_009:out_endofpacket -> rsp_mux_001:sink0_endofpacket
	wire    [0:0] pb_lwh2f_pcie_m0_limiter_cmd_src_valid;                               // pb_lwh2f_pcie_m0_limiter:cmd_src_valid -> limiter_pipeline:in_valid
	wire   [90:0] pb_lwh2f_pcie_m0_limiter_cmd_src_data;                                // pb_lwh2f_pcie_m0_limiter:cmd_src_data -> limiter_pipeline:in_data
	wire          pb_lwh2f_pcie_m0_limiter_cmd_src_ready;                               // limiter_pipeline:in_ready -> pb_lwh2f_pcie_m0_limiter:cmd_src_ready
	wire    [5:0] pb_lwh2f_pcie_m0_limiter_cmd_src_channel;                             // pb_lwh2f_pcie_m0_limiter:cmd_src_channel -> limiter_pipeline:in_channel
	wire          pb_lwh2f_pcie_m0_limiter_cmd_src_startofpacket;                       // pb_lwh2f_pcie_m0_limiter:cmd_src_startofpacket -> limiter_pipeline:in_startofpacket
	wire          pb_lwh2f_pcie_m0_limiter_cmd_src_endofpacket;                         // pb_lwh2f_pcie_m0_limiter:cmd_src_endofpacket -> limiter_pipeline:in_endofpacket
	wire          limiter_pipeline_source0_valid;                                       // limiter_pipeline:out_valid -> cmd_demux:sink_valid
	wire   [90:0] limiter_pipeline_source0_data;                                        // limiter_pipeline:out_data -> cmd_demux:sink_data
	wire          limiter_pipeline_source0_ready;                                       // cmd_demux:sink_ready -> limiter_pipeline:out_ready
	wire    [5:0] limiter_pipeline_source0_channel;                                     // limiter_pipeline:out_channel -> cmd_demux:sink_channel
	wire          limiter_pipeline_source0_startofpacket;                               // limiter_pipeline:out_startofpacket -> cmd_demux:sink_startofpacket
	wire          limiter_pipeline_source0_endofpacket;                                 // limiter_pipeline:out_endofpacket -> cmd_demux:sink_endofpacket
	wire          rsp_mux_src_valid;                                                    // rsp_mux:src_valid -> limiter_pipeline_001:in_valid
	wire   [90:0] rsp_mux_src_data;                                                     // rsp_mux:src_data -> limiter_pipeline_001:in_data
	wire          rsp_mux_src_ready;                                                    // limiter_pipeline_001:in_ready -> rsp_mux:src_ready
	wire    [5:0] rsp_mux_src_channel;                                                  // rsp_mux:src_channel -> limiter_pipeline_001:in_channel
	wire          rsp_mux_src_startofpacket;                                            // rsp_mux:src_startofpacket -> limiter_pipeline_001:in_startofpacket
	wire          rsp_mux_src_endofpacket;                                              // rsp_mux:src_endofpacket -> limiter_pipeline_001:in_endofpacket
	wire          limiter_pipeline_001_source0_valid;                                   // limiter_pipeline_001:out_valid -> pb_lwh2f_pcie_m0_limiter:rsp_sink_valid
	wire   [90:0] limiter_pipeline_001_source0_data;                                    // limiter_pipeline_001:out_data -> pb_lwh2f_pcie_m0_limiter:rsp_sink_data
	wire          limiter_pipeline_001_source0_ready;                                   // pb_lwh2f_pcie_m0_limiter:rsp_sink_ready -> limiter_pipeline_001:out_ready
	wire    [5:0] limiter_pipeline_001_source0_channel;                                 // limiter_pipeline_001:out_channel -> pb_lwh2f_pcie_m0_limiter:rsp_sink_channel
	wire          limiter_pipeline_001_source0_startofpacket;                           // limiter_pipeline_001:out_startofpacket -> pb_lwh2f_pcie_m0_limiter:rsp_sink_startofpacket
	wire          limiter_pipeline_001_source0_endofpacket;                             // limiter_pipeline_001:out_endofpacket -> pb_lwh2f_pcie_m0_limiter:rsp_sink_endofpacket
	wire          cmd_mux_src_valid;                                                    // cmd_mux:src_valid -> agent_pipeline:in_valid
	wire   [90:0] cmd_mux_src_data;                                                     // cmd_mux:src_data -> agent_pipeline:in_data
	wire          cmd_mux_src_ready;                                                    // agent_pipeline:in_ready -> cmd_mux:src_ready
	wire    [5:0] cmd_mux_src_channel;                                                  // cmd_mux:src_channel -> agent_pipeline:in_channel
	wire          cmd_mux_src_startofpacket;                                            // cmd_mux:src_startofpacket -> agent_pipeline:in_startofpacket
	wire          cmd_mux_src_endofpacket;                                              // cmd_mux:src_endofpacket -> agent_pipeline:in_endofpacket
	wire          agent_pipeline_source0_valid;                                         // agent_pipeline:out_valid -> pcie_hip_avmm_Cra_agent:cp_valid
	wire   [90:0] agent_pipeline_source0_data;                                          // agent_pipeline:out_data -> pcie_hip_avmm_Cra_agent:cp_data
	wire          agent_pipeline_source0_ready;                                         // pcie_hip_avmm_Cra_agent:cp_ready -> agent_pipeline:out_ready
	wire    [5:0] agent_pipeline_source0_channel;                                       // agent_pipeline:out_channel -> pcie_hip_avmm_Cra_agent:cp_channel
	wire          agent_pipeline_source0_startofpacket;                                 // agent_pipeline:out_startofpacket -> pcie_hip_avmm_Cra_agent:cp_startofpacket
	wire          agent_pipeline_source0_endofpacket;                                   // agent_pipeline:out_endofpacket -> pcie_hip_avmm_Cra_agent:cp_endofpacket
	wire          pcie_hip_avmm_cra_agent_rp_valid;                                     // pcie_hip_avmm_Cra_agent:rp_valid -> agent_pipeline_001:in_valid
	wire   [90:0] pcie_hip_avmm_cra_agent_rp_data;                                      // pcie_hip_avmm_Cra_agent:rp_data -> agent_pipeline_001:in_data
	wire          pcie_hip_avmm_cra_agent_rp_ready;                                     // agent_pipeline_001:in_ready -> pcie_hip_avmm_Cra_agent:rp_ready
	wire          pcie_hip_avmm_cra_agent_rp_startofpacket;                             // pcie_hip_avmm_Cra_agent:rp_startofpacket -> agent_pipeline_001:in_startofpacket
	wire          pcie_hip_avmm_cra_agent_rp_endofpacket;                               // pcie_hip_avmm_Cra_agent:rp_endofpacket -> agent_pipeline_001:in_endofpacket
	wire          agent_pipeline_001_source0_valid;                                     // agent_pipeline_001:out_valid -> router_002:sink_valid
	wire   [90:0] agent_pipeline_001_source0_data;                                      // agent_pipeline_001:out_data -> router_002:sink_data
	wire          agent_pipeline_001_source0_ready;                                     // router_002:sink_ready -> agent_pipeline_001:out_ready
	wire          agent_pipeline_001_source0_startofpacket;                             // agent_pipeline_001:out_startofpacket -> router_002:sink_startofpacket
	wire          agent_pipeline_001_source0_endofpacket;                               // agent_pipeline_001:out_endofpacket -> router_002:sink_endofpacket
	wire          cmd_mux_001_src_valid;                                                // cmd_mux_001:src_valid -> agent_pipeline_002:in_valid
	wire   [90:0] cmd_mux_001_src_data;                                                 // cmd_mux_001:src_data -> agent_pipeline_002:in_data
	wire          cmd_mux_001_src_ready;                                                // agent_pipeline_002:in_ready -> cmd_mux_001:src_ready
	wire    [5:0] cmd_mux_001_src_channel;                                              // cmd_mux_001:src_channel -> agent_pipeline_002:in_channel
	wire          cmd_mux_001_src_startofpacket;                                        // cmd_mux_001:src_startofpacket -> agent_pipeline_002:in_startofpacket
	wire          cmd_mux_001_src_endofpacket;                                          // cmd_mux_001:src_endofpacket -> agent_pipeline_002:in_endofpacket
	wire          agent_pipeline_002_source0_valid;                                     // agent_pipeline_002:out_valid -> performance_counter_0_control_slave_agent:cp_valid
	wire   [90:0] agent_pipeline_002_source0_data;                                      // agent_pipeline_002:out_data -> performance_counter_0_control_slave_agent:cp_data
	wire          agent_pipeline_002_source0_ready;                                     // performance_counter_0_control_slave_agent:cp_ready -> agent_pipeline_002:out_ready
	wire    [5:0] agent_pipeline_002_source0_channel;                                   // agent_pipeline_002:out_channel -> performance_counter_0_control_slave_agent:cp_channel
	wire          agent_pipeline_002_source0_startofpacket;                             // agent_pipeline_002:out_startofpacket -> performance_counter_0_control_slave_agent:cp_startofpacket
	wire          agent_pipeline_002_source0_endofpacket;                               // agent_pipeline_002:out_endofpacket -> performance_counter_0_control_slave_agent:cp_endofpacket
	wire          performance_counter_0_control_slave_agent_rp_valid;                   // performance_counter_0_control_slave_agent:rp_valid -> agent_pipeline_003:in_valid
	wire   [90:0] performance_counter_0_control_slave_agent_rp_data;                    // performance_counter_0_control_slave_agent:rp_data -> agent_pipeline_003:in_data
	wire          performance_counter_0_control_slave_agent_rp_ready;                   // agent_pipeline_003:in_ready -> performance_counter_0_control_slave_agent:rp_ready
	wire          performance_counter_0_control_slave_agent_rp_startofpacket;           // performance_counter_0_control_slave_agent:rp_startofpacket -> agent_pipeline_003:in_startofpacket
	wire          performance_counter_0_control_slave_agent_rp_endofpacket;             // performance_counter_0_control_slave_agent:rp_endofpacket -> agent_pipeline_003:in_endofpacket
	wire          agent_pipeline_003_source0_valid;                                     // agent_pipeline_003:out_valid -> router_003:sink_valid
	wire   [90:0] agent_pipeline_003_source0_data;                                      // agent_pipeline_003:out_data -> router_003:sink_data
	wire          agent_pipeline_003_source0_ready;                                     // router_003:sink_ready -> agent_pipeline_003:out_ready
	wire          agent_pipeline_003_source0_startofpacket;                             // agent_pipeline_003:out_startofpacket -> router_003:sink_startofpacket
	wire          agent_pipeline_003_source0_endofpacket;                               // agent_pipeline_003:out_endofpacket -> router_003:sink_endofpacket
	wire          cmd_mux_002_src_valid;                                                // cmd_mux_002:src_valid -> agent_pipeline_004:in_valid
	wire   [90:0] cmd_mux_002_src_data;                                                 // cmd_mux_002:src_data -> agent_pipeline_004:in_data
	wire          cmd_mux_002_src_ready;                                                // agent_pipeline_004:in_ready -> cmd_mux_002:src_ready
	wire    [5:0] cmd_mux_002_src_channel;                                              // cmd_mux_002:src_channel -> agent_pipeline_004:in_channel
	wire          cmd_mux_002_src_startofpacket;                                        // cmd_mux_002:src_startofpacket -> agent_pipeline_004:in_startofpacket
	wire          cmd_mux_002_src_endofpacket;                                          // cmd_mux_002:src_endofpacket -> agent_pipeline_004:in_endofpacket
	wire          agent_pipeline_004_source0_valid;                                     // agent_pipeline_004:out_valid -> msgdma_0_csr_agent:cp_valid
	wire   [90:0] agent_pipeline_004_source0_data;                                      // agent_pipeline_004:out_data -> msgdma_0_csr_agent:cp_data
	wire          agent_pipeline_004_source0_ready;                                     // msgdma_0_csr_agent:cp_ready -> agent_pipeline_004:out_ready
	wire    [5:0] agent_pipeline_004_source0_channel;                                   // agent_pipeline_004:out_channel -> msgdma_0_csr_agent:cp_channel
	wire          agent_pipeline_004_source0_startofpacket;                             // agent_pipeline_004:out_startofpacket -> msgdma_0_csr_agent:cp_startofpacket
	wire          agent_pipeline_004_source0_endofpacket;                               // agent_pipeline_004:out_endofpacket -> msgdma_0_csr_agent:cp_endofpacket
	wire          msgdma_0_csr_agent_rp_valid;                                          // msgdma_0_csr_agent:rp_valid -> agent_pipeline_005:in_valid
	wire   [90:0] msgdma_0_csr_agent_rp_data;                                           // msgdma_0_csr_agent:rp_data -> agent_pipeline_005:in_data
	wire          msgdma_0_csr_agent_rp_ready;                                          // agent_pipeline_005:in_ready -> msgdma_0_csr_agent:rp_ready
	wire          msgdma_0_csr_agent_rp_startofpacket;                                  // msgdma_0_csr_agent:rp_startofpacket -> agent_pipeline_005:in_startofpacket
	wire          msgdma_0_csr_agent_rp_endofpacket;                                    // msgdma_0_csr_agent:rp_endofpacket -> agent_pipeline_005:in_endofpacket
	wire          agent_pipeline_005_source0_valid;                                     // agent_pipeline_005:out_valid -> router_004:sink_valid
	wire   [90:0] agent_pipeline_005_source0_data;                                      // agent_pipeline_005:out_data -> router_004:sink_data
	wire          agent_pipeline_005_source0_ready;                                     // router_004:sink_ready -> agent_pipeline_005:out_ready
	wire          agent_pipeline_005_source0_startofpacket;                             // agent_pipeline_005:out_startofpacket -> router_004:sink_startofpacket
	wire          agent_pipeline_005_source0_endofpacket;                               // agent_pipeline_005:out_endofpacket -> router_004:sink_endofpacket
	wire          cmd_mux_003_src_valid;                                                // cmd_mux_003:src_valid -> agent_pipeline_006:in_valid
	wire   [90:0] cmd_mux_003_src_data;                                                 // cmd_mux_003:src_data -> agent_pipeline_006:in_data
	wire          cmd_mux_003_src_ready;                                                // agent_pipeline_006:in_ready -> cmd_mux_003:src_ready
	wire    [5:0] cmd_mux_003_src_channel;                                              // cmd_mux_003:src_channel -> agent_pipeline_006:in_channel
	wire          cmd_mux_003_src_startofpacket;                                        // cmd_mux_003:src_startofpacket -> agent_pipeline_006:in_startofpacket
	wire          cmd_mux_003_src_endofpacket;                                          // cmd_mux_003:src_endofpacket -> agent_pipeline_006:in_endofpacket
	wire          agent_pipeline_006_source0_valid;                                     // agent_pipeline_006:out_valid -> msi_to_gic_gen_0_csr_agent:cp_valid
	wire   [90:0] agent_pipeline_006_source0_data;                                      // agent_pipeline_006:out_data -> msi_to_gic_gen_0_csr_agent:cp_data
	wire          agent_pipeline_006_source0_ready;                                     // msi_to_gic_gen_0_csr_agent:cp_ready -> agent_pipeline_006:out_ready
	wire    [5:0] agent_pipeline_006_source0_channel;                                   // agent_pipeline_006:out_channel -> msi_to_gic_gen_0_csr_agent:cp_channel
	wire          agent_pipeline_006_source0_startofpacket;                             // agent_pipeline_006:out_startofpacket -> msi_to_gic_gen_0_csr_agent:cp_startofpacket
	wire          agent_pipeline_006_source0_endofpacket;                               // agent_pipeline_006:out_endofpacket -> msi_to_gic_gen_0_csr_agent:cp_endofpacket
	wire          msi_to_gic_gen_0_csr_agent_rp_valid;                                  // msi_to_gic_gen_0_csr_agent:rp_valid -> agent_pipeline_007:in_valid
	wire   [90:0] msi_to_gic_gen_0_csr_agent_rp_data;                                   // msi_to_gic_gen_0_csr_agent:rp_data -> agent_pipeline_007:in_data
	wire          msi_to_gic_gen_0_csr_agent_rp_ready;                                  // agent_pipeline_007:in_ready -> msi_to_gic_gen_0_csr_agent:rp_ready
	wire          msi_to_gic_gen_0_csr_agent_rp_startofpacket;                          // msi_to_gic_gen_0_csr_agent:rp_startofpacket -> agent_pipeline_007:in_startofpacket
	wire          msi_to_gic_gen_0_csr_agent_rp_endofpacket;                            // msi_to_gic_gen_0_csr_agent:rp_endofpacket -> agent_pipeline_007:in_endofpacket
	wire          agent_pipeline_007_source0_valid;                                     // agent_pipeline_007:out_valid -> router_005:sink_valid
	wire   [90:0] agent_pipeline_007_source0_data;                                      // agent_pipeline_007:out_data -> router_005:sink_data
	wire          agent_pipeline_007_source0_ready;                                     // router_005:sink_ready -> agent_pipeline_007:out_ready
	wire          agent_pipeline_007_source0_startofpacket;                             // agent_pipeline_007:out_startofpacket -> router_005:sink_startofpacket
	wire          agent_pipeline_007_source0_endofpacket;                               // agent_pipeline_007:out_endofpacket -> router_005:sink_endofpacket
	wire          msgdma_0_descriptor_slave_cmd_width_adapter_src_valid;                // msgdma_0_descriptor_slave_cmd_width_adapter:out_valid -> agent_pipeline_008:in_valid
	wire  [198:0] msgdma_0_descriptor_slave_cmd_width_adapter_src_data;                 // msgdma_0_descriptor_slave_cmd_width_adapter:out_data -> agent_pipeline_008:in_data
	wire          msgdma_0_descriptor_slave_cmd_width_adapter_src_ready;                // agent_pipeline_008:in_ready -> msgdma_0_descriptor_slave_cmd_width_adapter:out_ready
	wire    [5:0] msgdma_0_descriptor_slave_cmd_width_adapter_src_channel;              // msgdma_0_descriptor_slave_cmd_width_adapter:out_channel -> agent_pipeline_008:in_channel
	wire          msgdma_0_descriptor_slave_cmd_width_adapter_src_startofpacket;        // msgdma_0_descriptor_slave_cmd_width_adapter:out_startofpacket -> agent_pipeline_008:in_startofpacket
	wire          msgdma_0_descriptor_slave_cmd_width_adapter_src_endofpacket;          // msgdma_0_descriptor_slave_cmd_width_adapter:out_endofpacket -> agent_pipeline_008:in_endofpacket
	wire          agent_pipeline_008_source0_valid;                                     // agent_pipeline_008:out_valid -> msgdma_0_descriptor_slave_agent:cp_valid
	wire  [198:0] agent_pipeline_008_source0_data;                                      // agent_pipeline_008:out_data -> msgdma_0_descriptor_slave_agent:cp_data
	wire          agent_pipeline_008_source0_ready;                                     // msgdma_0_descriptor_slave_agent:cp_ready -> agent_pipeline_008:out_ready
	wire    [5:0] agent_pipeline_008_source0_channel;                                   // agent_pipeline_008:out_channel -> msgdma_0_descriptor_slave_agent:cp_channel
	wire          agent_pipeline_008_source0_startofpacket;                             // agent_pipeline_008:out_startofpacket -> msgdma_0_descriptor_slave_agent:cp_startofpacket
	wire          agent_pipeline_008_source0_endofpacket;                               // agent_pipeline_008:out_endofpacket -> msgdma_0_descriptor_slave_agent:cp_endofpacket
	wire          msgdma_0_descriptor_slave_agent_rp_valid;                             // msgdma_0_descriptor_slave_agent:rp_valid -> agent_pipeline_009:in_valid
	wire  [198:0] msgdma_0_descriptor_slave_agent_rp_data;                              // msgdma_0_descriptor_slave_agent:rp_data -> agent_pipeline_009:in_data
	wire          msgdma_0_descriptor_slave_agent_rp_ready;                             // agent_pipeline_009:in_ready -> msgdma_0_descriptor_slave_agent:rp_ready
	wire          msgdma_0_descriptor_slave_agent_rp_startofpacket;                     // msgdma_0_descriptor_slave_agent:rp_startofpacket -> agent_pipeline_009:in_startofpacket
	wire          msgdma_0_descriptor_slave_agent_rp_endofpacket;                       // msgdma_0_descriptor_slave_agent:rp_endofpacket -> agent_pipeline_009:in_endofpacket
	wire          agent_pipeline_009_source0_valid;                                     // agent_pipeline_009:out_valid -> router_006:sink_valid
	wire  [198:0] agent_pipeline_009_source0_data;                                      // agent_pipeline_009:out_data -> router_006:sink_data
	wire          agent_pipeline_009_source0_ready;                                     // router_006:sink_ready -> agent_pipeline_009:out_ready
	wire          agent_pipeline_009_source0_startofpacket;                             // agent_pipeline_009:out_startofpacket -> router_006:sink_startofpacket
	wire          agent_pipeline_009_source0_endofpacket;                               // agent_pipeline_009:out_endofpacket -> router_006:sink_endofpacket
	wire          cmd_mux_005_src_valid;                                                // cmd_mux_005:src_valid -> agent_pipeline_010:in_valid
	wire   [90:0] cmd_mux_005_src_data;                                                 // cmd_mux_005:src_data -> agent_pipeline_010:in_data
	wire          cmd_mux_005_src_ready;                                                // agent_pipeline_010:in_ready -> cmd_mux_005:src_ready
	wire    [5:0] cmd_mux_005_src_channel;                                              // cmd_mux_005:src_channel -> agent_pipeline_010:in_channel
	wire          cmd_mux_005_src_startofpacket;                                        // cmd_mux_005:src_startofpacket -> agent_pipeline_010:in_startofpacket
	wire          cmd_mux_005_src_endofpacket;                                          // cmd_mux_005:src_endofpacket -> agent_pipeline_010:in_endofpacket
	wire          agent_pipeline_010_source0_valid;                                     // agent_pipeline_010:out_valid -> msi_to_gic_gen_0_vector_slave_agent:cp_valid
	wire   [90:0] agent_pipeline_010_source0_data;                                      // agent_pipeline_010:out_data -> msi_to_gic_gen_0_vector_slave_agent:cp_data
	wire          agent_pipeline_010_source0_ready;                                     // msi_to_gic_gen_0_vector_slave_agent:cp_ready -> agent_pipeline_010:out_ready
	wire    [5:0] agent_pipeline_010_source0_channel;                                   // agent_pipeline_010:out_channel -> msi_to_gic_gen_0_vector_slave_agent:cp_channel
	wire          agent_pipeline_010_source0_startofpacket;                             // agent_pipeline_010:out_startofpacket -> msi_to_gic_gen_0_vector_slave_agent:cp_startofpacket
	wire          agent_pipeline_010_source0_endofpacket;                               // agent_pipeline_010:out_endofpacket -> msi_to_gic_gen_0_vector_slave_agent:cp_endofpacket
	wire          msi_to_gic_gen_0_vector_slave_agent_rp_valid;                         // msi_to_gic_gen_0_vector_slave_agent:rp_valid -> agent_pipeline_011:in_valid
	wire   [90:0] msi_to_gic_gen_0_vector_slave_agent_rp_data;                          // msi_to_gic_gen_0_vector_slave_agent:rp_data -> agent_pipeline_011:in_data
	wire          msi_to_gic_gen_0_vector_slave_agent_rp_ready;                         // agent_pipeline_011:in_ready -> msi_to_gic_gen_0_vector_slave_agent:rp_ready
	wire          msi_to_gic_gen_0_vector_slave_agent_rp_startofpacket;                 // msi_to_gic_gen_0_vector_slave_agent:rp_startofpacket -> agent_pipeline_011:in_startofpacket
	wire          msi_to_gic_gen_0_vector_slave_agent_rp_endofpacket;                   // msi_to_gic_gen_0_vector_slave_agent:rp_endofpacket -> agent_pipeline_011:in_endofpacket
	wire          agent_pipeline_011_source0_valid;                                     // agent_pipeline_011:out_valid -> router_007:sink_valid
	wire   [90:0] agent_pipeline_011_source0_data;                                      // agent_pipeline_011:out_data -> router_007:sink_data
	wire          agent_pipeline_011_source0_ready;                                     // router_007:sink_ready -> agent_pipeline_011:out_ready
	wire          agent_pipeline_011_source0_startofpacket;                             // agent_pipeline_011:out_startofpacket -> router_007:sink_startofpacket
	wire          agent_pipeline_011_source0_endofpacket;                               // agent_pipeline_011:out_endofpacket -> router_007:sink_endofpacket
	wire          pcie_hip_avmm_cra_agent_rdata_fifo_out_valid;                         // pcie_hip_avmm_Cra_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
	wire   [33:0] pcie_hip_avmm_cra_agent_rdata_fifo_out_data;                          // pcie_hip_avmm_Cra_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
	wire          pcie_hip_avmm_cra_agent_rdata_fifo_out_ready;                         // avalon_st_adapter:in_0_ready -> pcie_hip_avmm_Cra_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_out_0_valid;                                        // avalon_st_adapter:out_0_valid -> pcie_hip_avmm_Cra_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_out_0_data;                                         // avalon_st_adapter:out_0_data -> pcie_hip_avmm_Cra_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_out_0_ready;                                        // pcie_hip_avmm_Cra_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
	wire    [0:0] avalon_st_adapter_out_0_error;                                        // avalon_st_adapter:out_0_error -> pcie_hip_avmm_Cra_agent:rdata_fifo_sink_error
	wire          performance_counter_0_control_slave_agent_rdata_fifo_out_valid;       // performance_counter_0_control_slave_agent_rdata_fifo:out_valid -> avalon_st_adapter_001:in_0_valid
	wire   [33:0] performance_counter_0_control_slave_agent_rdata_fifo_out_data;        // performance_counter_0_control_slave_agent_rdata_fifo:out_data -> avalon_st_adapter_001:in_0_data
	wire          performance_counter_0_control_slave_agent_rdata_fifo_out_ready;       // avalon_st_adapter_001:in_0_ready -> performance_counter_0_control_slave_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_001_out_0_valid;                                    // avalon_st_adapter_001:out_0_valid -> performance_counter_0_control_slave_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_001_out_0_data;                                     // avalon_st_adapter_001:out_0_data -> performance_counter_0_control_slave_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_001_out_0_ready;                                    // performance_counter_0_control_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
	wire    [0:0] avalon_st_adapter_001_out_0_error;                                    // avalon_st_adapter_001:out_0_error -> performance_counter_0_control_slave_agent:rdata_fifo_sink_error
	wire          msgdma_0_csr_agent_rdata_fifo_src_valid;                              // msgdma_0_csr_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
	wire   [33:0] msgdma_0_csr_agent_rdata_fifo_src_data;                               // msgdma_0_csr_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
	wire          msgdma_0_csr_agent_rdata_fifo_src_ready;                              // avalon_st_adapter_002:in_0_ready -> msgdma_0_csr_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_002_out_0_valid;                                    // avalon_st_adapter_002:out_0_valid -> msgdma_0_csr_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_002_out_0_data;                                     // avalon_st_adapter_002:out_0_data -> msgdma_0_csr_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_002_out_0_ready;                                    // msgdma_0_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
	wire    [0:0] avalon_st_adapter_002_out_0_error;                                    // avalon_st_adapter_002:out_0_error -> msgdma_0_csr_agent:rdata_fifo_sink_error
	wire          msi_to_gic_gen_0_csr_agent_rdata_fifo_out_valid;                      // msi_to_gic_gen_0_csr_agent_rdata_fifo:out_valid -> avalon_st_adapter_003:in_0_valid
	wire   [33:0] msi_to_gic_gen_0_csr_agent_rdata_fifo_out_data;                       // msi_to_gic_gen_0_csr_agent_rdata_fifo:out_data -> avalon_st_adapter_003:in_0_data
	wire          msi_to_gic_gen_0_csr_agent_rdata_fifo_out_ready;                      // avalon_st_adapter_003:in_0_ready -> msi_to_gic_gen_0_csr_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_003_out_0_valid;                                    // avalon_st_adapter_003:out_0_valid -> msi_to_gic_gen_0_csr_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_003_out_0_data;                                     // avalon_st_adapter_003:out_0_data -> msi_to_gic_gen_0_csr_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_003_out_0_ready;                                    // msi_to_gic_gen_0_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
	wire    [0:0] avalon_st_adapter_003_out_0_error;                                    // avalon_st_adapter_003:out_0_error -> msi_to_gic_gen_0_csr_agent:rdata_fifo_sink_error
	wire          msgdma_0_descriptor_slave_agent_rdata_fifo_src_valid;                 // msgdma_0_descriptor_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_004:in_0_valid
	wire  [129:0] msgdma_0_descriptor_slave_agent_rdata_fifo_src_data;                  // msgdma_0_descriptor_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_004:in_0_data
	wire          msgdma_0_descriptor_slave_agent_rdata_fifo_src_ready;                 // avalon_st_adapter_004:in_0_ready -> msgdma_0_descriptor_slave_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_004_out_0_valid;                                    // avalon_st_adapter_004:out_0_valid -> msgdma_0_descriptor_slave_agent:rdata_fifo_sink_valid
	wire  [129:0] avalon_st_adapter_004_out_0_data;                                     // avalon_st_adapter_004:out_0_data -> msgdma_0_descriptor_slave_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_004_out_0_ready;                                    // msgdma_0_descriptor_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
	wire    [0:0] avalon_st_adapter_004_out_0_error;                                    // avalon_st_adapter_004:out_0_error -> msgdma_0_descriptor_slave_agent:rdata_fifo_sink_error
	wire          msi_to_gic_gen_0_vector_slave_agent_rdata_fifo_out_valid;             // msi_to_gic_gen_0_vector_slave_agent_rdata_fifo:out_valid -> avalon_st_adapter_005:in_0_valid
	wire   [33:0] msi_to_gic_gen_0_vector_slave_agent_rdata_fifo_out_data;              // msi_to_gic_gen_0_vector_slave_agent_rdata_fifo:out_data -> avalon_st_adapter_005:in_0_data
	wire          msi_to_gic_gen_0_vector_slave_agent_rdata_fifo_out_ready;             // avalon_st_adapter_005:in_0_ready -> msi_to_gic_gen_0_vector_slave_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_005_out_0_valid;                                    // avalon_st_adapter_005:out_0_valid -> msi_to_gic_gen_0_vector_slave_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_005_out_0_data;                                     // avalon_st_adapter_005:out_0_data -> msi_to_gic_gen_0_vector_slave_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_005_out_0_ready;                                    // msi_to_gic_gen_0_vector_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_005:out_0_ready
	wire    [0:0] avalon_st_adapter_005_out_0_error;                                    // avalon_st_adapter_005:out_0_error -> msi_to_gic_gen_0_vector_slave_agent:rdata_fifo_sink_error

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (15),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (15),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) pb_lwh2f_pcie_m0_translator (
		.clk                    (custom_reset_synchronizer_0_clock_out_clk),                           //                       clk.clk
		.reset                  (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),                     //                     reset.reset
		.uav_address            (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (pb_lwh2f_pcie_m0_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (pb_lwh2f_pcie_m0_waitrequest),                                        //                          .waitrequest
		.av_burstcount          (pb_lwh2f_pcie_m0_burstcount),                                         //                          .burstcount
		.av_byteenable          (pb_lwh2f_pcie_m0_byteenable),                                         //                          .byteenable
		.av_read                (pb_lwh2f_pcie_m0_read),                                               //                          .read
		.av_readdata            (pb_lwh2f_pcie_m0_readdata),                                           //                          .readdata
		.av_readdatavalid       (pb_lwh2f_pcie_m0_readdatavalid),                                      //                          .readdatavalid
		.av_write               (pb_lwh2f_pcie_m0_write),                                              //                          .write
		.av_writedata           (pb_lwh2f_pcie_m0_writedata),                                          //                          .writedata
		.av_debugaccess         (pb_lwh2f_pcie_m0_debugaccess),                                        //                          .debugaccess
		.av_beginbursttransfer  (1'b0),                                                                //               (terminated)
		.av_begintransfer       (1'b0),                                                                //               (terminated)
		.av_chipselect          (1'b0),                                                                //               (terminated)
		.av_lock                (1'b0),                                                                //               (terminated)
		.uav_clken              (),                                                                    //               (terminated)
		.av_clken               (1'b1),                                                                //               (terminated)
		.uav_response           (2'b00),                                                               //               (terminated)
		.av_response            (),                                                                    //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                //               (terminated)
		.av_writeresponsevalid  ()                                                                     //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (15),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (15),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) pb_rxm_2_msi_m0_translator (
		.clk                    (custom_reset_synchronizer_0_clock_out_clk),                          //                       clk.clk
		.reset                  (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),                    //                     reset.reset
		.uav_address            (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (pb_rxm_2_msi_m0_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (pb_rxm_2_msi_m0_waitrequest),                                        //                          .waitrequest
		.av_burstcount          (pb_rxm_2_msi_m0_burstcount),                                         //                          .burstcount
		.av_byteenable          (pb_rxm_2_msi_m0_byteenable),                                         //                          .byteenable
		.av_read                (pb_rxm_2_msi_m0_read),                                               //                          .read
		.av_readdata            (pb_rxm_2_msi_m0_readdata),                                           //                          .readdata
		.av_readdatavalid       (pb_rxm_2_msi_m0_readdatavalid),                                      //                          .readdatavalid
		.av_write               (pb_rxm_2_msi_m0_write),                                              //                          .write
		.av_writedata           (pb_rxm_2_msi_m0_writedata),                                          //                          .writedata
		.av_debugaccess         (pb_rxm_2_msi_m0_debugaccess),                                        //                          .debugaccess
		.av_beginbursttransfer  (1'b0),                                                               //               (terminated)
		.av_begintransfer       (1'b0),                                                               //               (terminated)
		.av_chipselect          (1'b0),                                                               //               (terminated)
		.av_lock                (1'b0),                                                               //               (terminated)
		.uav_clken              (),                                                                   //               (terminated)
		.av_clken               (1'b1),                                                               //               (terminated)
		.uav_response           (2'b00),                                                              //               (terminated)
		.av_response            (),                                                                   //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                               //               (terminated)
		.av_writeresponsevalid  ()                                                                    //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (14),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (15),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (1),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) pcie_hip_avmm_cra_translator (
		.clk                    (pcie_hip_avmm_coreclkout_clk),                                   //                      clk.clk
		.reset                  (pcie_hip_avmm_Cra_translator_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (pcie_hip_avmm_cra_agent_m0_address),                             // avalon_universal_slave_0.address
		.uav_burstcount         (pcie_hip_avmm_cra_agent_m0_burstcount),                          //                         .burstcount
		.uav_read               (pcie_hip_avmm_cra_agent_m0_read),                                //                         .read
		.uav_write              (pcie_hip_avmm_cra_agent_m0_write),                               //                         .write
		.uav_waitrequest        (pcie_hip_avmm_cra_agent_m0_waitrequest),                         //                         .waitrequest
		.uav_readdatavalid      (pcie_hip_avmm_cra_agent_m0_readdatavalid),                       //                         .readdatavalid
		.uav_byteenable         (pcie_hip_avmm_cra_agent_m0_byteenable),                          //                         .byteenable
		.uav_readdata           (pcie_hip_avmm_cra_agent_m0_readdata),                            //                         .readdata
		.uav_writedata          (pcie_hip_avmm_cra_agent_m0_writedata),                           //                         .writedata
		.uav_lock               (pcie_hip_avmm_cra_agent_m0_lock),                                //                         .lock
		.uav_debugaccess        (pcie_hip_avmm_cra_agent_m0_debugaccess),                         //                         .debugaccess
		.av_address             (pcie_hip_avmm_Cra_address),                                      //      avalon_anti_slave_0.address
		.av_write               (pcie_hip_avmm_Cra_write),                                        //                         .write
		.av_read                (pcie_hip_avmm_Cra_read),                                         //                         .read
		.av_readdata            (pcie_hip_avmm_Cra_readdata),                                     //                         .readdata
		.av_writedata           (pcie_hip_avmm_Cra_writedata),                                    //                         .writedata
		.av_byteenable          (pcie_hip_avmm_Cra_byteenable),                                   //                         .byteenable
		.av_waitrequest         (pcie_hip_avmm_Cra_waitrequest),                                  //                         .waitrequest
		.av_chipselect          (pcie_hip_avmm_Cra_chipselect),                                   //                         .chipselect
		.av_begintransfer       (),                                                               //              (terminated)
		.av_beginbursttransfer  (),                                                               //              (terminated)
		.av_burstcount          (),                                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                                           //              (terminated)
		.av_writebyteenable     (),                                                               //              (terminated)
		.av_lock                (),                                                               //              (terminated)
		.av_clken               (),                                                               //              (terminated)
		.uav_clken              (1'b0),                                                           //              (terminated)
		.av_debugaccess         (),                                                               //              (terminated)
		.av_outputenable        (),                                                               //              (terminated)
		.uav_response           (),                                                               //              (terminated)
		.av_response            (2'b00),                                                          //              (terminated)
		.uav_writeresponsevalid (),                                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                            //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (3),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (15),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) performance_counter_0_control_slave_translator (
		.clk                    (clk_clk_clk),                                                //                      clk.clk
		.reset                  (performance_counter_0_reset_reset_bridge_in_reset_reset),    //                    reset.reset
		.uav_address            (performance_counter_0_control_slave_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (performance_counter_0_control_slave_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (performance_counter_0_control_slave_agent_m0_read),          //                         .read
		.uav_write              (performance_counter_0_control_slave_agent_m0_write),         //                         .write
		.uav_waitrequest        (performance_counter_0_control_slave_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (performance_counter_0_control_slave_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (performance_counter_0_control_slave_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (performance_counter_0_control_slave_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (performance_counter_0_control_slave_agent_m0_writedata),     //                         .writedata
		.uav_lock               (performance_counter_0_control_slave_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (performance_counter_0_control_slave_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (performance_counter_0_control_slave_address),                //      avalon_anti_slave_0.address
		.av_write               (performance_counter_0_control_slave_write),                  //                         .write
		.av_readdata            (performance_counter_0_control_slave_readdata),               //                         .readdata
		.av_writedata           (performance_counter_0_control_slave_writedata),              //                         .writedata
		.av_begintransfer       (performance_counter_0_control_slave_begintransfer),          //                         .begintransfer
		.av_read                (),                                                           //              (terminated)
		.av_beginbursttransfer  (),                                                           //              (terminated)
		.av_burstcount          (),                                                           //              (terminated)
		.av_byteenable          (),                                                           //              (terminated)
		.av_readdatavalid       (1'b0),                                                       //              (terminated)
		.av_waitrequest         (1'b0),                                                       //              (terminated)
		.av_writebyteenable     (),                                                           //              (terminated)
		.av_lock                (),                                                           //              (terminated)
		.av_chipselect          (),                                                           //              (terminated)
		.av_clken               (),                                                           //              (terminated)
		.uav_clken              (1'b0),                                                       //              (terminated)
		.av_debugaccess         (),                                                           //              (terminated)
		.av_outputenable        (),                                                           //              (terminated)
		.uav_response           (),                                                           //              (terminated)
		.av_response            (2'b00),                                                      //              (terminated)
		.uav_writeresponsevalid (),                                                           //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                        //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (3),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (15),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) msgdma_0_csr_translator (
		.clk                    (custom_reset_synchronizer_0_clock_out_clk),       //                      clk.clk
		.reset                  (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (msgdma_0_csr_agent_m0_address),                   // avalon_universal_slave_0.address
		.uav_burstcount         (msgdma_0_csr_agent_m0_burstcount),                //                         .burstcount
		.uav_read               (msgdma_0_csr_agent_m0_read),                      //                         .read
		.uav_write              (msgdma_0_csr_agent_m0_write),                     //                         .write
		.uav_waitrequest        (msgdma_0_csr_agent_m0_waitrequest),               //                         .waitrequest
		.uav_readdatavalid      (msgdma_0_csr_agent_m0_readdatavalid),             //                         .readdatavalid
		.uav_byteenable         (msgdma_0_csr_agent_m0_byteenable),                //                         .byteenable
		.uav_readdata           (msgdma_0_csr_agent_m0_readdata),                  //                         .readdata
		.uav_writedata          (msgdma_0_csr_agent_m0_writedata),                 //                         .writedata
		.uav_lock               (msgdma_0_csr_agent_m0_lock),                      //                         .lock
		.uav_debugaccess        (msgdma_0_csr_agent_m0_debugaccess),               //                         .debugaccess
		.av_address             (msgdma_0_csr_address),                            //      avalon_anti_slave_0.address
		.av_write               (msgdma_0_csr_write),                              //                         .write
		.av_read                (msgdma_0_csr_read),                               //                         .read
		.av_readdata            (msgdma_0_csr_readdata),                           //                         .readdata
		.av_writedata           (msgdma_0_csr_writedata),                          //                         .writedata
		.av_byteenable          (msgdma_0_csr_byteenable),                         //                         .byteenable
		.av_begintransfer       (),                                                //              (terminated)
		.av_beginbursttransfer  (),                                                //              (terminated)
		.av_burstcount          (),                                                //              (terminated)
		.av_readdatavalid       (1'b0),                                            //              (terminated)
		.av_waitrequest         (1'b0),                                            //              (terminated)
		.av_writebyteenable     (),                                                //              (terminated)
		.av_lock                (),                                                //              (terminated)
		.av_chipselect          (),                                                //              (terminated)
		.av_clken               (),                                                //              (terminated)
		.uav_clken              (1'b0),                                            //              (terminated)
		.av_debugaccess         (),                                                //              (terminated)
		.av_outputenable        (),                                                //              (terminated)
		.uav_response           (),                                                //              (terminated)
		.av_response            (2'b00),                                           //              (terminated)
		.uav_writeresponsevalid (),                                                //              (terminated)
		.av_writeresponsevalid  (1'b0)                                             //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (15),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) msi_to_gic_gen_0_csr_translator (
		.clk                    (clk_clk_clk),                                             //                      clk.clk
		.reset                  (performance_counter_0_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (msi_to_gic_gen_0_csr_agent_m0_address),                   // avalon_universal_slave_0.address
		.uav_burstcount         (msi_to_gic_gen_0_csr_agent_m0_burstcount),                //                         .burstcount
		.uav_read               (msi_to_gic_gen_0_csr_agent_m0_read),                      //                         .read
		.uav_write              (msi_to_gic_gen_0_csr_agent_m0_write),                     //                         .write
		.uav_waitrequest        (msi_to_gic_gen_0_csr_agent_m0_waitrequest),               //                         .waitrequest
		.uav_readdatavalid      (msi_to_gic_gen_0_csr_agent_m0_readdatavalid),             //                         .readdatavalid
		.uav_byteenable         (msi_to_gic_gen_0_csr_agent_m0_byteenable),                //                         .byteenable
		.uav_readdata           (msi_to_gic_gen_0_csr_agent_m0_readdata),                  //                         .readdata
		.uav_writedata          (msi_to_gic_gen_0_csr_agent_m0_writedata),                 //                         .writedata
		.uav_lock               (msi_to_gic_gen_0_csr_agent_m0_lock),                      //                         .lock
		.uav_debugaccess        (msi_to_gic_gen_0_csr_agent_m0_debugaccess),               //                         .debugaccess
		.av_address             (msi_to_gic_gen_0_csr_address),                            //      avalon_anti_slave_0.address
		.av_write               (msi_to_gic_gen_0_csr_write),                              //                         .write
		.av_read                (msi_to_gic_gen_0_csr_read),                               //                         .read
		.av_readdata            (msi_to_gic_gen_0_csr_readdata),                           //                         .readdata
		.av_writedata           (msi_to_gic_gen_0_csr_writedata),                          //                         .writedata
		.av_begintransfer       (),                                                        //              (terminated)
		.av_beginbursttransfer  (),                                                        //              (terminated)
		.av_burstcount          (),                                                        //              (terminated)
		.av_byteenable          (),                                                        //              (terminated)
		.av_readdatavalid       (1'b0),                                                    //              (terminated)
		.av_waitrequest         (1'b0),                                                    //              (terminated)
		.av_writebyteenable     (),                                                        //              (terminated)
		.av_lock                (),                                                        //              (terminated)
		.av_chipselect          (),                                                        //              (terminated)
		.av_clken               (),                                                        //              (terminated)
		.uav_clken              (1'b0),                                                    //              (terminated)
		.av_debugaccess         (),                                                        //              (terminated)
		.av_outputenable        (),                                                        //              (terminated)
		.uav_response           (),                                                        //              (terminated)
		.av_response            (2'b00),                                                   //              (terminated)
		.uav_writeresponsevalid (),                                                        //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                     //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (1),
		.AV_DATA_W                      (128),
		.UAV_DATA_W                     (128),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (16),
		.UAV_BYTEENABLE_W               (16),
		.UAV_ADDRESS_W                  (15),
		.UAV_BURSTCOUNT_W               (5),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (16),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) msgdma_0_descriptor_slave_translator (
		.clk                    (custom_reset_synchronizer_0_clock_out_clk),                                                                                             //                      clk.clk
		.reset                  (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),                                                                                       //                    reset.reset
		.uav_address            (msgdma_0_descriptor_slave_agent_m0_address),                                                                                            // avalon_universal_slave_0.address
		.uav_burstcount         (msgdma_0_descriptor_slave_agent_m0_burstcount),                                                                                         //                         .burstcount
		.uav_read               (msgdma_0_descriptor_slave_agent_m0_read),                                                                                               //                         .read
		.uav_write              (msgdma_0_descriptor_slave_agent_m0_write),                                                                                              //                         .write
		.uav_waitrequest        (msgdma_0_descriptor_slave_agent_m0_waitrequest),                                                                                        //                         .waitrequest
		.uav_readdatavalid      (msgdma_0_descriptor_slave_agent_m0_readdatavalid),                                                                                      //                         .readdatavalid
		.uav_byteenable         (msgdma_0_descriptor_slave_agent_m0_byteenable),                                                                                         //                         .byteenable
		.uav_readdata           (msgdma_0_descriptor_slave_agent_m0_readdata),                                                                                           //                         .readdata
		.uav_writedata          (msgdma_0_descriptor_slave_agent_m0_writedata),                                                                                          //                         .writedata
		.uav_lock               (msgdma_0_descriptor_slave_agent_m0_lock),                                                                                               //                         .lock
		.uav_debugaccess        (msgdma_0_descriptor_slave_agent_m0_debugaccess),                                                                                        //                         .debugaccess
		.av_write               (msgdma_0_descriptor_slave_write),                                                                                                       //      avalon_anti_slave_0.write
		.av_writedata           (msgdma_0_descriptor_slave_writedata),                                                                                                   //                         .writedata
		.av_byteenable          (msgdma_0_descriptor_slave_byteenable),                                                                                                  //                         .byteenable
		.av_waitrequest         (msgdma_0_descriptor_slave_waitrequest),                                                                                                 //                         .waitrequest
		.av_address             (),                                                                                                                                      //              (terminated)
		.av_read                (),                                                                                                                                      //              (terminated)
		.av_readdata            (128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011011110101011011101111010101101), //              (terminated)
		.av_begintransfer       (),                                                                                                                                      //              (terminated)
		.av_beginbursttransfer  (),                                                                                                                                      //              (terminated)
		.av_burstcount          (),                                                                                                                                      //              (terminated)
		.av_readdatavalid       (1'b0),                                                                                                                                  //              (terminated)
		.av_writebyteenable     (),                                                                                                                                      //              (terminated)
		.av_lock                (),                                                                                                                                      //              (terminated)
		.av_chipselect          (),                                                                                                                                      //              (terminated)
		.av_clken               (),                                                                                                                                      //              (terminated)
		.uav_clken              (1'b0),                                                                                                                                  //              (terminated)
		.av_debugaccess         (),                                                                                                                                      //              (terminated)
		.av_outputenable        (),                                                                                                                                      //              (terminated)
		.uav_response           (),                                                                                                                                      //              (terminated)
		.av_response            (2'b00),                                                                                                                                 //              (terminated)
		.uav_writeresponsevalid (),                                                                                                                                      //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                                                                                                   //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (5),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (15),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) msi_to_gic_gen_0_vector_slave_translator (
		.clk                    (clk_clk_clk),                                             //                      clk.clk
		.reset                  (performance_counter_0_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (msi_to_gic_gen_0_vector_slave_agent_m0_address),          // avalon_universal_slave_0.address
		.uav_burstcount         (msi_to_gic_gen_0_vector_slave_agent_m0_burstcount),       //                         .burstcount
		.uav_read               (msi_to_gic_gen_0_vector_slave_agent_m0_read),             //                         .read
		.uav_write              (msi_to_gic_gen_0_vector_slave_agent_m0_write),            //                         .write
		.uav_waitrequest        (msi_to_gic_gen_0_vector_slave_agent_m0_waitrequest),      //                         .waitrequest
		.uav_readdatavalid      (msi_to_gic_gen_0_vector_slave_agent_m0_readdatavalid),    //                         .readdatavalid
		.uav_byteenable         (msi_to_gic_gen_0_vector_slave_agent_m0_byteenable),       //                         .byteenable
		.uav_readdata           (msi_to_gic_gen_0_vector_slave_agent_m0_readdata),         //                         .readdata
		.uav_writedata          (msi_to_gic_gen_0_vector_slave_agent_m0_writedata),        //                         .writedata
		.uav_lock               (msi_to_gic_gen_0_vector_slave_agent_m0_lock),             //                         .lock
		.uav_debugaccess        (msi_to_gic_gen_0_vector_slave_agent_m0_debugaccess),      //                         .debugaccess
		.av_address             (msi_to_gic_gen_0_vector_slave_address),                   //      avalon_anti_slave_0.address
		.av_write               (msi_to_gic_gen_0_vector_slave_write),                     //                         .write
		.av_read                (msi_to_gic_gen_0_vector_slave_read),                      //                         .read
		.av_readdata            (msi_to_gic_gen_0_vector_slave_readdata),                  //                         .readdata
		.av_writedata           (msi_to_gic_gen_0_vector_slave_writedata),                 //                         .writedata
		.av_begintransfer       (),                                                        //              (terminated)
		.av_beginbursttransfer  (),                                                        //              (terminated)
		.av_burstcount          (),                                                        //              (terminated)
		.av_byteenable          (),                                                        //              (terminated)
		.av_readdatavalid       (1'b0),                                                    //              (terminated)
		.av_waitrequest         (1'b0),                                                    //              (terminated)
		.av_writebyteenable     (),                                                        //              (terminated)
		.av_lock                (),                                                        //              (terminated)
		.av_chipselect          (),                                                        //              (terminated)
		.av_clken               (),                                                        //              (terminated)
		.uav_clken              (1'b0),                                                    //              (terminated)
		.av_debugaccess         (),                                                        //              (terminated)
		.av_outputenable        (),                                                        //              (terminated)
		.uav_response           (),                                                        //              (terminated)
		.av_response            (2'b00),                                                   //              (terminated)
		.uav_writeresponsevalid (),                                                        //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                     //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (90),
		.PKT_ORI_BURST_SIZE_L      (88),
		.PKT_RESPONSE_STATUS_H     (87),
		.PKT_RESPONSE_STATUS_L     (86),
		.PKT_QOS_H                 (71),
		.PKT_QOS_L                 (71),
		.PKT_DATA_SIDEBAND_H       (69),
		.PKT_DATA_SIDEBAND_L       (69),
		.PKT_ADDR_SIDEBAND_H       (68),
		.PKT_ADDR_SIDEBAND_L       (68),
		.PKT_BURST_TYPE_H          (67),
		.PKT_BURST_TYPE_L          (66),
		.PKT_CACHE_H               (85),
		.PKT_CACHE_L               (82),
		.PKT_THREAD_ID_H           (78),
		.PKT_THREAD_ID_L           (78),
		.PKT_BURST_SIZE_H          (65),
		.PKT_BURST_SIZE_L          (63),
		.PKT_TRANS_EXCLUSIVE       (56),
		.PKT_TRANS_LOCK            (55),
		.PKT_BEGIN_BURST           (70),
		.PKT_PROTECTION_H          (81),
		.PKT_PROTECTION_L          (79),
		.PKT_BURSTWRAP_H           (62),
		.PKT_BURSTWRAP_L           (62),
		.PKT_BYTE_CNT_H            (61),
		.PKT_BYTE_CNT_L            (57),
		.PKT_ADDR_H                (50),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (51),
		.PKT_TRANS_POSTED          (52),
		.PKT_TRANS_WRITE           (53),
		.PKT_TRANS_READ            (54),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (74),
		.PKT_SRC_ID_L              (72),
		.PKT_DEST_ID_H             (77),
		.PKT_DEST_ID_L             (75),
		.ST_DATA_W                 (91),
		.ST_CHANNEL_W              (6),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (1),
		.ID                        (0),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) pb_lwh2f_pcie_m0_agent (
		.clk                   (custom_reset_synchronizer_0_clock_out_clk),                           //       clk.clk
		.reset                 (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),                     // clk_reset.reset
		.av_address            (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (pb_lwh2f_pcie_m0_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (pb_lwh2f_pcie_m0_agent_cp_valid),                                     //        cp.valid
		.cp_data               (pb_lwh2f_pcie_m0_agent_cp_data),                                      //          .data
		.cp_startofpacket      (pb_lwh2f_pcie_m0_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (pb_lwh2f_pcie_m0_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (pb_lwh2f_pcie_m0_agent_cp_ready),                                     //          .ready
		.rp_valid              (pb_lwh2f_pcie_m0_limiter_rsp_src_valid),                              //        rp.valid
		.rp_data               (pb_lwh2f_pcie_m0_limiter_rsp_src_data),                               //          .data
		.rp_channel            (pb_lwh2f_pcie_m0_limiter_rsp_src_channel),                            //          .channel
		.rp_startofpacket      (pb_lwh2f_pcie_m0_limiter_rsp_src_startofpacket),                      //          .startofpacket
		.rp_endofpacket        (pb_lwh2f_pcie_m0_limiter_rsp_src_endofpacket),                        //          .endofpacket
		.rp_ready              (pb_lwh2f_pcie_m0_limiter_rsp_src_ready),                              //          .ready
		.av_response           (),                                                                    // (terminated)
		.av_writeresponsevalid ()                                                                     // (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (90),
		.PKT_ORI_BURST_SIZE_L      (88),
		.PKT_RESPONSE_STATUS_H     (87),
		.PKT_RESPONSE_STATUS_L     (86),
		.PKT_QOS_H                 (71),
		.PKT_QOS_L                 (71),
		.PKT_DATA_SIDEBAND_H       (69),
		.PKT_DATA_SIDEBAND_L       (69),
		.PKT_ADDR_SIDEBAND_H       (68),
		.PKT_ADDR_SIDEBAND_L       (68),
		.PKT_BURST_TYPE_H          (67),
		.PKT_BURST_TYPE_L          (66),
		.PKT_CACHE_H               (85),
		.PKT_CACHE_L               (82),
		.PKT_THREAD_ID_H           (78),
		.PKT_THREAD_ID_L           (78),
		.PKT_BURST_SIZE_H          (65),
		.PKT_BURST_SIZE_L          (63),
		.PKT_TRANS_EXCLUSIVE       (56),
		.PKT_TRANS_LOCK            (55),
		.PKT_BEGIN_BURST           (70),
		.PKT_PROTECTION_H          (81),
		.PKT_PROTECTION_L          (79),
		.PKT_BURSTWRAP_H           (62),
		.PKT_BURSTWRAP_L           (62),
		.PKT_BYTE_CNT_H            (61),
		.PKT_BYTE_CNT_L            (57),
		.PKT_ADDR_H                (50),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (51),
		.PKT_TRANS_POSTED          (52),
		.PKT_TRANS_WRITE           (53),
		.PKT_TRANS_READ            (54),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (74),
		.PKT_SRC_ID_L              (72),
		.PKT_DEST_ID_H             (77),
		.PKT_DEST_ID_L             (75),
		.ST_DATA_W                 (91),
		.ST_CHANNEL_W              (6),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (1),
		.ID                        (1),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) pb_rxm_2_msi_m0_agent (
		.clk                   (custom_reset_synchronizer_0_clock_out_clk),                          //       clk.clk
		.reset                 (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),                    // clk_reset.reset
		.av_address            (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (pb_rxm_2_msi_m0_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (pb_rxm_2_msi_m0_agent_cp_valid),                                     //        cp.valid
		.cp_data               (pb_rxm_2_msi_m0_agent_cp_data),                                      //          .data
		.cp_startofpacket      (pb_rxm_2_msi_m0_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (pb_rxm_2_msi_m0_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (pb_rxm_2_msi_m0_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_001_src_valid),                                              //        rp.valid
		.rp_data               (rsp_mux_001_src_data),                                               //          .data
		.rp_channel            (rsp_mux_001_src_channel),                                            //          .channel
		.rp_startofpacket      (rsp_mux_001_src_startofpacket),                                      //          .startofpacket
		.rp_endofpacket        (rsp_mux_001_src_endofpacket),                                        //          .endofpacket
		.rp_ready              (rsp_mux_001_src_ready),                                              //          .ready
		.av_response           (),                                                                   // (terminated)
		.av_writeresponsevalid ()                                                                    // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (90),
		.PKT_ORI_BURST_SIZE_L      (88),
		.PKT_RESPONSE_STATUS_H     (87),
		.PKT_RESPONSE_STATUS_L     (86),
		.PKT_BURST_SIZE_H          (65),
		.PKT_BURST_SIZE_L          (63),
		.PKT_TRANS_LOCK            (55),
		.PKT_BEGIN_BURST           (70),
		.PKT_PROTECTION_H          (81),
		.PKT_PROTECTION_L          (79),
		.PKT_BURSTWRAP_H           (62),
		.PKT_BURSTWRAP_L           (62),
		.PKT_BYTE_CNT_H            (61),
		.PKT_BYTE_CNT_L            (57),
		.PKT_ADDR_H                (50),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (51),
		.PKT_TRANS_POSTED          (52),
		.PKT_TRANS_WRITE           (53),
		.PKT_TRANS_READ            (54),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (74),
		.PKT_SRC_ID_L              (72),
		.PKT_DEST_ID_H             (77),
		.PKT_DEST_ID_L             (75),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (91),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) pcie_hip_avmm_cra_agent (
		.clk                     (pcie_hip_avmm_coreclkout_clk),                                   //             clk.clk
		.reset                   (pcie_hip_avmm_Cra_translator_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (pcie_hip_avmm_cra_agent_m0_address),                             //              m0.address
		.m0_burstcount           (pcie_hip_avmm_cra_agent_m0_burstcount),                          //                .burstcount
		.m0_byteenable           (pcie_hip_avmm_cra_agent_m0_byteenable),                          //                .byteenable
		.m0_debugaccess          (pcie_hip_avmm_cra_agent_m0_debugaccess),                         //                .debugaccess
		.m0_lock                 (pcie_hip_avmm_cra_agent_m0_lock),                                //                .lock
		.m0_readdata             (pcie_hip_avmm_cra_agent_m0_readdata),                            //                .readdata
		.m0_readdatavalid        (pcie_hip_avmm_cra_agent_m0_readdatavalid),                       //                .readdatavalid
		.m0_read                 (pcie_hip_avmm_cra_agent_m0_read),                                //                .read
		.m0_waitrequest          (pcie_hip_avmm_cra_agent_m0_waitrequest),                         //                .waitrequest
		.m0_writedata            (pcie_hip_avmm_cra_agent_m0_writedata),                           //                .writedata
		.m0_write                (pcie_hip_avmm_cra_agent_m0_write),                               //                .write
		.rp_endofpacket          (pcie_hip_avmm_cra_agent_rp_endofpacket),                         //              rp.endofpacket
		.rp_ready                (pcie_hip_avmm_cra_agent_rp_ready),                               //                .ready
		.rp_valid                (pcie_hip_avmm_cra_agent_rp_valid),                               //                .valid
		.rp_data                 (pcie_hip_avmm_cra_agent_rp_data),                                //                .data
		.rp_startofpacket        (pcie_hip_avmm_cra_agent_rp_startofpacket),                       //                .startofpacket
		.cp_ready                (agent_pipeline_source0_ready),                                   //              cp.ready
		.cp_valid                (agent_pipeline_source0_valid),                                   //                .valid
		.cp_data                 (agent_pipeline_source0_data),                                    //                .data
		.cp_startofpacket        (agent_pipeline_source0_startofpacket),                           //                .startofpacket
		.cp_endofpacket          (agent_pipeline_source0_endofpacket),                             //                .endofpacket
		.cp_channel              (agent_pipeline_source0_channel),                                 //                .channel
		.rf_sink_ready           (pcie_hip_avmm_cra_agent_rsp_fifo_out_ready),                     //         rf_sink.ready
		.rf_sink_valid           (pcie_hip_avmm_cra_agent_rsp_fifo_out_valid),                     //                .valid
		.rf_sink_startofpacket   (pcie_hip_avmm_cra_agent_rsp_fifo_out_startofpacket),             //                .startofpacket
		.rf_sink_endofpacket     (pcie_hip_avmm_cra_agent_rsp_fifo_out_endofpacket),               //                .endofpacket
		.rf_sink_data            (pcie_hip_avmm_cra_agent_rsp_fifo_out_data),                      //                .data
		.rf_source_ready         (pcie_hip_avmm_cra_agent_rf_source_ready),                        //       rf_source.ready
		.rf_source_valid         (pcie_hip_avmm_cra_agent_rf_source_valid),                        //                .valid
		.rf_source_startofpacket (pcie_hip_avmm_cra_agent_rf_source_startofpacket),                //                .startofpacket
		.rf_source_endofpacket   (pcie_hip_avmm_cra_agent_rf_source_endofpacket),                  //                .endofpacket
		.rf_source_data          (pcie_hip_avmm_cra_agent_rf_source_data),                         //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                                  // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                                  //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                                   //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                                  //                .error
		.rdata_fifo_src_ready    (pcie_hip_avmm_cra_agent_rdata_fifo_src_ready),                   //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (pcie_hip_avmm_cra_agent_rdata_fifo_src_valid),                   //                .valid
		.rdata_fifo_src_data     (pcie_hip_avmm_cra_agent_rdata_fifo_src_data),                    //                .data
		.m0_response             (2'b00),                                                          //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (92),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) pcie_hip_avmm_cra_agent_rsp_fifo (
		.clk               (pcie_hip_avmm_coreclkout_clk),                                   //       clk.clk
		.reset             (pcie_hip_avmm_Cra_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (pcie_hip_avmm_cra_agent_rf_source_data),                         //        in.data
		.in_valid          (pcie_hip_avmm_cra_agent_rf_source_valid),                        //          .valid
		.in_ready          (pcie_hip_avmm_cra_agent_rf_source_ready),                        //          .ready
		.in_startofpacket  (pcie_hip_avmm_cra_agent_rf_source_startofpacket),                //          .startofpacket
		.in_endofpacket    (pcie_hip_avmm_cra_agent_rf_source_endofpacket),                  //          .endofpacket
		.out_data          (pcie_hip_avmm_cra_agent_rsp_fifo_out_data),                      //       out.data
		.out_valid         (pcie_hip_avmm_cra_agent_rsp_fifo_out_valid),                     //          .valid
		.out_ready         (pcie_hip_avmm_cra_agent_rsp_fifo_out_ready),                     //          .ready
		.out_startofpacket (pcie_hip_avmm_cra_agent_rsp_fifo_out_startofpacket),             //          .startofpacket
		.out_endofpacket   (pcie_hip_avmm_cra_agent_rsp_fifo_out_endofpacket),               //          .endofpacket
		.csr_address       (2'b00),                                                          // (terminated)
		.csr_read          (1'b0),                                                           // (terminated)
		.csr_write         (1'b0),                                                           // (terminated)
		.csr_readdata      (),                                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                           // (terminated)
		.almost_full_data  (),                                                               // (terminated)
		.almost_empty_data (),                                                               // (terminated)
		.in_empty          (1'b0),                                                           // (terminated)
		.out_empty         (),                                                               // (terminated)
		.in_error          (1'b0),                                                           // (terminated)
		.out_error         (),                                                               // (terminated)
		.in_channel        (1'b0),                                                           // (terminated)
		.out_channel       ()                                                                // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) pcie_hip_avmm_cra_agent_rdata_fifo (
		.clk               (pcie_hip_avmm_coreclkout_clk),                                   //       clk.clk
		.reset             (pcie_hip_avmm_Cra_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (pcie_hip_avmm_cra_agent_rdata_fifo_src_data),                    //        in.data
		.in_valid          (pcie_hip_avmm_cra_agent_rdata_fifo_src_valid),                   //          .valid
		.in_ready          (pcie_hip_avmm_cra_agent_rdata_fifo_src_ready),                   //          .ready
		.out_data          (pcie_hip_avmm_cra_agent_rdata_fifo_out_data),                    //       out.data
		.out_valid         (pcie_hip_avmm_cra_agent_rdata_fifo_out_valid),                   //          .valid
		.out_ready         (pcie_hip_avmm_cra_agent_rdata_fifo_out_ready),                   //          .ready
		.csr_address       (2'b00),                                                          // (terminated)
		.csr_read          (1'b0),                                                           // (terminated)
		.csr_write         (1'b0),                                                           // (terminated)
		.csr_readdata      (),                                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                           // (terminated)
		.almost_full_data  (),                                                               // (terminated)
		.almost_empty_data (),                                                               // (terminated)
		.in_startofpacket  (1'b0),                                                           // (terminated)
		.in_endofpacket    (1'b0),                                                           // (terminated)
		.out_startofpacket (),                                                               // (terminated)
		.out_endofpacket   (),                                                               // (terminated)
		.in_empty          (1'b0),                                                           // (terminated)
		.out_empty         (),                                                               // (terminated)
		.in_error          (1'b0),                                                           // (terminated)
		.out_error         (),                                                               // (terminated)
		.in_channel        (1'b0),                                                           // (terminated)
		.out_channel       ()                                                                // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (90),
		.PKT_ORI_BURST_SIZE_L      (88),
		.PKT_RESPONSE_STATUS_H     (87),
		.PKT_RESPONSE_STATUS_L     (86),
		.PKT_BURST_SIZE_H          (65),
		.PKT_BURST_SIZE_L          (63),
		.PKT_TRANS_LOCK            (55),
		.PKT_BEGIN_BURST           (70),
		.PKT_PROTECTION_H          (81),
		.PKT_PROTECTION_L          (79),
		.PKT_BURSTWRAP_H           (62),
		.PKT_BURSTWRAP_L           (62),
		.PKT_BYTE_CNT_H            (61),
		.PKT_BYTE_CNT_L            (57),
		.PKT_ADDR_H                (50),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (51),
		.PKT_TRANS_POSTED          (52),
		.PKT_TRANS_WRITE           (53),
		.PKT_TRANS_READ            (54),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (74),
		.PKT_SRC_ID_L              (72),
		.PKT_DEST_ID_H             (77),
		.PKT_DEST_ID_L             (75),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (91),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) performance_counter_0_control_slave_agent (
		.clk                     (clk_clk_clk),                                                          //             clk.clk
		.reset                   (performance_counter_0_reset_reset_bridge_in_reset_reset),              //       clk_reset.reset
		.m0_address              (performance_counter_0_control_slave_agent_m0_address),                 //              m0.address
		.m0_burstcount           (performance_counter_0_control_slave_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (performance_counter_0_control_slave_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (performance_counter_0_control_slave_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (performance_counter_0_control_slave_agent_m0_lock),                    //                .lock
		.m0_readdata             (performance_counter_0_control_slave_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (performance_counter_0_control_slave_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (performance_counter_0_control_slave_agent_m0_read),                    //                .read
		.m0_waitrequest          (performance_counter_0_control_slave_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (performance_counter_0_control_slave_agent_m0_writedata),               //                .writedata
		.m0_write                (performance_counter_0_control_slave_agent_m0_write),                   //                .write
		.rp_endofpacket          (performance_counter_0_control_slave_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (performance_counter_0_control_slave_agent_rp_ready),                   //                .ready
		.rp_valid                (performance_counter_0_control_slave_agent_rp_valid),                   //                .valid
		.rp_data                 (performance_counter_0_control_slave_agent_rp_data),                    //                .data
		.rp_startofpacket        (performance_counter_0_control_slave_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (agent_pipeline_002_source0_ready),                                     //              cp.ready
		.cp_valid                (agent_pipeline_002_source0_valid),                                     //                .valid
		.cp_data                 (agent_pipeline_002_source0_data),                                      //                .data
		.cp_startofpacket        (agent_pipeline_002_source0_startofpacket),                             //                .startofpacket
		.cp_endofpacket          (agent_pipeline_002_source0_endofpacket),                               //                .endofpacket
		.cp_channel              (agent_pipeline_002_source0_channel),                                   //                .channel
		.rf_sink_ready           (performance_counter_0_control_slave_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (performance_counter_0_control_slave_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (performance_counter_0_control_slave_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (performance_counter_0_control_slave_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (performance_counter_0_control_slave_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (performance_counter_0_control_slave_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (performance_counter_0_control_slave_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (performance_counter_0_control_slave_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (performance_counter_0_control_slave_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (performance_counter_0_control_slave_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_001_out_0_ready),                                    // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_001_out_0_valid),                                    //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_001_out_0_data),                                     //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_001_out_0_error),                                    //                .error
		.rdata_fifo_src_ready    (performance_counter_0_control_slave_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (performance_counter_0_control_slave_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (performance_counter_0_control_slave_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                                //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                                  //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (92),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) performance_counter_0_control_slave_agent_rsp_fifo (
		.clk               (clk_clk_clk),                                                          //       clk.clk
		.reset             (performance_counter_0_reset_reset_bridge_in_reset_reset),              // clk_reset.reset
		.in_data           (performance_counter_0_control_slave_agent_rf_source_data),             //        in.data
		.in_valid          (performance_counter_0_control_slave_agent_rf_source_valid),            //          .valid
		.in_ready          (performance_counter_0_control_slave_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (performance_counter_0_control_slave_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (performance_counter_0_control_slave_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (performance_counter_0_control_slave_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (performance_counter_0_control_slave_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (performance_counter_0_control_slave_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (performance_counter_0_control_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (performance_counter_0_control_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                // (terminated)
		.csr_read          (1'b0),                                                                 // (terminated)
		.csr_write         (1'b0),                                                                 // (terminated)
		.csr_readdata      (),                                                                     // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                 // (terminated)
		.almost_full_data  (),                                                                     // (terminated)
		.almost_empty_data (),                                                                     // (terminated)
		.in_empty          (1'b0),                                                                 // (terminated)
		.out_empty         (),                                                                     // (terminated)
		.in_error          (1'b0),                                                                 // (terminated)
		.out_error         (),                                                                     // (terminated)
		.in_channel        (1'b0),                                                                 // (terminated)
		.out_channel       ()                                                                      // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) performance_counter_0_control_slave_agent_rdata_fifo (
		.clk               (clk_clk_clk),                                                    //       clk.clk
		.reset             (performance_counter_0_reset_reset_bridge_in_reset_reset),        // clk_reset.reset
		.in_data           (performance_counter_0_control_slave_agent_rdata_fifo_src_data),  //        in.data
		.in_valid          (performance_counter_0_control_slave_agent_rdata_fifo_src_valid), //          .valid
		.in_ready          (performance_counter_0_control_slave_agent_rdata_fifo_src_ready), //          .ready
		.out_data          (performance_counter_0_control_slave_agent_rdata_fifo_out_data),  //       out.data
		.out_valid         (performance_counter_0_control_slave_agent_rdata_fifo_out_valid), //          .valid
		.out_ready         (performance_counter_0_control_slave_agent_rdata_fifo_out_ready), //          .ready
		.csr_address       (2'b00),                                                          // (terminated)
		.csr_read          (1'b0),                                                           // (terminated)
		.csr_write         (1'b0),                                                           // (terminated)
		.csr_readdata      (),                                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                           // (terminated)
		.almost_full_data  (),                                                               // (terminated)
		.almost_empty_data (),                                                               // (terminated)
		.in_startofpacket  (1'b0),                                                           // (terminated)
		.in_endofpacket    (1'b0),                                                           // (terminated)
		.out_startofpacket (),                                                               // (terminated)
		.out_endofpacket   (),                                                               // (terminated)
		.in_empty          (1'b0),                                                           // (terminated)
		.out_empty         (),                                                               // (terminated)
		.in_error          (1'b0),                                                           // (terminated)
		.out_error         (),                                                               // (terminated)
		.in_channel        (1'b0),                                                           // (terminated)
		.out_channel       ()                                                                // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (90),
		.PKT_ORI_BURST_SIZE_L      (88),
		.PKT_RESPONSE_STATUS_H     (87),
		.PKT_RESPONSE_STATUS_L     (86),
		.PKT_BURST_SIZE_H          (65),
		.PKT_BURST_SIZE_L          (63),
		.PKT_TRANS_LOCK            (55),
		.PKT_BEGIN_BURST           (70),
		.PKT_PROTECTION_H          (81),
		.PKT_PROTECTION_L          (79),
		.PKT_BURSTWRAP_H           (62),
		.PKT_BURSTWRAP_L           (62),
		.PKT_BYTE_CNT_H            (61),
		.PKT_BYTE_CNT_L            (57),
		.PKT_ADDR_H                (50),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (51),
		.PKT_TRANS_POSTED          (52),
		.PKT_TRANS_WRITE           (53),
		.PKT_TRANS_READ            (54),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (74),
		.PKT_SRC_ID_L              (72),
		.PKT_DEST_ID_H             (77),
		.PKT_DEST_ID_L             (75),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (91),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) msgdma_0_csr_agent (
		.clk                     (custom_reset_synchronizer_0_clock_out_clk),       //             clk.clk
		.reset                   (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (msgdma_0_csr_agent_m0_address),                   //              m0.address
		.m0_burstcount           (msgdma_0_csr_agent_m0_burstcount),                //                .burstcount
		.m0_byteenable           (msgdma_0_csr_agent_m0_byteenable),                //                .byteenable
		.m0_debugaccess          (msgdma_0_csr_agent_m0_debugaccess),               //                .debugaccess
		.m0_lock                 (msgdma_0_csr_agent_m0_lock),                      //                .lock
		.m0_readdata             (msgdma_0_csr_agent_m0_readdata),                  //                .readdata
		.m0_readdatavalid        (msgdma_0_csr_agent_m0_readdatavalid),             //                .readdatavalid
		.m0_read                 (msgdma_0_csr_agent_m0_read),                      //                .read
		.m0_waitrequest          (msgdma_0_csr_agent_m0_waitrequest),               //                .waitrequest
		.m0_writedata            (msgdma_0_csr_agent_m0_writedata),                 //                .writedata
		.m0_write                (msgdma_0_csr_agent_m0_write),                     //                .write
		.rp_endofpacket          (msgdma_0_csr_agent_rp_endofpacket),               //              rp.endofpacket
		.rp_ready                (msgdma_0_csr_agent_rp_ready),                     //                .ready
		.rp_valid                (msgdma_0_csr_agent_rp_valid),                     //                .valid
		.rp_data                 (msgdma_0_csr_agent_rp_data),                      //                .data
		.rp_startofpacket        (msgdma_0_csr_agent_rp_startofpacket),             //                .startofpacket
		.cp_ready                (agent_pipeline_004_source0_ready),                //              cp.ready
		.cp_valid                (agent_pipeline_004_source0_valid),                //                .valid
		.cp_data                 (agent_pipeline_004_source0_data),                 //                .data
		.cp_startofpacket        (agent_pipeline_004_source0_startofpacket),        //                .startofpacket
		.cp_endofpacket          (agent_pipeline_004_source0_endofpacket),          //                .endofpacket
		.cp_channel              (agent_pipeline_004_source0_channel),              //                .channel
		.rf_sink_ready           (msgdma_0_csr_agent_rsp_fifo_out_ready),           //         rf_sink.ready
		.rf_sink_valid           (msgdma_0_csr_agent_rsp_fifo_out_valid),           //                .valid
		.rf_sink_startofpacket   (msgdma_0_csr_agent_rsp_fifo_out_startofpacket),   //                .startofpacket
		.rf_sink_endofpacket     (msgdma_0_csr_agent_rsp_fifo_out_endofpacket),     //                .endofpacket
		.rf_sink_data            (msgdma_0_csr_agent_rsp_fifo_out_data),            //                .data
		.rf_source_ready         (msgdma_0_csr_agent_rf_source_ready),              //       rf_source.ready
		.rf_source_valid         (msgdma_0_csr_agent_rf_source_valid),              //                .valid
		.rf_source_startofpacket (msgdma_0_csr_agent_rf_source_startofpacket),      //                .startofpacket
		.rf_source_endofpacket   (msgdma_0_csr_agent_rf_source_endofpacket),        //                .endofpacket
		.rf_source_data          (msgdma_0_csr_agent_rf_source_data),               //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_002_out_0_ready),               // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_002_out_0_valid),               //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_002_out_0_data),                //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_002_out_0_error),               //                .error
		.rdata_fifo_src_ready    (msgdma_0_csr_agent_rdata_fifo_src_ready),         //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (msgdma_0_csr_agent_rdata_fifo_src_valid),         //                .valid
		.rdata_fifo_src_data     (msgdma_0_csr_agent_rdata_fifo_src_data),          //                .data
		.m0_response             (2'b00),                                           //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                             //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (92),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) msgdma_0_csr_agent_rsp_fifo (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),       //       clk.clk
		.reset             (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (msgdma_0_csr_agent_rf_source_data),               //        in.data
		.in_valid          (msgdma_0_csr_agent_rf_source_valid),              //          .valid
		.in_ready          (msgdma_0_csr_agent_rf_source_ready),              //          .ready
		.in_startofpacket  (msgdma_0_csr_agent_rf_source_startofpacket),      //          .startofpacket
		.in_endofpacket    (msgdma_0_csr_agent_rf_source_endofpacket),        //          .endofpacket
		.out_data          (msgdma_0_csr_agent_rsp_fifo_out_data),            //       out.data
		.out_valid         (msgdma_0_csr_agent_rsp_fifo_out_valid),           //          .valid
		.out_ready         (msgdma_0_csr_agent_rsp_fifo_out_ready),           //          .ready
		.out_startofpacket (msgdma_0_csr_agent_rsp_fifo_out_startofpacket),   //          .startofpacket
		.out_endofpacket   (msgdma_0_csr_agent_rsp_fifo_out_endofpacket),     //          .endofpacket
		.csr_address       (2'b00),                                           // (terminated)
		.csr_read          (1'b0),                                            // (terminated)
		.csr_write         (1'b0),                                            // (terminated)
		.csr_readdata      (),                                                // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),            // (terminated)
		.almost_full_data  (),                                                // (terminated)
		.almost_empty_data (),                                                // (terminated)
		.in_empty          (1'b0),                                            // (terminated)
		.out_empty         (),                                                // (terminated)
		.in_error          (1'b0),                                            // (terminated)
		.out_error         (),                                                // (terminated)
		.in_channel        (1'b0),                                            // (terminated)
		.out_channel       ()                                                 // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (90),
		.PKT_ORI_BURST_SIZE_L      (88),
		.PKT_RESPONSE_STATUS_H     (87),
		.PKT_RESPONSE_STATUS_L     (86),
		.PKT_BURST_SIZE_H          (65),
		.PKT_BURST_SIZE_L          (63),
		.PKT_TRANS_LOCK            (55),
		.PKT_BEGIN_BURST           (70),
		.PKT_PROTECTION_H          (81),
		.PKT_PROTECTION_L          (79),
		.PKT_BURSTWRAP_H           (62),
		.PKT_BURSTWRAP_L           (62),
		.PKT_BYTE_CNT_H            (61),
		.PKT_BYTE_CNT_L            (57),
		.PKT_ADDR_H                (50),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (51),
		.PKT_TRANS_POSTED          (52),
		.PKT_TRANS_WRITE           (53),
		.PKT_TRANS_READ            (54),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (74),
		.PKT_SRC_ID_L              (72),
		.PKT_DEST_ID_H             (77),
		.PKT_DEST_ID_L             (75),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (91),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) msi_to_gic_gen_0_csr_agent (
		.clk                     (clk_clk_clk),                                             //             clk.clk
		.reset                   (performance_counter_0_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (msi_to_gic_gen_0_csr_agent_m0_address),                   //              m0.address
		.m0_burstcount           (msi_to_gic_gen_0_csr_agent_m0_burstcount),                //                .burstcount
		.m0_byteenable           (msi_to_gic_gen_0_csr_agent_m0_byteenable),                //                .byteenable
		.m0_debugaccess          (msi_to_gic_gen_0_csr_agent_m0_debugaccess),               //                .debugaccess
		.m0_lock                 (msi_to_gic_gen_0_csr_agent_m0_lock),                      //                .lock
		.m0_readdata             (msi_to_gic_gen_0_csr_agent_m0_readdata),                  //                .readdata
		.m0_readdatavalid        (msi_to_gic_gen_0_csr_agent_m0_readdatavalid),             //                .readdatavalid
		.m0_read                 (msi_to_gic_gen_0_csr_agent_m0_read),                      //                .read
		.m0_waitrequest          (msi_to_gic_gen_0_csr_agent_m0_waitrequest),               //                .waitrequest
		.m0_writedata            (msi_to_gic_gen_0_csr_agent_m0_writedata),                 //                .writedata
		.m0_write                (msi_to_gic_gen_0_csr_agent_m0_write),                     //                .write
		.rp_endofpacket          (msi_to_gic_gen_0_csr_agent_rp_endofpacket),               //              rp.endofpacket
		.rp_ready                (msi_to_gic_gen_0_csr_agent_rp_ready),                     //                .ready
		.rp_valid                (msi_to_gic_gen_0_csr_agent_rp_valid),                     //                .valid
		.rp_data                 (msi_to_gic_gen_0_csr_agent_rp_data),                      //                .data
		.rp_startofpacket        (msi_to_gic_gen_0_csr_agent_rp_startofpacket),             //                .startofpacket
		.cp_ready                (agent_pipeline_006_source0_ready),                        //              cp.ready
		.cp_valid                (agent_pipeline_006_source0_valid),                        //                .valid
		.cp_data                 (agent_pipeline_006_source0_data),                         //                .data
		.cp_startofpacket        (agent_pipeline_006_source0_startofpacket),                //                .startofpacket
		.cp_endofpacket          (agent_pipeline_006_source0_endofpacket),                  //                .endofpacket
		.cp_channel              (agent_pipeline_006_source0_channel),                      //                .channel
		.rf_sink_ready           (msi_to_gic_gen_0_csr_agent_rsp_fifo_out_ready),           //         rf_sink.ready
		.rf_sink_valid           (msi_to_gic_gen_0_csr_agent_rsp_fifo_out_valid),           //                .valid
		.rf_sink_startofpacket   (msi_to_gic_gen_0_csr_agent_rsp_fifo_out_startofpacket),   //                .startofpacket
		.rf_sink_endofpacket     (msi_to_gic_gen_0_csr_agent_rsp_fifo_out_endofpacket),     //                .endofpacket
		.rf_sink_data            (msi_to_gic_gen_0_csr_agent_rsp_fifo_out_data),            //                .data
		.rf_source_ready         (msi_to_gic_gen_0_csr_agent_rf_source_ready),              //       rf_source.ready
		.rf_source_valid         (msi_to_gic_gen_0_csr_agent_rf_source_valid),              //                .valid
		.rf_source_startofpacket (msi_to_gic_gen_0_csr_agent_rf_source_startofpacket),      //                .startofpacket
		.rf_source_endofpacket   (msi_to_gic_gen_0_csr_agent_rf_source_endofpacket),        //                .endofpacket
		.rf_source_data          (msi_to_gic_gen_0_csr_agent_rf_source_data),               //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_003_out_0_ready),                       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_003_out_0_valid),                       //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_003_out_0_data),                        //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_003_out_0_error),                       //                .error
		.rdata_fifo_src_ready    (msi_to_gic_gen_0_csr_agent_rdata_fifo_src_ready),         //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (msi_to_gic_gen_0_csr_agent_rdata_fifo_src_valid),         //                .valid
		.rdata_fifo_src_data     (msi_to_gic_gen_0_csr_agent_rdata_fifo_src_data),          //                .data
		.m0_response             (2'b00),                                                   //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                     //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (92),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) msi_to_gic_gen_0_csr_agent_rsp_fifo (
		.clk               (clk_clk_clk),                                             //       clk.clk
		.reset             (performance_counter_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (msi_to_gic_gen_0_csr_agent_rf_source_data),               //        in.data
		.in_valid          (msi_to_gic_gen_0_csr_agent_rf_source_valid),              //          .valid
		.in_ready          (msi_to_gic_gen_0_csr_agent_rf_source_ready),              //          .ready
		.in_startofpacket  (msi_to_gic_gen_0_csr_agent_rf_source_startofpacket),      //          .startofpacket
		.in_endofpacket    (msi_to_gic_gen_0_csr_agent_rf_source_endofpacket),        //          .endofpacket
		.out_data          (msi_to_gic_gen_0_csr_agent_rsp_fifo_out_data),            //       out.data
		.out_valid         (msi_to_gic_gen_0_csr_agent_rsp_fifo_out_valid),           //          .valid
		.out_ready         (msi_to_gic_gen_0_csr_agent_rsp_fifo_out_ready),           //          .ready
		.out_startofpacket (msi_to_gic_gen_0_csr_agent_rsp_fifo_out_startofpacket),   //          .startofpacket
		.out_endofpacket   (msi_to_gic_gen_0_csr_agent_rsp_fifo_out_endofpacket),     //          .endofpacket
		.csr_address       (2'b00),                                                   // (terminated)
		.csr_read          (1'b0),                                                    // (terminated)
		.csr_write         (1'b0),                                                    // (terminated)
		.csr_readdata      (),                                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                    // (terminated)
		.almost_full_data  (),                                                        // (terminated)
		.almost_empty_data (),                                                        // (terminated)
		.in_empty          (1'b0),                                                    // (terminated)
		.out_empty         (),                                                        // (terminated)
		.in_error          (1'b0),                                                    // (terminated)
		.out_error         (),                                                        // (terminated)
		.in_channel        (1'b0),                                                    // (terminated)
		.out_channel       ()                                                         // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) msi_to_gic_gen_0_csr_agent_rdata_fifo (
		.clk               (clk_clk_clk),                                             //       clk.clk
		.reset             (performance_counter_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (msi_to_gic_gen_0_csr_agent_rdata_fifo_src_data),          //        in.data
		.in_valid          (msi_to_gic_gen_0_csr_agent_rdata_fifo_src_valid),         //          .valid
		.in_ready          (msi_to_gic_gen_0_csr_agent_rdata_fifo_src_ready),         //          .ready
		.out_data          (msi_to_gic_gen_0_csr_agent_rdata_fifo_out_data),          //       out.data
		.out_valid         (msi_to_gic_gen_0_csr_agent_rdata_fifo_out_valid),         //          .valid
		.out_ready         (msi_to_gic_gen_0_csr_agent_rdata_fifo_out_ready),         //          .ready
		.csr_address       (2'b00),                                                   // (terminated)
		.csr_read          (1'b0),                                                    // (terminated)
		.csr_write         (1'b0),                                                    // (terminated)
		.csr_readdata      (),                                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                    // (terminated)
		.almost_full_data  (),                                                        // (terminated)
		.almost_empty_data (),                                                        // (terminated)
		.in_startofpacket  (1'b0),                                                    // (terminated)
		.in_endofpacket    (1'b0),                                                    // (terminated)
		.out_startofpacket (),                                                        // (terminated)
		.out_endofpacket   (),                                                        // (terminated)
		.in_empty          (1'b0),                                                    // (terminated)
		.out_empty         (),                                                        // (terminated)
		.in_error          (1'b0),                                                    // (terminated)
		.out_error         (),                                                        // (terminated)
		.in_channel        (1'b0),                                                    // (terminated)
		.out_channel       ()                                                         // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (198),
		.PKT_ORI_BURST_SIZE_L      (196),
		.PKT_RESPONSE_STATUS_H     (195),
		.PKT_RESPONSE_STATUS_L     (194),
		.PKT_BURST_SIZE_H          (173),
		.PKT_BURST_SIZE_L          (171),
		.PKT_TRANS_LOCK            (163),
		.PKT_BEGIN_BURST           (178),
		.PKT_PROTECTION_H          (189),
		.PKT_PROTECTION_L          (187),
		.PKT_BURSTWRAP_H           (170),
		.PKT_BURSTWRAP_L           (170),
		.PKT_BYTE_CNT_H            (169),
		.PKT_BYTE_CNT_L            (165),
		.PKT_ADDR_H                (158),
		.PKT_ADDR_L                (144),
		.PKT_TRANS_COMPRESSED_READ (159),
		.PKT_TRANS_POSTED          (160),
		.PKT_TRANS_WRITE           (161),
		.PKT_TRANS_READ            (162),
		.PKT_DATA_H                (127),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (143),
		.PKT_BYTEEN_L              (128),
		.PKT_SRC_ID_H              (182),
		.PKT_SRC_ID_L              (180),
		.PKT_DEST_ID_H             (185),
		.PKT_DEST_ID_L             (183),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (199),
		.AVS_BURSTCOUNT_W          (5),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) msgdma_0_descriptor_slave_agent (
		.clk                     (custom_reset_synchronizer_0_clock_out_clk),                  //             clk.clk
		.reset                   (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),            //       clk_reset.reset
		.m0_address              (msgdma_0_descriptor_slave_agent_m0_address),                 //              m0.address
		.m0_burstcount           (msgdma_0_descriptor_slave_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (msgdma_0_descriptor_slave_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (msgdma_0_descriptor_slave_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (msgdma_0_descriptor_slave_agent_m0_lock),                    //                .lock
		.m0_readdata             (msgdma_0_descriptor_slave_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (msgdma_0_descriptor_slave_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (msgdma_0_descriptor_slave_agent_m0_read),                    //                .read
		.m0_waitrequest          (msgdma_0_descriptor_slave_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (msgdma_0_descriptor_slave_agent_m0_writedata),               //                .writedata
		.m0_write                (msgdma_0_descriptor_slave_agent_m0_write),                   //                .write
		.rp_endofpacket          (msgdma_0_descriptor_slave_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (msgdma_0_descriptor_slave_agent_rp_ready),                   //                .ready
		.rp_valid                (msgdma_0_descriptor_slave_agent_rp_valid),                   //                .valid
		.rp_data                 (msgdma_0_descriptor_slave_agent_rp_data),                    //                .data
		.rp_startofpacket        (msgdma_0_descriptor_slave_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (agent_pipeline_008_source0_ready),                           //              cp.ready
		.cp_valid                (agent_pipeline_008_source0_valid),                           //                .valid
		.cp_data                 (agent_pipeline_008_source0_data),                            //                .data
		.cp_startofpacket        (agent_pipeline_008_source0_startofpacket),                   //                .startofpacket
		.cp_endofpacket          (agent_pipeline_008_source0_endofpacket),                     //                .endofpacket
		.cp_channel              (agent_pipeline_008_source0_channel),                         //                .channel
		.rf_sink_ready           (msgdma_0_descriptor_slave_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (msgdma_0_descriptor_slave_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (msgdma_0_descriptor_slave_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (msgdma_0_descriptor_slave_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (msgdma_0_descriptor_slave_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (msgdma_0_descriptor_slave_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (msgdma_0_descriptor_slave_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (msgdma_0_descriptor_slave_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (msgdma_0_descriptor_slave_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (msgdma_0_descriptor_slave_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_004_out_0_ready),                          // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_004_out_0_valid),                          //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_004_out_0_data),                           //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_004_out_0_error),                          //                .error
		.rdata_fifo_src_ready    (msgdma_0_descriptor_slave_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (msgdma_0_descriptor_slave_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (msgdma_0_descriptor_slave_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                      //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                        //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (200),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) msgdma_0_descriptor_slave_agent_rsp_fifo (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),                  //       clk.clk
		.reset             (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),            // clk_reset.reset
		.in_data           (msgdma_0_descriptor_slave_agent_rf_source_data),             //        in.data
		.in_valid          (msgdma_0_descriptor_slave_agent_rf_source_valid),            //          .valid
		.in_ready          (msgdma_0_descriptor_slave_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (msgdma_0_descriptor_slave_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (msgdma_0_descriptor_slave_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (msgdma_0_descriptor_slave_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (msgdma_0_descriptor_slave_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (msgdma_0_descriptor_slave_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (msgdma_0_descriptor_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (msgdma_0_descriptor_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                      // (terminated)
		.csr_read          (1'b0),                                                       // (terminated)
		.csr_write         (1'b0),                                                       // (terminated)
		.csr_readdata      (),                                                           // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                       // (terminated)
		.almost_full_data  (),                                                           // (terminated)
		.almost_empty_data (),                                                           // (terminated)
		.in_empty          (1'b0),                                                       // (terminated)
		.out_empty         (),                                                           // (terminated)
		.in_error          (1'b0),                                                       // (terminated)
		.out_error         (),                                                           // (terminated)
		.in_channel        (1'b0),                                                       // (terminated)
		.out_channel       ()                                                            // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (90),
		.PKT_ORI_BURST_SIZE_L      (88),
		.PKT_RESPONSE_STATUS_H     (87),
		.PKT_RESPONSE_STATUS_L     (86),
		.PKT_BURST_SIZE_H          (65),
		.PKT_BURST_SIZE_L          (63),
		.PKT_TRANS_LOCK            (55),
		.PKT_BEGIN_BURST           (70),
		.PKT_PROTECTION_H          (81),
		.PKT_PROTECTION_L          (79),
		.PKT_BURSTWRAP_H           (62),
		.PKT_BURSTWRAP_L           (62),
		.PKT_BYTE_CNT_H            (61),
		.PKT_BYTE_CNT_L            (57),
		.PKT_ADDR_H                (50),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (51),
		.PKT_TRANS_POSTED          (52),
		.PKT_TRANS_WRITE           (53),
		.PKT_TRANS_READ            (54),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (74),
		.PKT_SRC_ID_L              (72),
		.PKT_DEST_ID_H             (77),
		.PKT_DEST_ID_L             (75),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (91),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) msi_to_gic_gen_0_vector_slave_agent (
		.clk                     (clk_clk_clk),                                                    //             clk.clk
		.reset                   (performance_counter_0_reset_reset_bridge_in_reset_reset),        //       clk_reset.reset
		.m0_address              (msi_to_gic_gen_0_vector_slave_agent_m0_address),                 //              m0.address
		.m0_burstcount           (msi_to_gic_gen_0_vector_slave_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (msi_to_gic_gen_0_vector_slave_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (msi_to_gic_gen_0_vector_slave_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (msi_to_gic_gen_0_vector_slave_agent_m0_lock),                    //                .lock
		.m0_readdata             (msi_to_gic_gen_0_vector_slave_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (msi_to_gic_gen_0_vector_slave_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (msi_to_gic_gen_0_vector_slave_agent_m0_read),                    //                .read
		.m0_waitrequest          (msi_to_gic_gen_0_vector_slave_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (msi_to_gic_gen_0_vector_slave_agent_m0_writedata),               //                .writedata
		.m0_write                (msi_to_gic_gen_0_vector_slave_agent_m0_write),                   //                .write
		.rp_endofpacket          (msi_to_gic_gen_0_vector_slave_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (msi_to_gic_gen_0_vector_slave_agent_rp_ready),                   //                .ready
		.rp_valid                (msi_to_gic_gen_0_vector_slave_agent_rp_valid),                   //                .valid
		.rp_data                 (msi_to_gic_gen_0_vector_slave_agent_rp_data),                    //                .data
		.rp_startofpacket        (msi_to_gic_gen_0_vector_slave_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (agent_pipeline_010_source0_ready),                               //              cp.ready
		.cp_valid                (agent_pipeline_010_source0_valid),                               //                .valid
		.cp_data                 (agent_pipeline_010_source0_data),                                //                .data
		.cp_startofpacket        (agent_pipeline_010_source0_startofpacket),                       //                .startofpacket
		.cp_endofpacket          (agent_pipeline_010_source0_endofpacket),                         //                .endofpacket
		.cp_channel              (agent_pipeline_010_source0_channel),                             //                .channel
		.rf_sink_ready           (msi_to_gic_gen_0_vector_slave_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (msi_to_gic_gen_0_vector_slave_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (msi_to_gic_gen_0_vector_slave_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (msi_to_gic_gen_0_vector_slave_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (msi_to_gic_gen_0_vector_slave_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (msi_to_gic_gen_0_vector_slave_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (msi_to_gic_gen_0_vector_slave_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (msi_to_gic_gen_0_vector_slave_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (msi_to_gic_gen_0_vector_slave_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (msi_to_gic_gen_0_vector_slave_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_005_out_0_ready),                              // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_005_out_0_valid),                              //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_005_out_0_data),                               //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_005_out_0_error),                              //                .error
		.rdata_fifo_src_ready    (msi_to_gic_gen_0_vector_slave_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (msi_to_gic_gen_0_vector_slave_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (msi_to_gic_gen_0_vector_slave_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                          //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (92),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) msi_to_gic_gen_0_vector_slave_agent_rsp_fifo (
		.clk               (clk_clk_clk),                                                    //       clk.clk
		.reset             (performance_counter_0_reset_reset_bridge_in_reset_reset),        // clk_reset.reset
		.in_data           (msi_to_gic_gen_0_vector_slave_agent_rf_source_data),             //        in.data
		.in_valid          (msi_to_gic_gen_0_vector_slave_agent_rf_source_valid),            //          .valid
		.in_ready          (msi_to_gic_gen_0_vector_slave_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (msi_to_gic_gen_0_vector_slave_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (msi_to_gic_gen_0_vector_slave_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (msi_to_gic_gen_0_vector_slave_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (msi_to_gic_gen_0_vector_slave_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (msi_to_gic_gen_0_vector_slave_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (msi_to_gic_gen_0_vector_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (msi_to_gic_gen_0_vector_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                          // (terminated)
		.csr_read          (1'b0),                                                           // (terminated)
		.csr_write         (1'b0),                                                           // (terminated)
		.csr_readdata      (),                                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                           // (terminated)
		.almost_full_data  (),                                                               // (terminated)
		.almost_empty_data (),                                                               // (terminated)
		.in_empty          (1'b0),                                                           // (terminated)
		.out_empty         (),                                                               // (terminated)
		.in_error          (1'b0),                                                           // (terminated)
		.out_error         (),                                                               // (terminated)
		.in_channel        (1'b0),                                                           // (terminated)
		.out_channel       ()                                                                // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) msi_to_gic_gen_0_vector_slave_agent_rdata_fifo (
		.clk               (clk_clk_clk),                                              //       clk.clk
		.reset             (performance_counter_0_reset_reset_bridge_in_reset_reset),  // clk_reset.reset
		.in_data           (msi_to_gic_gen_0_vector_slave_agent_rdata_fifo_src_data),  //        in.data
		.in_valid          (msi_to_gic_gen_0_vector_slave_agent_rdata_fifo_src_valid), //          .valid
		.in_ready          (msi_to_gic_gen_0_vector_slave_agent_rdata_fifo_src_ready), //          .ready
		.out_data          (msi_to_gic_gen_0_vector_slave_agent_rdata_fifo_out_data),  //       out.data
		.out_valid         (msi_to_gic_gen_0_vector_slave_agent_rdata_fifo_out_valid), //          .valid
		.out_ready         (msi_to_gic_gen_0_vector_slave_agent_rdata_fifo_out_ready), //          .ready
		.csr_address       (2'b00),                                                    // (terminated)
		.csr_read          (1'b0),                                                     // (terminated)
		.csr_write         (1'b0),                                                     // (terminated)
		.csr_readdata      (),                                                         // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                     // (terminated)
		.almost_full_data  (),                                                         // (terminated)
		.almost_empty_data (),                                                         // (terminated)
		.in_startofpacket  (1'b0),                                                     // (terminated)
		.in_endofpacket    (1'b0),                                                     // (terminated)
		.out_startofpacket (),                                                         // (terminated)
		.out_endofpacket   (),                                                         // (terminated)
		.in_empty          (1'b0),                                                     // (terminated)
		.out_empty         (),                                                         // (terminated)
		.in_error          (1'b0),                                                     // (terminated)
		.out_error         (),                                                         // (terminated)
		.in_channel        (1'b0),                                                     // (terminated)
		.out_channel       ()                                                          // (terminated)
	);

	soc_system_pcie_0_mm_interconnect_1_router router (
		.sink_ready         (pb_lwh2f_pcie_m0_agent_cp_ready),                 //      sink.ready
		.sink_valid         (pb_lwh2f_pcie_m0_agent_cp_valid),                 //          .valid
		.sink_data          (pb_lwh2f_pcie_m0_agent_cp_data),                  //          .data
		.sink_startofpacket (pb_lwh2f_pcie_m0_agent_cp_startofpacket),         //          .startofpacket
		.sink_endofpacket   (pb_lwh2f_pcie_m0_agent_cp_endofpacket),           //          .endofpacket
		.clk                (custom_reset_synchronizer_0_clock_out_clk),       //       clk.clk
		.reset              (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_src_ready),                                //       src.ready
		.src_valid          (router_src_valid),                                //          .valid
		.src_data           (router_src_data),                                 //          .data
		.src_channel        (router_src_channel),                              //          .channel
		.src_startofpacket  (router_src_startofpacket),                        //          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                           //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_router_001 router_001 (
		.sink_ready         (pb_rxm_2_msi_m0_agent_cp_ready),                  //      sink.ready
		.sink_valid         (pb_rxm_2_msi_m0_agent_cp_valid),                  //          .valid
		.sink_data          (pb_rxm_2_msi_m0_agent_cp_data),                   //          .data
		.sink_startofpacket (pb_rxm_2_msi_m0_agent_cp_startofpacket),          //          .startofpacket
		.sink_endofpacket   (pb_rxm_2_msi_m0_agent_cp_endofpacket),            //          .endofpacket
		.clk                (custom_reset_synchronizer_0_clock_out_clk),       //       clk.clk
		.reset              (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_001_src_ready),                            //       src.ready
		.src_valid          (router_001_src_valid),                            //          .valid
		.src_data           (router_001_src_data),                             //          .data
		.src_channel        (router_001_src_channel),                          //          .channel
		.src_startofpacket  (router_001_src_startofpacket),                    //          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                       //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_router_002 router_002 (
		.sink_ready         (agent_pipeline_001_source0_ready),                               //      sink.ready
		.sink_valid         (agent_pipeline_001_source0_valid),                               //          .valid
		.sink_data          (agent_pipeline_001_source0_data),                                //          .data
		.sink_startofpacket (agent_pipeline_001_source0_startofpacket),                       //          .startofpacket
		.sink_endofpacket   (agent_pipeline_001_source0_endofpacket),                         //          .endofpacket
		.clk                (pcie_hip_avmm_coreclkout_clk),                                   //       clk.clk
		.reset              (pcie_hip_avmm_Cra_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_002_src_ready),                                           //       src.ready
		.src_valid          (router_002_src_valid),                                           //          .valid
		.src_data           (router_002_src_data),                                            //          .data
		.src_channel        (router_002_src_channel),                                         //          .channel
		.src_startofpacket  (router_002_src_startofpacket),                                   //          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                                      //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_router_002 router_003 (
		.sink_ready         (agent_pipeline_003_source0_ready),                        //      sink.ready
		.sink_valid         (agent_pipeline_003_source0_valid),                        //          .valid
		.sink_data          (agent_pipeline_003_source0_data),                         //          .data
		.sink_startofpacket (agent_pipeline_003_source0_startofpacket),                //          .startofpacket
		.sink_endofpacket   (agent_pipeline_003_source0_endofpacket),                  //          .endofpacket
		.clk                (clk_clk_clk),                                             //       clk.clk
		.reset              (performance_counter_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_003_src_ready),                                    //       src.ready
		.src_valid          (router_003_src_valid),                                    //          .valid
		.src_data           (router_003_src_data),                                     //          .data
		.src_channel        (router_003_src_channel),                                  //          .channel
		.src_startofpacket  (router_003_src_startofpacket),                            //          .startofpacket
		.src_endofpacket    (router_003_src_endofpacket)                               //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_router_002 router_004 (
		.sink_ready         (agent_pipeline_005_source0_ready),                //      sink.ready
		.sink_valid         (agent_pipeline_005_source0_valid),                //          .valid
		.sink_data          (agent_pipeline_005_source0_data),                 //          .data
		.sink_startofpacket (agent_pipeline_005_source0_startofpacket),        //          .startofpacket
		.sink_endofpacket   (agent_pipeline_005_source0_endofpacket),          //          .endofpacket
		.clk                (custom_reset_synchronizer_0_clock_out_clk),       //       clk.clk
		.reset              (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_004_src_ready),                            //       src.ready
		.src_valid          (router_004_src_valid),                            //          .valid
		.src_data           (router_004_src_data),                             //          .data
		.src_channel        (router_004_src_channel),                          //          .channel
		.src_startofpacket  (router_004_src_startofpacket),                    //          .startofpacket
		.src_endofpacket    (router_004_src_endofpacket)                       //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_router_002 router_005 (
		.sink_ready         (agent_pipeline_007_source0_ready),                        //      sink.ready
		.sink_valid         (agent_pipeline_007_source0_valid),                        //          .valid
		.sink_data          (agent_pipeline_007_source0_data),                         //          .data
		.sink_startofpacket (agent_pipeline_007_source0_startofpacket),                //          .startofpacket
		.sink_endofpacket   (agent_pipeline_007_source0_endofpacket),                  //          .endofpacket
		.clk                (clk_clk_clk),                                             //       clk.clk
		.reset              (performance_counter_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_005_src_ready),                                    //       src.ready
		.src_valid          (router_005_src_valid),                                    //          .valid
		.src_data           (router_005_src_data),                                     //          .data
		.src_channel        (router_005_src_channel),                                  //          .channel
		.src_startofpacket  (router_005_src_startofpacket),                            //          .startofpacket
		.src_endofpacket    (router_005_src_endofpacket)                               //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_router_006 router_006 (
		.sink_ready         (agent_pipeline_009_source0_ready),                //      sink.ready
		.sink_valid         (agent_pipeline_009_source0_valid),                //          .valid
		.sink_data          (agent_pipeline_009_source0_data),                 //          .data
		.sink_startofpacket (agent_pipeline_009_source0_startofpacket),        //          .startofpacket
		.sink_endofpacket   (agent_pipeline_009_source0_endofpacket),          //          .endofpacket
		.clk                (custom_reset_synchronizer_0_clock_out_clk),       //       clk.clk
		.reset              (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_006_src_ready),                            //       src.ready
		.src_valid          (router_006_src_valid),                            //          .valid
		.src_data           (router_006_src_data),                             //          .data
		.src_channel        (router_006_src_channel),                          //          .channel
		.src_startofpacket  (router_006_src_startofpacket),                    //          .startofpacket
		.src_endofpacket    (router_006_src_endofpacket)                       //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_router_007 router_007 (
		.sink_ready         (agent_pipeline_011_source0_ready),                        //      sink.ready
		.sink_valid         (agent_pipeline_011_source0_valid),                        //          .valid
		.sink_data          (agent_pipeline_011_source0_data),                         //          .data
		.sink_startofpacket (agent_pipeline_011_source0_startofpacket),                //          .startofpacket
		.sink_endofpacket   (agent_pipeline_011_source0_endofpacket),                  //          .endofpacket
		.clk                (clk_clk_clk),                                             //       clk.clk
		.reset              (performance_counter_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_007_src_ready),                                    //       src.ready
		.src_valid          (router_007_src_valid),                                    //          .valid
		.src_data           (router_007_src_data),                                     //          .data
		.src_channel        (router_007_src_channel),                                  //          .channel
		.src_startofpacket  (router_007_src_startofpacket),                            //          .startofpacket
		.src_endofpacket    (router_007_src_endofpacket)                               //          .endofpacket
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (77),
		.PKT_DEST_ID_L             (75),
		.PKT_SRC_ID_H              (74),
		.PKT_SRC_ID_L              (72),
		.PKT_BYTE_CNT_H            (61),
		.PKT_BYTE_CNT_L            (57),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_TRANS_POSTED          (52),
		.PKT_TRANS_WRITE           (53),
		.MAX_OUTSTANDING_RESPONSES (13),
		.PIPELINED                 (0),
		.ST_DATA_W                 (91),
		.ST_CHANNEL_W              (6),
		.VALID_WIDTH               (1),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (0),
		.SUPPORTS_POSTED_WRITES    (1),
		.SUPPORTS_NONPOSTED_WRITES (0),
		.REORDER                   (0)
	) pb_lwh2f_pcie_m0_limiter (
		.clk                    (custom_reset_synchronizer_0_clock_out_clk),       //       clk.clk
		.reset                  (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.cmd_sink_ready         (router_src_ready),                                //  cmd_sink.ready
		.cmd_sink_valid         (router_src_valid),                                //          .valid
		.cmd_sink_data          (router_src_data),                                 //          .data
		.cmd_sink_channel       (router_src_channel),                              //          .channel
		.cmd_sink_startofpacket (router_src_startofpacket),                        //          .startofpacket
		.cmd_sink_endofpacket   (router_src_endofpacket),                          //          .endofpacket
		.cmd_src_ready          (pb_lwh2f_pcie_m0_limiter_cmd_src_ready),          //   cmd_src.ready
		.cmd_src_data           (pb_lwh2f_pcie_m0_limiter_cmd_src_data),           //          .data
		.cmd_src_channel        (pb_lwh2f_pcie_m0_limiter_cmd_src_channel),        //          .channel
		.cmd_src_startofpacket  (pb_lwh2f_pcie_m0_limiter_cmd_src_startofpacket),  //          .startofpacket
		.cmd_src_endofpacket    (pb_lwh2f_pcie_m0_limiter_cmd_src_endofpacket),    //          .endofpacket
		.cmd_src_valid          (pb_lwh2f_pcie_m0_limiter_cmd_src_valid),          //          .valid
		.rsp_sink_ready         (limiter_pipeline_001_source0_ready),              //  rsp_sink.ready
		.rsp_sink_valid         (limiter_pipeline_001_source0_valid),              //          .valid
		.rsp_sink_channel       (limiter_pipeline_001_source0_channel),            //          .channel
		.rsp_sink_data          (limiter_pipeline_001_source0_data),               //          .data
		.rsp_sink_startofpacket (limiter_pipeline_001_source0_startofpacket),      //          .startofpacket
		.rsp_sink_endofpacket   (limiter_pipeline_001_source0_endofpacket),        //          .endofpacket
		.rsp_src_ready          (pb_lwh2f_pcie_m0_limiter_rsp_src_ready),          //   rsp_src.ready
		.rsp_src_valid          (pb_lwh2f_pcie_m0_limiter_rsp_src_valid),          //          .valid
		.rsp_src_data           (pb_lwh2f_pcie_m0_limiter_rsp_src_data),           //          .data
		.rsp_src_channel        (pb_lwh2f_pcie_m0_limiter_rsp_src_channel),        //          .channel
		.rsp_src_startofpacket  (pb_lwh2f_pcie_m0_limiter_rsp_src_startofpacket),  //          .startofpacket
		.rsp_src_endofpacket    (pb_lwh2f_pcie_m0_limiter_rsp_src_endofpacket)     //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_cmd_demux cmd_demux (
		.clk                (custom_reset_synchronizer_0_clock_out_clk),       //       clk.clk
		.reset              (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (limiter_pipeline_source0_ready),                  //      sink.ready
		.sink_channel       (limiter_pipeline_source0_channel),                //          .channel
		.sink_data          (limiter_pipeline_source0_data),                   //          .data
		.sink_startofpacket (limiter_pipeline_source0_startofpacket),          //          .startofpacket
		.sink_endofpacket   (limiter_pipeline_source0_endofpacket),            //          .endofpacket
		.sink_valid         (limiter_pipeline_source0_valid),                  //          .valid
		.src0_ready         (cmd_demux_src0_ready),                            //      src0.ready
		.src0_valid         (cmd_demux_src0_valid),                            //          .valid
		.src0_data          (cmd_demux_src0_data),                             //          .data
		.src0_channel       (cmd_demux_src0_channel),                          //          .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                    //          .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket),                      //          .endofpacket
		.src1_ready         (cmd_demux_src1_ready),                            //      src1.ready
		.src1_valid         (cmd_demux_src1_valid),                            //          .valid
		.src1_data          (cmd_demux_src1_data),                             //          .data
		.src1_channel       (cmd_demux_src1_channel),                          //          .channel
		.src1_startofpacket (cmd_demux_src1_startofpacket),                    //          .startofpacket
		.src1_endofpacket   (cmd_demux_src1_endofpacket),                      //          .endofpacket
		.src2_ready         (cmd_demux_src2_ready),                            //      src2.ready
		.src2_valid         (cmd_demux_src2_valid),                            //          .valid
		.src2_data          (cmd_demux_src2_data),                             //          .data
		.src2_channel       (cmd_demux_src2_channel),                          //          .channel
		.src2_startofpacket (cmd_demux_src2_startofpacket),                    //          .startofpacket
		.src2_endofpacket   (cmd_demux_src2_endofpacket),                      //          .endofpacket
		.src3_ready         (cmd_demux_src3_ready),                            //      src3.ready
		.src3_valid         (cmd_demux_src3_valid),                            //          .valid
		.src3_data          (cmd_demux_src3_data),                             //          .data
		.src3_channel       (cmd_demux_src3_channel),                          //          .channel
		.src3_startofpacket (cmd_demux_src3_startofpacket),                    //          .startofpacket
		.src3_endofpacket   (cmd_demux_src3_endofpacket),                      //          .endofpacket
		.src4_ready         (cmd_demux_src4_ready),                            //      src4.ready
		.src4_valid         (cmd_demux_src4_valid),                            //          .valid
		.src4_data          (cmd_demux_src4_data),                             //          .data
		.src4_channel       (cmd_demux_src4_channel),                          //          .channel
		.src4_startofpacket (cmd_demux_src4_startofpacket),                    //          .startofpacket
		.src4_endofpacket   (cmd_demux_src4_endofpacket),                      //          .endofpacket
		.src5_ready         (cmd_demux_src5_ready),                            //      src5.ready
		.src5_valid         (cmd_demux_src5_valid),                            //          .valid
		.src5_data          (cmd_demux_src5_data),                             //          .data
		.src5_channel       (cmd_demux_src5_channel),                          //          .channel
		.src5_startofpacket (cmd_demux_src5_startofpacket),                    //          .startofpacket
		.src5_endofpacket   (cmd_demux_src5_endofpacket)                       //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_cmd_demux_001 cmd_demux_001 (
		.clk                (custom_reset_synchronizer_0_clock_out_clk),       //       clk.clk
		.reset              (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_001_src_ready),                            //      sink.ready
		.sink_channel       (router_001_src_channel),                          //          .channel
		.sink_data          (router_001_src_data),                             //          .data
		.sink_startofpacket (router_001_src_startofpacket),                    //          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),                      //          .endofpacket
		.sink_valid         (router_001_src_valid),                            //          .valid
		.src0_ready         (cmd_demux_001_src0_ready),                        //      src0.ready
		.src0_valid         (cmd_demux_001_src0_valid),                        //          .valid
		.src0_data          (cmd_demux_001_src0_data),                         //          .data
		.src0_channel       (cmd_demux_001_src0_channel),                      //          .channel
		.src0_startofpacket (cmd_demux_001_src0_startofpacket),                //          .startofpacket
		.src0_endofpacket   (cmd_demux_001_src0_endofpacket)                   //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_cmd_mux cmd_mux (
		.clk                 (pcie_hip_avmm_coreclkout_clk),                                   //       clk.clk
		.reset               (pcie_hip_avmm_Cra_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                                              //       src.ready
		.src_valid           (cmd_mux_src_valid),                                              //          .valid
		.src_data            (cmd_mux_src_data),                                               //          .data
		.src_channel         (cmd_mux_src_channel),                                            //          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                                      //          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                                        //          .endofpacket
		.sink0_ready         (crosser_out_ready),                                              //     sink0.ready
		.sink0_valid         (crosser_out_valid),                                              //          .valid
		.sink0_channel       (crosser_out_channel),                                            //          .channel
		.sink0_data          (crosser_out_data),                                               //          .data
		.sink0_startofpacket (crosser_out_startofpacket),                                      //          .startofpacket
		.sink0_endofpacket   (crosser_out_endofpacket)                                         //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_cmd_mux cmd_mux_001 (
		.clk                 (clk_clk_clk),                                             //       clk.clk
		.reset               (performance_counter_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_001_src_ready),                                   //       src.ready
		.src_valid           (cmd_mux_001_src_valid),                                   //          .valid
		.src_data            (cmd_mux_001_src_data),                                    //          .data
		.src_channel         (cmd_mux_001_src_channel),                                 //          .channel
		.src_startofpacket   (cmd_mux_001_src_startofpacket),                           //          .startofpacket
		.src_endofpacket     (cmd_mux_001_src_endofpacket),                             //          .endofpacket
		.sink0_ready         (crosser_001_out_ready),                                   //     sink0.ready
		.sink0_valid         (crosser_001_out_valid),                                   //          .valid
		.sink0_channel       (crosser_001_out_channel),                                 //          .channel
		.sink0_data          (crosser_001_out_data),                                    //          .data
		.sink0_startofpacket (crosser_001_out_startofpacket),                           //          .startofpacket
		.sink0_endofpacket   (crosser_001_out_endofpacket)                              //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_cmd_mux cmd_mux_002 (
		.clk                 (custom_reset_synchronizer_0_clock_out_clk),       //       clk.clk
		.reset               (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_002_src_ready),                           //       src.ready
		.src_valid           (cmd_mux_002_src_valid),                           //          .valid
		.src_data            (cmd_mux_002_src_data),                            //          .data
		.src_channel         (cmd_mux_002_src_channel),                         //          .channel
		.src_startofpacket   (cmd_mux_002_src_startofpacket),                   //          .startofpacket
		.src_endofpacket     (cmd_mux_002_src_endofpacket),                     //          .endofpacket
		.sink0_ready         (cmd_demux_src2_ready),                            //     sink0.ready
		.sink0_valid         (cmd_demux_src2_valid),                            //          .valid
		.sink0_channel       (cmd_demux_src2_channel),                          //          .channel
		.sink0_data          (cmd_demux_src2_data),                             //          .data
		.sink0_startofpacket (cmd_demux_src2_startofpacket),                    //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src2_endofpacket)                       //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_cmd_mux cmd_mux_003 (
		.clk                 (clk_clk_clk),                                             //       clk.clk
		.reset               (performance_counter_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_003_src_ready),                                   //       src.ready
		.src_valid           (cmd_mux_003_src_valid),                                   //          .valid
		.src_data            (cmd_mux_003_src_data),                                    //          .data
		.src_channel         (cmd_mux_003_src_channel),                                 //          .channel
		.src_startofpacket   (cmd_mux_003_src_startofpacket),                           //          .startofpacket
		.src_endofpacket     (cmd_mux_003_src_endofpacket),                             //          .endofpacket
		.sink0_ready         (crosser_002_out_ready),                                   //     sink0.ready
		.sink0_valid         (crosser_002_out_valid),                                   //          .valid
		.sink0_channel       (crosser_002_out_channel),                                 //          .channel
		.sink0_data          (crosser_002_out_data),                                    //          .data
		.sink0_startofpacket (crosser_002_out_startofpacket),                           //          .startofpacket
		.sink0_endofpacket   (crosser_002_out_endofpacket)                              //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_cmd_mux cmd_mux_004 (
		.clk                 (custom_reset_synchronizer_0_clock_out_clk),       //       clk.clk
		.reset               (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_004_src_ready),                           //       src.ready
		.src_valid           (cmd_mux_004_src_valid),                           //          .valid
		.src_data            (cmd_mux_004_src_data),                            //          .data
		.src_channel         (cmd_mux_004_src_channel),                         //          .channel
		.src_startofpacket   (cmd_mux_004_src_startofpacket),                   //          .startofpacket
		.src_endofpacket     (cmd_mux_004_src_endofpacket),                     //          .endofpacket
		.sink0_ready         (cmd_demux_src4_ready),                            //     sink0.ready
		.sink0_valid         (cmd_demux_src4_valid),                            //          .valid
		.sink0_channel       (cmd_demux_src4_channel),                          //          .channel
		.sink0_data          (cmd_demux_src4_data),                             //          .data
		.sink0_startofpacket (cmd_demux_src4_startofpacket),                    //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src4_endofpacket)                       //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_cmd_mux_005 cmd_mux_005 (
		.clk                 (clk_clk_clk),                                             //       clk.clk
		.reset               (performance_counter_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_005_src_ready),                                   //       src.ready
		.src_valid           (cmd_mux_005_src_valid),                                   //          .valid
		.src_data            (cmd_mux_005_src_data),                                    //          .data
		.src_channel         (cmd_mux_005_src_channel),                                 //          .channel
		.src_startofpacket   (cmd_mux_005_src_startofpacket),                           //          .startofpacket
		.src_endofpacket     (cmd_mux_005_src_endofpacket),                             //          .endofpacket
		.sink0_ready         (crosser_003_out_ready),                                   //     sink0.ready
		.sink0_valid         (crosser_003_out_valid),                                   //          .valid
		.sink0_channel       (crosser_003_out_channel),                                 //          .channel
		.sink0_data          (crosser_003_out_data),                                    //          .data
		.sink0_startofpacket (crosser_003_out_startofpacket),                           //          .startofpacket
		.sink0_endofpacket   (crosser_003_out_endofpacket),                             //          .endofpacket
		.sink1_ready         (crosser_004_out_ready),                                   //     sink1.ready
		.sink1_valid         (crosser_004_out_valid),                                   //          .valid
		.sink1_channel       (crosser_004_out_channel),                                 //          .channel
		.sink1_data          (crosser_004_out_data),                                    //          .data
		.sink1_startofpacket (crosser_004_out_startofpacket),                           //          .startofpacket
		.sink1_endofpacket   (crosser_004_out_endofpacket)                              //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_rsp_demux rsp_demux (
		.clk                (pcie_hip_avmm_coreclkout_clk),                                   //       clk.clk
		.reset              (pcie_hip_avmm_Cra_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_002_src_ready),                                           //      sink.ready
		.sink_channel       (router_002_src_channel),                                         //          .channel
		.sink_data          (router_002_src_data),                                            //          .data
		.sink_startofpacket (router_002_src_startofpacket),                                   //          .startofpacket
		.sink_endofpacket   (router_002_src_endofpacket),                                     //          .endofpacket
		.sink_valid         (router_002_src_valid),                                           //          .valid
		.src0_ready         (rsp_demux_src0_ready),                                           //      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                                           //          .valid
		.src0_data          (rsp_demux_src0_data),                                            //          .data
		.src0_channel       (rsp_demux_src0_channel),                                         //          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                                   //          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket)                                      //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_rsp_demux_001 rsp_demux_001 (
		.clk                (clk_clk_clk),                                             //       clk.clk
		.reset              (performance_counter_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_003_src_ready),                                    //      sink.ready
		.sink_channel       (router_003_src_channel),                                  //          .channel
		.sink_data          (router_003_src_data),                                     //          .data
		.sink_startofpacket (router_003_src_startofpacket),                            //          .startofpacket
		.sink_endofpacket   (router_003_src_endofpacket),                              //          .endofpacket
		.sink_valid         (router_003_src_valid),                                    //          .valid
		.src0_ready         (rsp_demux_001_src0_ready),                                //      src0.ready
		.src0_valid         (rsp_demux_001_src0_valid),                                //          .valid
		.src0_data          (rsp_demux_001_src0_data),                                 //          .data
		.src0_channel       (rsp_demux_001_src0_channel),                              //          .channel
		.src0_startofpacket (rsp_demux_001_src0_startofpacket),                        //          .startofpacket
		.src0_endofpacket   (rsp_demux_001_src0_endofpacket)                           //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_cmd_demux_001 rsp_demux_002 (
		.clk                (custom_reset_synchronizer_0_clock_out_clk),       //       clk.clk
		.reset              (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_004_src_ready),                            //      sink.ready
		.sink_channel       (router_004_src_channel),                          //          .channel
		.sink_data          (router_004_src_data),                             //          .data
		.sink_startofpacket (router_004_src_startofpacket),                    //          .startofpacket
		.sink_endofpacket   (router_004_src_endofpacket),                      //          .endofpacket
		.sink_valid         (router_004_src_valid),                            //          .valid
		.src0_ready         (rsp_demux_002_src0_ready),                        //      src0.ready
		.src0_valid         (rsp_demux_002_src0_valid),                        //          .valid
		.src0_data          (rsp_demux_002_src0_data),                         //          .data
		.src0_channel       (rsp_demux_002_src0_channel),                      //          .channel
		.src0_startofpacket (rsp_demux_002_src0_startofpacket),                //          .startofpacket
		.src0_endofpacket   (rsp_demux_002_src0_endofpacket)                   //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_rsp_demux_001 rsp_demux_003 (
		.clk                (clk_clk_clk),                                             //       clk.clk
		.reset              (performance_counter_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_005_src_ready),                                    //      sink.ready
		.sink_channel       (router_005_src_channel),                                  //          .channel
		.sink_data          (router_005_src_data),                                     //          .data
		.sink_startofpacket (router_005_src_startofpacket),                            //          .startofpacket
		.sink_endofpacket   (router_005_src_endofpacket),                              //          .endofpacket
		.sink_valid         (router_005_src_valid),                                    //          .valid
		.src0_ready         (rsp_demux_003_src0_ready),                                //      src0.ready
		.src0_valid         (rsp_demux_003_src0_valid),                                //          .valid
		.src0_data          (rsp_demux_003_src0_data),                                 //          .data
		.src0_channel       (rsp_demux_003_src0_channel),                              //          .channel
		.src0_startofpacket (rsp_demux_003_src0_startofpacket),                        //          .startofpacket
		.src0_endofpacket   (rsp_demux_003_src0_endofpacket)                           //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_cmd_demux_001 rsp_demux_004 (
		.clk                (custom_reset_synchronizer_0_clock_out_clk),                     //       clk.clk
		.reset              (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),               // clk_reset.reset
		.sink_ready         (msgdma_0_descriptor_slave_rsp_width_adapter_src_ready),         //      sink.ready
		.sink_channel       (msgdma_0_descriptor_slave_rsp_width_adapter_src_channel),       //          .channel
		.sink_data          (msgdma_0_descriptor_slave_rsp_width_adapter_src_data),          //          .data
		.sink_startofpacket (msgdma_0_descriptor_slave_rsp_width_adapter_src_startofpacket), //          .startofpacket
		.sink_endofpacket   (msgdma_0_descriptor_slave_rsp_width_adapter_src_endofpacket),   //          .endofpacket
		.sink_valid         (msgdma_0_descriptor_slave_rsp_width_adapter_src_valid),         //          .valid
		.src0_ready         (rsp_demux_004_src0_ready),                                      //      src0.ready
		.src0_valid         (rsp_demux_004_src0_valid),                                      //          .valid
		.src0_data          (rsp_demux_004_src0_data),                                       //          .data
		.src0_channel       (rsp_demux_004_src0_channel),                                    //          .channel
		.src0_startofpacket (rsp_demux_004_src0_startofpacket),                              //          .startofpacket
		.src0_endofpacket   (rsp_demux_004_src0_endofpacket)                                 //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_rsp_demux_005 rsp_demux_005 (
		.clk                (clk_clk_clk),                                             //       clk.clk
		.reset              (performance_counter_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_007_src_ready),                                    //      sink.ready
		.sink_channel       (router_007_src_channel),                                  //          .channel
		.sink_data          (router_007_src_data),                                     //          .data
		.sink_startofpacket (router_007_src_startofpacket),                            //          .startofpacket
		.sink_endofpacket   (router_007_src_endofpacket),                              //          .endofpacket
		.sink_valid         (router_007_src_valid),                                    //          .valid
		.src0_ready         (rsp_demux_005_src0_ready),                                //      src0.ready
		.src0_valid         (rsp_demux_005_src0_valid),                                //          .valid
		.src0_data          (rsp_demux_005_src0_data),                                 //          .data
		.src0_channel       (rsp_demux_005_src0_channel),                              //          .channel
		.src0_startofpacket (rsp_demux_005_src0_startofpacket),                        //          .startofpacket
		.src0_endofpacket   (rsp_demux_005_src0_endofpacket),                          //          .endofpacket
		.src1_ready         (rsp_demux_005_src1_ready),                                //      src1.ready
		.src1_valid         (rsp_demux_005_src1_valid),                                //          .valid
		.src1_data          (rsp_demux_005_src1_data),                                 //          .data
		.src1_channel       (rsp_demux_005_src1_channel),                              //          .channel
		.src1_startofpacket (rsp_demux_005_src1_startofpacket),                        //          .startofpacket
		.src1_endofpacket   (rsp_demux_005_src1_endofpacket)                           //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_rsp_mux rsp_mux (
		.clk                 (custom_reset_synchronizer_0_clock_out_clk),       //       clk.clk
		.reset               (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                               //       src.ready
		.src_valid           (rsp_mux_src_valid),                               //          .valid
		.src_data            (rsp_mux_src_data),                                //          .data
		.src_channel         (rsp_mux_src_channel),                             //          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                       //          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                         //          .endofpacket
		.sink0_ready         (crosser_005_out_ready),                           //     sink0.ready
		.sink0_valid         (crosser_005_out_valid),                           //          .valid
		.sink0_channel       (crosser_005_out_channel),                         //          .channel
		.sink0_data          (crosser_005_out_data),                            //          .data
		.sink0_startofpacket (crosser_005_out_startofpacket),                   //          .startofpacket
		.sink0_endofpacket   (crosser_005_out_endofpacket),                     //          .endofpacket
		.sink1_ready         (crosser_006_out_ready),                           //     sink1.ready
		.sink1_valid         (crosser_006_out_valid),                           //          .valid
		.sink1_channel       (crosser_006_out_channel),                         //          .channel
		.sink1_data          (crosser_006_out_data),                            //          .data
		.sink1_startofpacket (crosser_006_out_startofpacket),                   //          .startofpacket
		.sink1_endofpacket   (crosser_006_out_endofpacket),                     //          .endofpacket
		.sink2_ready         (rsp_demux_002_src0_ready),                        //     sink2.ready
		.sink2_valid         (rsp_demux_002_src0_valid),                        //          .valid
		.sink2_channel       (rsp_demux_002_src0_channel),                      //          .channel
		.sink2_data          (rsp_demux_002_src0_data),                         //          .data
		.sink2_startofpacket (rsp_demux_002_src0_startofpacket),                //          .startofpacket
		.sink2_endofpacket   (rsp_demux_002_src0_endofpacket),                  //          .endofpacket
		.sink3_ready         (crosser_007_out_ready),                           //     sink3.ready
		.sink3_valid         (crosser_007_out_valid),                           //          .valid
		.sink3_channel       (crosser_007_out_channel),                         //          .channel
		.sink3_data          (crosser_007_out_data),                            //          .data
		.sink3_startofpacket (crosser_007_out_startofpacket),                   //          .startofpacket
		.sink3_endofpacket   (crosser_007_out_endofpacket),                     //          .endofpacket
		.sink4_ready         (rsp_demux_004_src0_ready),                        //     sink4.ready
		.sink4_valid         (rsp_demux_004_src0_valid),                        //          .valid
		.sink4_channel       (rsp_demux_004_src0_channel),                      //          .channel
		.sink4_data          (rsp_demux_004_src0_data),                         //          .data
		.sink4_startofpacket (rsp_demux_004_src0_startofpacket),                //          .startofpacket
		.sink4_endofpacket   (rsp_demux_004_src0_endofpacket),                  //          .endofpacket
		.sink5_ready         (crosser_008_out_ready),                           //     sink5.ready
		.sink5_valid         (crosser_008_out_valid),                           //          .valid
		.sink5_channel       (crosser_008_out_channel),                         //          .channel
		.sink5_data          (crosser_008_out_data),                            //          .data
		.sink5_startofpacket (crosser_008_out_startofpacket),                   //          .startofpacket
		.sink5_endofpacket   (crosser_008_out_endofpacket)                      //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_1_rsp_mux_001 rsp_mux_001 (
		.clk                 (custom_reset_synchronizer_0_clock_out_clk),       //       clk.clk
		.reset               (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_001_src_ready),                           //       src.ready
		.src_valid           (rsp_mux_001_src_valid),                           //          .valid
		.src_data            (rsp_mux_001_src_data),                            //          .data
		.src_channel         (rsp_mux_001_src_channel),                         //          .channel
		.src_startofpacket   (rsp_mux_001_src_startofpacket),                   //          .startofpacket
		.src_endofpacket     (rsp_mux_001_src_endofpacket),                     //          .endofpacket
		.sink0_ready         (crosser_009_out_ready),                           //     sink0.ready
		.sink0_valid         (crosser_009_out_valid),                           //          .valid
		.sink0_channel       (crosser_009_out_channel),                         //          .channel
		.sink0_data          (crosser_009_out_data),                            //          .data
		.sink0_startofpacket (crosser_009_out_startofpacket),                   //          .startofpacket
		.sink0_endofpacket   (crosser_009_out_endofpacket)                      //          .endofpacket
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (50),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (61),
		.IN_PKT_BYTE_CNT_L             (57),
		.IN_PKT_TRANS_COMPRESSED_READ  (51),
		.IN_PKT_TRANS_WRITE            (53),
		.IN_PKT_BURSTWRAP_H            (62),
		.IN_PKT_BURSTWRAP_L            (62),
		.IN_PKT_BURST_SIZE_H           (65),
		.IN_PKT_BURST_SIZE_L           (63),
		.IN_PKT_RESPONSE_STATUS_H      (87),
		.IN_PKT_RESPONSE_STATUS_L      (86),
		.IN_PKT_TRANS_EXCLUSIVE        (56),
		.IN_PKT_BURST_TYPE_H           (67),
		.IN_PKT_BURST_TYPE_L           (66),
		.IN_PKT_ORI_BURST_SIZE_L       (88),
		.IN_PKT_ORI_BURST_SIZE_H       (90),
		.IN_ST_DATA_W                  (91),
		.OUT_PKT_ADDR_H                (158),
		.OUT_PKT_ADDR_L                (144),
		.OUT_PKT_DATA_H                (127),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (143),
		.OUT_PKT_BYTEEN_L              (128),
		.OUT_PKT_BYTE_CNT_H            (169),
		.OUT_PKT_BYTE_CNT_L            (165),
		.OUT_PKT_TRANS_COMPRESSED_READ (159),
		.OUT_PKT_BURST_SIZE_H          (173),
		.OUT_PKT_BURST_SIZE_L          (171),
		.OUT_PKT_RESPONSE_STATUS_H     (195),
		.OUT_PKT_RESPONSE_STATUS_L     (194),
		.OUT_PKT_TRANS_EXCLUSIVE       (164),
		.OUT_PKT_BURST_TYPE_H          (175),
		.OUT_PKT_BURST_TYPE_L          (174),
		.OUT_PKT_ORI_BURST_SIZE_L      (196),
		.OUT_PKT_ORI_BURST_SIZE_H      (198),
		.OUT_ST_DATA_W                 (199),
		.ST_CHANNEL_W                  (6),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (1),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0)
	) msgdma_0_descriptor_slave_cmd_width_adapter (
		.clk                  (custom_reset_synchronizer_0_clock_out_clk),                     //       clk.clk
		.reset                (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),               // clk_reset.reset
		.in_valid             (cmd_mux_004_src_valid),                                         //      sink.valid
		.in_channel           (cmd_mux_004_src_channel),                                       //          .channel
		.in_startofpacket     (cmd_mux_004_src_startofpacket),                                 //          .startofpacket
		.in_endofpacket       (cmd_mux_004_src_endofpacket),                                   //          .endofpacket
		.in_ready             (cmd_mux_004_src_ready),                                         //          .ready
		.in_data              (cmd_mux_004_src_data),                                          //          .data
		.out_endofpacket      (msgdma_0_descriptor_slave_cmd_width_adapter_src_endofpacket),   //       src.endofpacket
		.out_data             (msgdma_0_descriptor_slave_cmd_width_adapter_src_data),          //          .data
		.out_channel          (msgdma_0_descriptor_slave_cmd_width_adapter_src_channel),       //          .channel
		.out_valid            (msgdma_0_descriptor_slave_cmd_width_adapter_src_valid),         //          .valid
		.out_ready            (msgdma_0_descriptor_slave_cmd_width_adapter_src_ready),         //          .ready
		.out_startofpacket    (msgdma_0_descriptor_slave_cmd_width_adapter_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                                                         // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (158),
		.IN_PKT_ADDR_L                 (144),
		.IN_PKT_DATA_H                 (127),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (143),
		.IN_PKT_BYTEEN_L               (128),
		.IN_PKT_BYTE_CNT_H             (169),
		.IN_PKT_BYTE_CNT_L             (165),
		.IN_PKT_TRANS_COMPRESSED_READ  (159),
		.IN_PKT_TRANS_WRITE            (161),
		.IN_PKT_BURSTWRAP_H            (170),
		.IN_PKT_BURSTWRAP_L            (170),
		.IN_PKT_BURST_SIZE_H           (173),
		.IN_PKT_BURST_SIZE_L           (171),
		.IN_PKT_RESPONSE_STATUS_H      (195),
		.IN_PKT_RESPONSE_STATUS_L      (194),
		.IN_PKT_TRANS_EXCLUSIVE        (164),
		.IN_PKT_BURST_TYPE_H           (175),
		.IN_PKT_BURST_TYPE_L           (174),
		.IN_PKT_ORI_BURST_SIZE_L       (196),
		.IN_PKT_ORI_BURST_SIZE_H       (198),
		.IN_ST_DATA_W                  (199),
		.OUT_PKT_ADDR_H                (50),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (61),
		.OUT_PKT_BYTE_CNT_L            (57),
		.OUT_PKT_TRANS_COMPRESSED_READ (51),
		.OUT_PKT_BURST_SIZE_H          (65),
		.OUT_PKT_BURST_SIZE_L          (63),
		.OUT_PKT_RESPONSE_STATUS_H     (87),
		.OUT_PKT_RESPONSE_STATUS_L     (86),
		.OUT_PKT_TRANS_EXCLUSIVE       (56),
		.OUT_PKT_BURST_TYPE_H          (67),
		.OUT_PKT_BURST_TYPE_L          (66),
		.OUT_PKT_ORI_BURST_SIZE_L      (88),
		.OUT_PKT_ORI_BURST_SIZE_H      (90),
		.OUT_ST_DATA_W                 (91),
		.ST_CHANNEL_W                  (6),
		.OPTIMIZE_FOR_RSP              (1),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (1),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0)
	) msgdma_0_descriptor_slave_rsp_width_adapter (
		.clk                  (custom_reset_synchronizer_0_clock_out_clk),                     //       clk.clk
		.reset                (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),               // clk_reset.reset
		.in_valid             (router_006_src_valid),                                          //      sink.valid
		.in_channel           (router_006_src_channel),                                        //          .channel
		.in_startofpacket     (router_006_src_startofpacket),                                  //          .startofpacket
		.in_endofpacket       (router_006_src_endofpacket),                                    //          .endofpacket
		.in_ready             (router_006_src_ready),                                          //          .ready
		.in_data              (router_006_src_data),                                           //          .data
		.out_endofpacket      (msgdma_0_descriptor_slave_rsp_width_adapter_src_endofpacket),   //       src.endofpacket
		.out_data             (msgdma_0_descriptor_slave_rsp_width_adapter_src_data),          //          .data
		.out_channel          (msgdma_0_descriptor_slave_rsp_width_adapter_src_channel),       //          .channel
		.out_valid            (msgdma_0_descriptor_slave_rsp_width_adapter_src_valid),         //          .valid
		.out_ready            (msgdma_0_descriptor_slave_rsp_width_adapter_src_ready),         //          .ready
		.out_startofpacket    (msgdma_0_descriptor_slave_rsp_width_adapter_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                                                         // (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (91),
		.BITS_PER_SYMBOL     (91),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (6),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser (
		.in_clk            (custom_reset_synchronizer_0_clock_out_clk),                      //        in_clk.clk
		.in_reset          (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),                //  in_clk_reset.reset
		.out_clk           (pcie_hip_avmm_coreclkout_clk),                                   //       out_clk.clk
		.out_reset         (pcie_hip_avmm_Cra_translator_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
		.in_ready          (cmd_demux_src0_ready),                                           //            in.ready
		.in_valid          (cmd_demux_src0_valid),                                           //              .valid
		.in_startofpacket  (cmd_demux_src0_startofpacket),                                   //              .startofpacket
		.in_endofpacket    (cmd_demux_src0_endofpacket),                                     //              .endofpacket
		.in_channel        (cmd_demux_src0_channel),                                         //              .channel
		.in_data           (cmd_demux_src0_data),                                            //              .data
		.out_ready         (crosser_out_ready),                                              //           out.ready
		.out_valid         (crosser_out_valid),                                              //              .valid
		.out_startofpacket (crosser_out_startofpacket),                                      //              .startofpacket
		.out_endofpacket   (crosser_out_endofpacket),                                        //              .endofpacket
		.out_channel       (crosser_out_channel),                                            //              .channel
		.out_data          (crosser_out_data),                                               //              .data
		.in_empty          (1'b0),                                                           //   (terminated)
		.in_error          (1'b0),                                                           //   (terminated)
		.out_empty         (),                                                               //   (terminated)
		.out_error         ()                                                                //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (91),
		.BITS_PER_SYMBOL     (91),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (6),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_001 (
		.in_clk            (custom_reset_synchronizer_0_clock_out_clk),               //        in_clk.clk
		.in_reset          (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),         //  in_clk_reset.reset
		.out_clk           (clk_clk_clk),                                             //       out_clk.clk
		.out_reset         (performance_counter_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
		.in_ready          (cmd_demux_src1_ready),                                    //            in.ready
		.in_valid          (cmd_demux_src1_valid),                                    //              .valid
		.in_startofpacket  (cmd_demux_src1_startofpacket),                            //              .startofpacket
		.in_endofpacket    (cmd_demux_src1_endofpacket),                              //              .endofpacket
		.in_channel        (cmd_demux_src1_channel),                                  //              .channel
		.in_data           (cmd_demux_src1_data),                                     //              .data
		.out_ready         (crosser_001_out_ready),                                   //           out.ready
		.out_valid         (crosser_001_out_valid),                                   //              .valid
		.out_startofpacket (crosser_001_out_startofpacket),                           //              .startofpacket
		.out_endofpacket   (crosser_001_out_endofpacket),                             //              .endofpacket
		.out_channel       (crosser_001_out_channel),                                 //              .channel
		.out_data          (crosser_001_out_data),                                    //              .data
		.in_empty          (1'b0),                                                    //   (terminated)
		.in_error          (1'b0),                                                    //   (terminated)
		.out_empty         (),                                                        //   (terminated)
		.out_error         ()                                                         //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (91),
		.BITS_PER_SYMBOL     (91),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (6),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_002 (
		.in_clk            (custom_reset_synchronizer_0_clock_out_clk),               //        in_clk.clk
		.in_reset          (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),         //  in_clk_reset.reset
		.out_clk           (clk_clk_clk),                                             //       out_clk.clk
		.out_reset         (performance_counter_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
		.in_ready          (cmd_demux_src3_ready),                                    //            in.ready
		.in_valid          (cmd_demux_src3_valid),                                    //              .valid
		.in_startofpacket  (cmd_demux_src3_startofpacket),                            //              .startofpacket
		.in_endofpacket    (cmd_demux_src3_endofpacket),                              //              .endofpacket
		.in_channel        (cmd_demux_src3_channel),                                  //              .channel
		.in_data           (cmd_demux_src3_data),                                     //              .data
		.out_ready         (crosser_002_out_ready),                                   //           out.ready
		.out_valid         (crosser_002_out_valid),                                   //              .valid
		.out_startofpacket (crosser_002_out_startofpacket),                           //              .startofpacket
		.out_endofpacket   (crosser_002_out_endofpacket),                             //              .endofpacket
		.out_channel       (crosser_002_out_channel),                                 //              .channel
		.out_data          (crosser_002_out_data),                                    //              .data
		.in_empty          (1'b0),                                                    //   (terminated)
		.in_error          (1'b0),                                                    //   (terminated)
		.out_empty         (),                                                        //   (terminated)
		.out_error         ()                                                         //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (91),
		.BITS_PER_SYMBOL     (91),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (6),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_003 (
		.in_clk            (custom_reset_synchronizer_0_clock_out_clk),               //        in_clk.clk
		.in_reset          (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),         //  in_clk_reset.reset
		.out_clk           (clk_clk_clk),                                             //       out_clk.clk
		.out_reset         (performance_counter_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
		.in_ready          (cmd_demux_src5_ready),                                    //            in.ready
		.in_valid          (cmd_demux_src5_valid),                                    //              .valid
		.in_startofpacket  (cmd_demux_src5_startofpacket),                            //              .startofpacket
		.in_endofpacket    (cmd_demux_src5_endofpacket),                              //              .endofpacket
		.in_channel        (cmd_demux_src5_channel),                                  //              .channel
		.in_data           (cmd_demux_src5_data),                                     //              .data
		.out_ready         (crosser_003_out_ready),                                   //           out.ready
		.out_valid         (crosser_003_out_valid),                                   //              .valid
		.out_startofpacket (crosser_003_out_startofpacket),                           //              .startofpacket
		.out_endofpacket   (crosser_003_out_endofpacket),                             //              .endofpacket
		.out_channel       (crosser_003_out_channel),                                 //              .channel
		.out_data          (crosser_003_out_data),                                    //              .data
		.in_empty          (1'b0),                                                    //   (terminated)
		.in_error          (1'b0),                                                    //   (terminated)
		.out_empty         (),                                                        //   (terminated)
		.out_error         ()                                                         //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (91),
		.BITS_PER_SYMBOL     (91),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (6),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_004 (
		.in_clk            (custom_reset_synchronizer_0_clock_out_clk),               //        in_clk.clk
		.in_reset          (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),         //  in_clk_reset.reset
		.out_clk           (clk_clk_clk),                                             //       out_clk.clk
		.out_reset         (performance_counter_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
		.in_ready          (cmd_demux_001_src0_ready),                                //            in.ready
		.in_valid          (cmd_demux_001_src0_valid),                                //              .valid
		.in_startofpacket  (cmd_demux_001_src0_startofpacket),                        //              .startofpacket
		.in_endofpacket    (cmd_demux_001_src0_endofpacket),                          //              .endofpacket
		.in_channel        (cmd_demux_001_src0_channel),                              //              .channel
		.in_data           (cmd_demux_001_src0_data),                                 //              .data
		.out_ready         (crosser_004_out_ready),                                   //           out.ready
		.out_valid         (crosser_004_out_valid),                                   //              .valid
		.out_startofpacket (crosser_004_out_startofpacket),                           //              .startofpacket
		.out_endofpacket   (crosser_004_out_endofpacket),                             //              .endofpacket
		.out_channel       (crosser_004_out_channel),                                 //              .channel
		.out_data          (crosser_004_out_data),                                    //              .data
		.in_empty          (1'b0),                                                    //   (terminated)
		.in_error          (1'b0),                                                    //   (terminated)
		.out_empty         (),                                                        //   (terminated)
		.out_error         ()                                                         //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (91),
		.BITS_PER_SYMBOL     (91),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (6),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_005 (
		.in_clk            (pcie_hip_avmm_coreclkout_clk),                                   //        in_clk.clk
		.in_reset          (pcie_hip_avmm_Cra_translator_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset
		.out_clk           (custom_reset_synchronizer_0_clock_out_clk),                      //       out_clk.clk
		.out_reset         (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),                // out_clk_reset.reset
		.in_ready          (rsp_demux_src0_ready),                                           //            in.ready
		.in_valid          (rsp_demux_src0_valid),                                           //              .valid
		.in_startofpacket  (rsp_demux_src0_startofpacket),                                   //              .startofpacket
		.in_endofpacket    (rsp_demux_src0_endofpacket),                                     //              .endofpacket
		.in_channel        (rsp_demux_src0_channel),                                         //              .channel
		.in_data           (rsp_demux_src0_data),                                            //              .data
		.out_ready         (crosser_005_out_ready),                                          //           out.ready
		.out_valid         (crosser_005_out_valid),                                          //              .valid
		.out_startofpacket (crosser_005_out_startofpacket),                                  //              .startofpacket
		.out_endofpacket   (crosser_005_out_endofpacket),                                    //              .endofpacket
		.out_channel       (crosser_005_out_channel),                                        //              .channel
		.out_data          (crosser_005_out_data),                                           //              .data
		.in_empty          (1'b0),                                                           //   (terminated)
		.in_error          (1'b0),                                                           //   (terminated)
		.out_empty         (),                                                               //   (terminated)
		.out_error         ()                                                                //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (91),
		.BITS_PER_SYMBOL     (91),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (6),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_006 (
		.in_clk            (clk_clk_clk),                                             //        in_clk.clk
		.in_reset          (performance_counter_0_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset
		.out_clk           (custom_reset_synchronizer_0_clock_out_clk),               //       out_clk.clk
		.out_reset         (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),         // out_clk_reset.reset
		.in_ready          (rsp_demux_001_src0_ready),                                //            in.ready
		.in_valid          (rsp_demux_001_src0_valid),                                //              .valid
		.in_startofpacket  (rsp_demux_001_src0_startofpacket),                        //              .startofpacket
		.in_endofpacket    (rsp_demux_001_src0_endofpacket),                          //              .endofpacket
		.in_channel        (rsp_demux_001_src0_channel),                              //              .channel
		.in_data           (rsp_demux_001_src0_data),                                 //              .data
		.out_ready         (crosser_006_out_ready),                                   //           out.ready
		.out_valid         (crosser_006_out_valid),                                   //              .valid
		.out_startofpacket (crosser_006_out_startofpacket),                           //              .startofpacket
		.out_endofpacket   (crosser_006_out_endofpacket),                             //              .endofpacket
		.out_channel       (crosser_006_out_channel),                                 //              .channel
		.out_data          (crosser_006_out_data),                                    //              .data
		.in_empty          (1'b0),                                                    //   (terminated)
		.in_error          (1'b0),                                                    //   (terminated)
		.out_empty         (),                                                        //   (terminated)
		.out_error         ()                                                         //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (91),
		.BITS_PER_SYMBOL     (91),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (6),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_007 (
		.in_clk            (clk_clk_clk),                                             //        in_clk.clk
		.in_reset          (performance_counter_0_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset
		.out_clk           (custom_reset_synchronizer_0_clock_out_clk),               //       out_clk.clk
		.out_reset         (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),         // out_clk_reset.reset
		.in_ready          (rsp_demux_003_src0_ready),                                //            in.ready
		.in_valid          (rsp_demux_003_src0_valid),                                //              .valid
		.in_startofpacket  (rsp_demux_003_src0_startofpacket),                        //              .startofpacket
		.in_endofpacket    (rsp_demux_003_src0_endofpacket),                          //              .endofpacket
		.in_channel        (rsp_demux_003_src0_channel),                              //              .channel
		.in_data           (rsp_demux_003_src0_data),                                 //              .data
		.out_ready         (crosser_007_out_ready),                                   //           out.ready
		.out_valid         (crosser_007_out_valid),                                   //              .valid
		.out_startofpacket (crosser_007_out_startofpacket),                           //              .startofpacket
		.out_endofpacket   (crosser_007_out_endofpacket),                             //              .endofpacket
		.out_channel       (crosser_007_out_channel),                                 //              .channel
		.out_data          (crosser_007_out_data),                                    //              .data
		.in_empty          (1'b0),                                                    //   (terminated)
		.in_error          (1'b0),                                                    //   (terminated)
		.out_empty         (),                                                        //   (terminated)
		.out_error         ()                                                         //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (91),
		.BITS_PER_SYMBOL     (91),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (6),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_008 (
		.in_clk            (clk_clk_clk),                                             //        in_clk.clk
		.in_reset          (performance_counter_0_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset
		.out_clk           (custom_reset_synchronizer_0_clock_out_clk),               //       out_clk.clk
		.out_reset         (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),         // out_clk_reset.reset
		.in_ready          (rsp_demux_005_src0_ready),                                //            in.ready
		.in_valid          (rsp_demux_005_src0_valid),                                //              .valid
		.in_startofpacket  (rsp_demux_005_src0_startofpacket),                        //              .startofpacket
		.in_endofpacket    (rsp_demux_005_src0_endofpacket),                          //              .endofpacket
		.in_channel        (rsp_demux_005_src0_channel),                              //              .channel
		.in_data           (rsp_demux_005_src0_data),                                 //              .data
		.out_ready         (crosser_008_out_ready),                                   //           out.ready
		.out_valid         (crosser_008_out_valid),                                   //              .valid
		.out_startofpacket (crosser_008_out_startofpacket),                           //              .startofpacket
		.out_endofpacket   (crosser_008_out_endofpacket),                             //              .endofpacket
		.out_channel       (crosser_008_out_channel),                                 //              .channel
		.out_data          (crosser_008_out_data),                                    //              .data
		.in_empty          (1'b0),                                                    //   (terminated)
		.in_error          (1'b0),                                                    //   (terminated)
		.out_empty         (),                                                        //   (terminated)
		.out_error         ()                                                         //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (91),
		.BITS_PER_SYMBOL     (91),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (6),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_009 (
		.in_clk            (clk_clk_clk),                                             //        in_clk.clk
		.in_reset          (performance_counter_0_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset
		.out_clk           (custom_reset_synchronizer_0_clock_out_clk),               //       out_clk.clk
		.out_reset         (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),         // out_clk_reset.reset
		.in_ready          (rsp_demux_005_src1_ready),                                //            in.ready
		.in_valid          (rsp_demux_005_src1_valid),                                //              .valid
		.in_startofpacket  (rsp_demux_005_src1_startofpacket),                        //              .startofpacket
		.in_endofpacket    (rsp_demux_005_src1_endofpacket),                          //              .endofpacket
		.in_channel        (rsp_demux_005_src1_channel),                              //              .channel
		.in_data           (rsp_demux_005_src1_data),                                 //              .data
		.out_ready         (crosser_009_out_ready),                                   //           out.ready
		.out_valid         (crosser_009_out_valid),                                   //              .valid
		.out_startofpacket (crosser_009_out_startofpacket),                           //              .startofpacket
		.out_endofpacket   (crosser_009_out_endofpacket),                             //              .endofpacket
		.out_channel       (crosser_009_out_channel),                                 //              .channel
		.out_data          (crosser_009_out_data),                                    //              .data
		.in_empty          (1'b0),                                                    //   (terminated)
		.in_error          (1'b0),                                                    //   (terminated)
		.out_empty         (),                                                        //   (terminated)
		.out_error         ()                                                         //   (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (91),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (6),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) limiter_pipeline (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),       //       cr0.clk
		.reset             (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (pb_lwh2f_pcie_m0_limiter_cmd_src_ready),          //     sink0.ready
		.in_valid          (pb_lwh2f_pcie_m0_limiter_cmd_src_valid),          //          .valid
		.in_startofpacket  (pb_lwh2f_pcie_m0_limiter_cmd_src_startofpacket),  //          .startofpacket
		.in_endofpacket    (pb_lwh2f_pcie_m0_limiter_cmd_src_endofpacket),    //          .endofpacket
		.in_data           (pb_lwh2f_pcie_m0_limiter_cmd_src_data),           //          .data
		.in_channel        (pb_lwh2f_pcie_m0_limiter_cmd_src_channel),        //          .channel
		.out_ready         (limiter_pipeline_source0_ready),                  //   source0.ready
		.out_valid         (limiter_pipeline_source0_valid),                  //          .valid
		.out_startofpacket (limiter_pipeline_source0_startofpacket),          //          .startofpacket
		.out_endofpacket   (limiter_pipeline_source0_endofpacket),            //          .endofpacket
		.out_data          (limiter_pipeline_source0_data),                   //          .data
		.out_channel       (limiter_pipeline_source0_channel),                //          .channel
		.in_empty          (1'b0),                                            // (terminated)
		.out_empty         (),                                                // (terminated)
		.out_error         (),                                                // (terminated)
		.in_error          (1'b0)                                             // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (91),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (6),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) limiter_pipeline_001 (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),       //       cr0.clk
		.reset             (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (rsp_mux_src_ready),                               //     sink0.ready
		.in_valid          (rsp_mux_src_valid),                               //          .valid
		.in_startofpacket  (rsp_mux_src_startofpacket),                       //          .startofpacket
		.in_endofpacket    (rsp_mux_src_endofpacket),                         //          .endofpacket
		.in_data           (rsp_mux_src_data),                                //          .data
		.in_channel        (rsp_mux_src_channel),                             //          .channel
		.out_ready         (limiter_pipeline_001_source0_ready),              //   source0.ready
		.out_valid         (limiter_pipeline_001_source0_valid),              //          .valid
		.out_startofpacket (limiter_pipeline_001_source0_startofpacket),      //          .startofpacket
		.out_endofpacket   (limiter_pipeline_001_source0_endofpacket),        //          .endofpacket
		.out_data          (limiter_pipeline_001_source0_data),               //          .data
		.out_channel       (limiter_pipeline_001_source0_channel),            //          .channel
		.in_empty          (1'b0),                                            // (terminated)
		.out_empty         (),                                                // (terminated)
		.out_error         (),                                                // (terminated)
		.in_error          (1'b0)                                             // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (91),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (6),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline (
		.clk               (pcie_hip_avmm_coreclkout_clk),                                   //       cr0.clk
		.reset             (pcie_hip_avmm_Cra_translator_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (cmd_mux_src_ready),                                              //     sink0.ready
		.in_valid          (cmd_mux_src_valid),                                              //          .valid
		.in_startofpacket  (cmd_mux_src_startofpacket),                                      //          .startofpacket
		.in_endofpacket    (cmd_mux_src_endofpacket),                                        //          .endofpacket
		.in_data           (cmd_mux_src_data),                                               //          .data
		.in_channel        (cmd_mux_src_channel),                                            //          .channel
		.out_ready         (agent_pipeline_source0_ready),                                   //   source0.ready
		.out_valid         (agent_pipeline_source0_valid),                                   //          .valid
		.out_startofpacket (agent_pipeline_source0_startofpacket),                           //          .startofpacket
		.out_endofpacket   (agent_pipeline_source0_endofpacket),                             //          .endofpacket
		.out_data          (agent_pipeline_source0_data),                                    //          .data
		.out_channel       (agent_pipeline_source0_channel),                                 //          .channel
		.in_empty          (1'b0),                                                           // (terminated)
		.out_empty         (),                                                               // (terminated)
		.out_error         (),                                                               // (terminated)
		.in_error          (1'b0)                                                            // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (91),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_001 (
		.clk               (pcie_hip_avmm_coreclkout_clk),                                   //       cr0.clk
		.reset             (pcie_hip_avmm_Cra_translator_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (pcie_hip_avmm_cra_agent_rp_ready),                               //     sink0.ready
		.in_valid          (pcie_hip_avmm_cra_agent_rp_valid),                               //          .valid
		.in_startofpacket  (pcie_hip_avmm_cra_agent_rp_startofpacket),                       //          .startofpacket
		.in_endofpacket    (pcie_hip_avmm_cra_agent_rp_endofpacket),                         //          .endofpacket
		.in_data           (pcie_hip_avmm_cra_agent_rp_data),                                //          .data
		.out_ready         (agent_pipeline_001_source0_ready),                               //   source0.ready
		.out_valid         (agent_pipeline_001_source0_valid),                               //          .valid
		.out_startofpacket (agent_pipeline_001_source0_startofpacket),                       //          .startofpacket
		.out_endofpacket   (agent_pipeline_001_source0_endofpacket),                         //          .endofpacket
		.out_data          (agent_pipeline_001_source0_data),                                //          .data
		.in_empty          (1'b0),                                                           // (terminated)
		.out_empty         (),                                                               // (terminated)
		.out_error         (),                                                               // (terminated)
		.in_error          (1'b0),                                                           // (terminated)
		.out_channel       (),                                                               // (terminated)
		.in_channel        (1'b0)                                                            // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (91),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (6),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_002 (
		.clk               (clk_clk_clk),                                             //       cr0.clk
		.reset             (performance_counter_0_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (cmd_mux_001_src_ready),                                   //     sink0.ready
		.in_valid          (cmd_mux_001_src_valid),                                   //          .valid
		.in_startofpacket  (cmd_mux_001_src_startofpacket),                           //          .startofpacket
		.in_endofpacket    (cmd_mux_001_src_endofpacket),                             //          .endofpacket
		.in_data           (cmd_mux_001_src_data),                                    //          .data
		.in_channel        (cmd_mux_001_src_channel),                                 //          .channel
		.out_ready         (agent_pipeline_002_source0_ready),                        //   source0.ready
		.out_valid         (agent_pipeline_002_source0_valid),                        //          .valid
		.out_startofpacket (agent_pipeline_002_source0_startofpacket),                //          .startofpacket
		.out_endofpacket   (agent_pipeline_002_source0_endofpacket),                  //          .endofpacket
		.out_data          (agent_pipeline_002_source0_data),                         //          .data
		.out_channel       (agent_pipeline_002_source0_channel),                      //          .channel
		.in_empty          (1'b0),                                                    // (terminated)
		.out_empty         (),                                                        // (terminated)
		.out_error         (),                                                        // (terminated)
		.in_error          (1'b0)                                                     // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (91),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_003 (
		.clk               (clk_clk_clk),                                                //       cr0.clk
		.reset             (performance_counter_0_reset_reset_bridge_in_reset_reset),    // cr0_reset.reset
		.in_ready          (performance_counter_0_control_slave_agent_rp_ready),         //     sink0.ready
		.in_valid          (performance_counter_0_control_slave_agent_rp_valid),         //          .valid
		.in_startofpacket  (performance_counter_0_control_slave_agent_rp_startofpacket), //          .startofpacket
		.in_endofpacket    (performance_counter_0_control_slave_agent_rp_endofpacket),   //          .endofpacket
		.in_data           (performance_counter_0_control_slave_agent_rp_data),          //          .data
		.out_ready         (agent_pipeline_003_source0_ready),                           //   source0.ready
		.out_valid         (agent_pipeline_003_source0_valid),                           //          .valid
		.out_startofpacket (agent_pipeline_003_source0_startofpacket),                   //          .startofpacket
		.out_endofpacket   (agent_pipeline_003_source0_endofpacket),                     //          .endofpacket
		.out_data          (agent_pipeline_003_source0_data),                            //          .data
		.in_empty          (1'b0),                                                       // (terminated)
		.out_empty         (),                                                           // (terminated)
		.out_error         (),                                                           // (terminated)
		.in_error          (1'b0),                                                       // (terminated)
		.out_channel       (),                                                           // (terminated)
		.in_channel        (1'b0)                                                        // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (91),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (6),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_004 (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),       //       cr0.clk
		.reset             (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (cmd_mux_002_src_ready),                           //     sink0.ready
		.in_valid          (cmd_mux_002_src_valid),                           //          .valid
		.in_startofpacket  (cmd_mux_002_src_startofpacket),                   //          .startofpacket
		.in_endofpacket    (cmd_mux_002_src_endofpacket),                     //          .endofpacket
		.in_data           (cmd_mux_002_src_data),                            //          .data
		.in_channel        (cmd_mux_002_src_channel),                         //          .channel
		.out_ready         (agent_pipeline_004_source0_ready),                //   source0.ready
		.out_valid         (agent_pipeline_004_source0_valid),                //          .valid
		.out_startofpacket (agent_pipeline_004_source0_startofpacket),        //          .startofpacket
		.out_endofpacket   (agent_pipeline_004_source0_endofpacket),          //          .endofpacket
		.out_data          (agent_pipeline_004_source0_data),                 //          .data
		.out_channel       (agent_pipeline_004_source0_channel),              //          .channel
		.in_empty          (1'b0),                                            // (terminated)
		.out_empty         (),                                                // (terminated)
		.out_error         (),                                                // (terminated)
		.in_error          (1'b0)                                             // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (91),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_005 (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),       //       cr0.clk
		.reset             (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (msgdma_0_csr_agent_rp_ready),                     //     sink0.ready
		.in_valid          (msgdma_0_csr_agent_rp_valid),                     //          .valid
		.in_startofpacket  (msgdma_0_csr_agent_rp_startofpacket),             //          .startofpacket
		.in_endofpacket    (msgdma_0_csr_agent_rp_endofpacket),               //          .endofpacket
		.in_data           (msgdma_0_csr_agent_rp_data),                      //          .data
		.out_ready         (agent_pipeline_005_source0_ready),                //   source0.ready
		.out_valid         (agent_pipeline_005_source0_valid),                //          .valid
		.out_startofpacket (agent_pipeline_005_source0_startofpacket),        //          .startofpacket
		.out_endofpacket   (agent_pipeline_005_source0_endofpacket),          //          .endofpacket
		.out_data          (agent_pipeline_005_source0_data),                 //          .data
		.in_empty          (1'b0),                                            // (terminated)
		.out_empty         (),                                                // (terminated)
		.out_error         (),                                                // (terminated)
		.in_error          (1'b0),                                            // (terminated)
		.out_channel       (),                                                // (terminated)
		.in_channel        (1'b0)                                             // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (91),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (6),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_006 (
		.clk               (clk_clk_clk),                                             //       cr0.clk
		.reset             (performance_counter_0_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (cmd_mux_003_src_ready),                                   //     sink0.ready
		.in_valid          (cmd_mux_003_src_valid),                                   //          .valid
		.in_startofpacket  (cmd_mux_003_src_startofpacket),                           //          .startofpacket
		.in_endofpacket    (cmd_mux_003_src_endofpacket),                             //          .endofpacket
		.in_data           (cmd_mux_003_src_data),                                    //          .data
		.in_channel        (cmd_mux_003_src_channel),                                 //          .channel
		.out_ready         (agent_pipeline_006_source0_ready),                        //   source0.ready
		.out_valid         (agent_pipeline_006_source0_valid),                        //          .valid
		.out_startofpacket (agent_pipeline_006_source0_startofpacket),                //          .startofpacket
		.out_endofpacket   (agent_pipeline_006_source0_endofpacket),                  //          .endofpacket
		.out_data          (agent_pipeline_006_source0_data),                         //          .data
		.out_channel       (agent_pipeline_006_source0_channel),                      //          .channel
		.in_empty          (1'b0),                                                    // (terminated)
		.out_empty         (),                                                        // (terminated)
		.out_error         (),                                                        // (terminated)
		.in_error          (1'b0)                                                     // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (91),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_007 (
		.clk               (clk_clk_clk),                                             //       cr0.clk
		.reset             (performance_counter_0_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (msi_to_gic_gen_0_csr_agent_rp_ready),                     //     sink0.ready
		.in_valid          (msi_to_gic_gen_0_csr_agent_rp_valid),                     //          .valid
		.in_startofpacket  (msi_to_gic_gen_0_csr_agent_rp_startofpacket),             //          .startofpacket
		.in_endofpacket    (msi_to_gic_gen_0_csr_agent_rp_endofpacket),               //          .endofpacket
		.in_data           (msi_to_gic_gen_0_csr_agent_rp_data),                      //          .data
		.out_ready         (agent_pipeline_007_source0_ready),                        //   source0.ready
		.out_valid         (agent_pipeline_007_source0_valid),                        //          .valid
		.out_startofpacket (agent_pipeline_007_source0_startofpacket),                //          .startofpacket
		.out_endofpacket   (agent_pipeline_007_source0_endofpacket),                  //          .endofpacket
		.out_data          (agent_pipeline_007_source0_data),                         //          .data
		.in_empty          (1'b0),                                                    // (terminated)
		.out_empty         (),                                                        // (terminated)
		.out_error         (),                                                        // (terminated)
		.in_error          (1'b0),                                                    // (terminated)
		.out_channel       (),                                                        // (terminated)
		.in_channel        (1'b0)                                                     // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (199),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (6),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_008 (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),                     //       cr0.clk
		.reset             (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),               // cr0_reset.reset
		.in_ready          (msgdma_0_descriptor_slave_cmd_width_adapter_src_ready),         //     sink0.ready
		.in_valid          (msgdma_0_descriptor_slave_cmd_width_adapter_src_valid),         //          .valid
		.in_startofpacket  (msgdma_0_descriptor_slave_cmd_width_adapter_src_startofpacket), //          .startofpacket
		.in_endofpacket    (msgdma_0_descriptor_slave_cmd_width_adapter_src_endofpacket),   //          .endofpacket
		.in_data           (msgdma_0_descriptor_slave_cmd_width_adapter_src_data),          //          .data
		.in_channel        (msgdma_0_descriptor_slave_cmd_width_adapter_src_channel),       //          .channel
		.out_ready         (agent_pipeline_008_source0_ready),                              //   source0.ready
		.out_valid         (agent_pipeline_008_source0_valid),                              //          .valid
		.out_startofpacket (agent_pipeline_008_source0_startofpacket),                      //          .startofpacket
		.out_endofpacket   (agent_pipeline_008_source0_endofpacket),                        //          .endofpacket
		.out_data          (agent_pipeline_008_source0_data),                               //          .data
		.out_channel       (agent_pipeline_008_source0_channel),                            //          .channel
		.in_empty          (1'b0),                                                          // (terminated)
		.out_empty         (),                                                              // (terminated)
		.out_error         (),                                                              // (terminated)
		.in_error          (1'b0)                                                           // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (199),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_009 (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),        //       cr0.clk
		.reset             (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),  // cr0_reset.reset
		.in_ready          (msgdma_0_descriptor_slave_agent_rp_ready),         //     sink0.ready
		.in_valid          (msgdma_0_descriptor_slave_agent_rp_valid),         //          .valid
		.in_startofpacket  (msgdma_0_descriptor_slave_agent_rp_startofpacket), //          .startofpacket
		.in_endofpacket    (msgdma_0_descriptor_slave_agent_rp_endofpacket),   //          .endofpacket
		.in_data           (msgdma_0_descriptor_slave_agent_rp_data),          //          .data
		.out_ready         (agent_pipeline_009_source0_ready),                 //   source0.ready
		.out_valid         (agent_pipeline_009_source0_valid),                 //          .valid
		.out_startofpacket (agent_pipeline_009_source0_startofpacket),         //          .startofpacket
		.out_endofpacket   (agent_pipeline_009_source0_endofpacket),           //          .endofpacket
		.out_data          (agent_pipeline_009_source0_data),                  //          .data
		.in_empty          (1'b0),                                             // (terminated)
		.out_empty         (),                                                 // (terminated)
		.out_error         (),                                                 // (terminated)
		.in_error          (1'b0),                                             // (terminated)
		.out_channel       (),                                                 // (terminated)
		.in_channel        (1'b0)                                              // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (91),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (6),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_010 (
		.clk               (clk_clk_clk),                                             //       cr0.clk
		.reset             (performance_counter_0_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (cmd_mux_005_src_ready),                                   //     sink0.ready
		.in_valid          (cmd_mux_005_src_valid),                                   //          .valid
		.in_startofpacket  (cmd_mux_005_src_startofpacket),                           //          .startofpacket
		.in_endofpacket    (cmd_mux_005_src_endofpacket),                             //          .endofpacket
		.in_data           (cmd_mux_005_src_data),                                    //          .data
		.in_channel        (cmd_mux_005_src_channel),                                 //          .channel
		.out_ready         (agent_pipeline_010_source0_ready),                        //   source0.ready
		.out_valid         (agent_pipeline_010_source0_valid),                        //          .valid
		.out_startofpacket (agent_pipeline_010_source0_startofpacket),                //          .startofpacket
		.out_endofpacket   (agent_pipeline_010_source0_endofpacket),                  //          .endofpacket
		.out_data          (agent_pipeline_010_source0_data),                         //          .data
		.out_channel       (agent_pipeline_010_source0_channel),                      //          .channel
		.in_empty          (1'b0),                                                    // (terminated)
		.out_empty         (),                                                        // (terminated)
		.out_error         (),                                                        // (terminated)
		.in_error          (1'b0)                                                     // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (91),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_011 (
		.clk               (clk_clk_clk),                                             //       cr0.clk
		.reset             (performance_counter_0_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (msi_to_gic_gen_0_vector_slave_agent_rp_ready),            //     sink0.ready
		.in_valid          (msi_to_gic_gen_0_vector_slave_agent_rp_valid),            //          .valid
		.in_startofpacket  (msi_to_gic_gen_0_vector_slave_agent_rp_startofpacket),    //          .startofpacket
		.in_endofpacket    (msi_to_gic_gen_0_vector_slave_agent_rp_endofpacket),      //          .endofpacket
		.in_data           (msi_to_gic_gen_0_vector_slave_agent_rp_data),             //          .data
		.out_ready         (agent_pipeline_011_source0_ready),                        //   source0.ready
		.out_valid         (agent_pipeline_011_source0_valid),                        //          .valid
		.out_startofpacket (agent_pipeline_011_source0_startofpacket),                //          .startofpacket
		.out_endofpacket   (agent_pipeline_011_source0_endofpacket),                  //          .endofpacket
		.out_data          (agent_pipeline_011_source0_data),                         //          .data
		.in_empty          (1'b0),                                                    // (terminated)
		.out_empty         (),                                                        // (terminated)
		.out_error         (),                                                        // (terminated)
		.in_error          (1'b0),                                                    // (terminated)
		.out_channel       (),                                                        // (terminated)
		.in_channel        (1'b0)                                                     // (terminated)
	);

	soc_system_mm_interconnect_2_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter (
		.in_clk_0_clk   (pcie_hip_avmm_coreclkout_clk),                                   // in_clk_0.clk
		.in_rst_0_reset (pcie_hip_avmm_Cra_translator_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (pcie_hip_avmm_cra_agent_rdata_fifo_out_data),                    //     in_0.data
		.in_0_valid     (pcie_hip_avmm_cra_agent_rdata_fifo_out_valid),                   //         .valid
		.in_0_ready     (pcie_hip_avmm_cra_agent_rdata_fifo_out_ready),                   //         .ready
		.out_0_data     (avalon_st_adapter_out_0_data),                                   //    out_0.data
		.out_0_valid    (avalon_st_adapter_out_0_valid),                                  //         .valid
		.out_0_ready    (avalon_st_adapter_out_0_ready),                                  //         .ready
		.out_0_error    (avalon_st_adapter_out_0_error)                                   //         .error
	);

	soc_system_mm_interconnect_2_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_001 (
		.in_clk_0_clk   (clk_clk_clk),                                                    // in_clk_0.clk
		.in_rst_0_reset (performance_counter_0_reset_reset_bridge_in_reset_reset),        // in_rst_0.reset
		.in_0_data      (performance_counter_0_control_slave_agent_rdata_fifo_out_data),  //     in_0.data
		.in_0_valid     (performance_counter_0_control_slave_agent_rdata_fifo_out_valid), //         .valid
		.in_0_ready     (performance_counter_0_control_slave_agent_rdata_fifo_out_ready), //         .ready
		.out_0_data     (avalon_st_adapter_001_out_0_data),                               //    out_0.data
		.out_0_valid    (avalon_st_adapter_001_out_0_valid),                              //         .valid
		.out_0_ready    (avalon_st_adapter_001_out_0_ready),                              //         .ready
		.out_0_error    (avalon_st_adapter_001_out_0_error)                               //         .error
	);

	soc_system_mm_interconnect_2_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_002 (
		.in_clk_0_clk   (custom_reset_synchronizer_0_clock_out_clk),       // in_clk_0.clk
		.in_rst_0_reset (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (msgdma_0_csr_agent_rdata_fifo_src_data),          //     in_0.data
		.in_0_valid     (msgdma_0_csr_agent_rdata_fifo_src_valid),         //         .valid
		.in_0_ready     (msgdma_0_csr_agent_rdata_fifo_src_ready),         //         .ready
		.out_0_data     (avalon_st_adapter_002_out_0_data),                //    out_0.data
		.out_0_valid    (avalon_st_adapter_002_out_0_valid),               //         .valid
		.out_0_ready    (avalon_st_adapter_002_out_0_ready),               //         .ready
		.out_0_error    (avalon_st_adapter_002_out_0_error)                //         .error
	);

	soc_system_mm_interconnect_2_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_003 (
		.in_clk_0_clk   (clk_clk_clk),                                             // in_clk_0.clk
		.in_rst_0_reset (performance_counter_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (msi_to_gic_gen_0_csr_agent_rdata_fifo_out_data),          //     in_0.data
		.in_0_valid     (msi_to_gic_gen_0_csr_agent_rdata_fifo_out_valid),         //         .valid
		.in_0_ready     (msi_to_gic_gen_0_csr_agent_rdata_fifo_out_ready),         //         .ready
		.out_0_data     (avalon_st_adapter_003_out_0_data),                        //    out_0.data
		.out_0_valid    (avalon_st_adapter_003_out_0_valid),                       //         .valid
		.out_0_ready    (avalon_st_adapter_003_out_0_ready),                       //         .ready
		.out_0_error    (avalon_st_adapter_003_out_0_error)                        //         .error
	);

	soc_system_pcie_0_mm_interconnect_1_avalon_st_adapter_004 #(
		.inBitsPerSymbol (130),
		.inUsePackets    (0),
		.inDataWidth     (130),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (130),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_004 (
		.in_clk_0_clk   (custom_reset_synchronizer_0_clock_out_clk),            // in_clk_0.clk
		.in_rst_0_reset (pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset),      // in_rst_0.reset
		.in_0_data      (msgdma_0_descriptor_slave_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (msgdma_0_descriptor_slave_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (msgdma_0_descriptor_slave_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_004_out_0_data),                     //    out_0.data
		.out_0_valid    (avalon_st_adapter_004_out_0_valid),                    //         .valid
		.out_0_ready    (avalon_st_adapter_004_out_0_ready),                    //         .ready
		.out_0_error    (avalon_st_adapter_004_out_0_error)                     //         .error
	);

	soc_system_mm_interconnect_2_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_005 (
		.in_clk_0_clk   (clk_clk_clk),                                              // in_clk_0.clk
		.in_rst_0_reset (performance_counter_0_reset_reset_bridge_in_reset_reset),  // in_rst_0.reset
		.in_0_data      (msi_to_gic_gen_0_vector_slave_agent_rdata_fifo_out_data),  //     in_0.data
		.in_0_valid     (msi_to_gic_gen_0_vector_slave_agent_rdata_fifo_out_valid), //         .valid
		.in_0_ready     (msi_to_gic_gen_0_vector_slave_agent_rdata_fifo_out_ready), //         .ready
		.out_0_data     (avalon_st_adapter_005_out_0_data),                         //    out_0.data
		.out_0_valid    (avalon_st_adapter_005_out_0_valid),                        //         .valid
		.out_0_ready    (avalon_st_adapter_005_out_0_ready),                        //         .ready
		.out_0_error    (avalon_st_adapter_005_out_0_error)                         //         .error
	);

endmodule
