datasheet for subsys_pcie

subsys_pcie |

2020.06.26.14:46:07 | Datasheet

Overview

clk | subsys_pcie
coreclk_fanout

All Components
add_x_f2sdram altera_address_span_extender 18.1
alt_xcvr_reconfig_0 alt_xcvr_reconfig 18.1
ccb_h2f altera_avalon_mm_clock_crossing_bridge 18.1
msgdma_0 altera_msgdma 18.1
msi_to_gic_gen_0 altera_msi_to_gic_gen 1.0
pb_2_ocm altera_avalon_mm_bridge 18.1
pb_f2sdram altera_avalon_mm_bridge 18.1
pb_lwh2f_pcie altera_avalon_mm_bridge 18.1
pb_msgdma_2_txs altera_avalon_mm_bridge 18.1
pb_rxm_2_msi altera_avalon_mm_bridge 18.1
pcie_hip_avmm altera_pcie_cv_hip_avmm 18.1
performance_counter_0 altera_avalon_performance_counter 18.1
Memory Map

| msgdma_0 | pcie_hip_avmm
mm_read | mm_write | RP_Master
alt_xcvr_reconfig_0 |  |  |
reconfig_mgmt |  |  |
msgdma_0 |  |  |
csr |  |  |
descriptor_slave |  |  |
msi_to_gic_gen_0 |  |  |
csr |  |  |
vector_slave |  |  | 0xff214000
pcie_hip_avmm |  |  |
Txs | 0xd0000000 | 0xd0000000 |
Cra |  |  |
performance_counter_0 |  |  |
control_slave |  |  |

## add_x_f2sdram

altera_address_span_extender v18.1

pb_f2sdram | m0 | add_x_f2sdram
windowed_slave
custom_reset_synchronizer_0 | clock_out
clock
reset_out
reset

## Parameters

DATA_WIDTH | 256
BYTEENABLE_WIDTH | 32
DATA_WORD_WIDTH | 32
MASTER_ADDRESS_WIDTH | 32
MASTER_ADDRESS_SPAN | 4 gigabytes
SLAVE_ADDRESS_WIDTH | 25
SLAVE_ADDRESS_SPAN | 1 gigabytes
SLAVE_ADDRESS_SHIFT | 5
BURSTCOUNT_WIDTH | 8
MAX_BURST_WORDS | 128
MAX_BURST_BYTES | 4096
CNTL_ADDRESS_WIDTH | 1
SUB_WINDOW_COUNT | 1
MASTER_ADDRESS_DEF | 0
ENABLE_SLAVE_PORT | false
SUB_WINDOW_SPAN | 1 gigabytes
MAX_PENDING_READS | 16
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BURSTCOUNT_WIDTH | 8
BYTEENABLE_WIDTH | 32
CNTL_ADDRESS_WIDTH | 1
DATA_WIDTH | 256
MASTER_ADDRESS_WIDTH | 32
MAX_BURST_BYTES | 4096
MAX_BURST_WORDS | 128
SLAVE_ADDRESS_SHIFT | 5
SLAVE_ADDRESS_WIDTH | 25
SUB_WINDOW_COUNT | 1

## alt_xcvr_reconfig_0

alt_xcvr_reconfig v18.1

custom_reset_synchronizer_0 | clock_out | alt_xcvr_reconfig_0
mgmt_clk_clk
reset_out
mgmt_rst_reset
pcie_hip_avmm | reconfig_busy
reconfig_busy
|  | reconfig_from_xcvr | pcie_hip_avmm
|  | reconfig_from_xcvr
|  | reconfig_to_xcvr
|  | reconfig_to_xcvr

## Parameters

device_family | CYCLONEV
number_of_reconfig_interfaces | 2
gui_split_sizes |
enable_offset | 1
enable_lc | 0
enable_dcd | 0
enable_dcd_power_up | 1
enable_analog | 1
enable_eyemon | 0
ber_en | 0
enable_ber | 0
enable_dfe | 0
enable_adce | 0
enable_mif | 0
gui_enable_pll | 0
enable_pll | 0
gui_cal_status_port | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## ccb_h2f

altera_avalon_mm_clock_crossing_bridge v18.1

clk | clk | ccb_h2f
s0_clk
custom_reset_synchronizer_0 | clock_out
m0_clk
reset_out
m0_reset
reset_out
s0_reset
|  | m0 | pcie_hip_avmm
|  | Txs

## Parameters

DATA_WIDTH | 64
SYMBOL_WIDTH | 8
ADDRESS_WIDTH | 29
SYSINFO_ADDR_WIDTH | 28
USE_AUTO_ADDRESS_WIDTH | 1
AUTO_ADDRESS_WIDTH | 28
HDL_ADDR_WIDTH | 28
ADDRESS_UNITS | SYMBOLS
BURSTCOUNT_WIDTH | 7
MAX_BURST_SIZE | 64
COMMAND_FIFO_DEPTH | 4
RESPONSE_FIFO_DEPTH | 128
MASTER_SYNC_DEPTH | 2
SLAVE_SYNC_DEPTH | 2
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## clk

clock_source v18.1

## Parameters

clockFrequency | 50000000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## coreclk_fanout

clock_source v18.1

custom_reset_synchronizer_0 | clock_out | coreclk_fanout
clk_in
reset_out
clk_in_reset

## Parameters

clockFrequency | 125000000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | DEASSERT
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## coreclkout_125

altera_clock_bridge v18.1

custom_reset_synchronizer_0 | clock_out | coreclkout_125
in_clk

## Parameters

DERIVED_CLOCK_RATE | 0
EXPLICIT_CLOCK_RATE | 125000000
NUM_CLOCK_OUTPUTS | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## custom_reset_synchronizer_0

custom_reset_synchronizer v15.1

pcie_hip_avmm | coreclkout | custom_reset_synchronizer_0
clock_in
nreset_status
reset_in
clk | clk_reset
reset_in
|  | clock_out | pb_lwh2f_pcie
|  | clk
|  | reset_out
|  | reset
|  | clock_out | pb_rxm_2_msi
|  | clk
|  | reset_out
|  | reset
|  | clock_out | pb_msgdma_2_txs
|  | clk
|  | reset_out
|  | reset
|  | clock_out | pb_f2sdram
|  | clk
|  | reset_out
|  | reset
|  | clock_out | pb_2_ocm
|  | clk
|  | reset_out
|  | reset
|  | clock_out | nreset_status
|  | clk
|  | reset_out
|  | in_reset
|  | clock_out | coreclk_fanout
|  | clk_in
|  | reset_out
|  | clk_in_reset
|  | clock_out | msgdma_0
|  | clock
|  | reset_out
|  | reset_n
|  | clock_out | add_x_f2sdram
|  | clock
|  | reset_out
|  | reset
|  | clock_out | coreclkout_125
|  | in_clk
|  | clock_out | ccb_h2f
|  | m0_clk
|  | reset_out
|  | m0_reset
|  | reset_out
|  | s0_reset
|  | clock_out | alt_xcvr_reconfig_0
|  | mgmt_clk_clk
|  | reset_out
|  | mgmt_rst_reset
|  | reset_out | msi_to_gic_gen_0
|  | reset
|  | reset_out | performance_counter_0
|  | reset

## Parameters

INPUT_CLOCK_FREQUENCY | 125000000
INPUT_CLOCK_KNOWN | 1
DERIVED_CLOCK_RATE | 125000000
SYNC_DEPTH | 3
ADDITIONAL_DEPTH | 10
DISABLE_GLOBAL_NETWORK | 1
SYNC_BOTH_EDGES | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## msgdma_0

altera_msgdma v18.1

pb_lwh2f_pcie | m0 | msgdma_0
csr
m0
descriptor_slave
custom_reset_synchronizer_0 | clock_out
clock
reset_out
reset_n
|  | mm_read | pb_msgdma_2_txs
|  | s0
|  | mm_write
|  | s0
|  | mm_read | pb_2_ocm
|  | s0
|  | mm_write
|  | s0
|  | mm_read | pb_f2sdram
|  | s0
|  | mm_write
|  | s0

## Parameters

MODE | 0
DATA_WIDTH | 64
USE_FIX_ADDRESS_WIDTH | 0
FIX_ADDRESS_WIDTH | 32
EXPOSE_ST_PORT | 0
DATA_FIFO_DEPTH | 256
DESCRIPTOR_FIFO_DEPTH | 8
RESPONSE_PORT | 2
MAX_BYTE | 524288
TRANSFER_TYPE | Full Word Accesses Only
BURST_ENABLE | 1
MAX_BURST_COUNT | 64
BURST_WRAPPING_SUPPORT | 0
ENHANCED_FEATURES | 0
STRIDE_ENABLE | 0
MAX_STRIDE | 1
PROGRAMMABLE_BURST_ENABLE | 0
STRIDE_ENABLE_DERIVED | 0
PACKET_ENABLE | 0
PACKET_ENABLE_DERIVED | 0
ERROR_ENABLE | 0
ERROR_ENABLE_DERIVED | 0
ERROR_WIDTH | 8
CHANNEL_ENABLE | 0
CHANNEL_ENABLE_DERIVED | 0
CHANNEL_WIDTH | 8
PREFETCHER_ENABLE | 0
PREFETCHER_READ_BURST_ENABLE | 0
PREFETCHER_DATA_WIDTH | 32
PREFETCHER_MAX_READ_BURST_COUNT | 2
AUTO_DEVICE_FAMILY | CYCLONEV
AUTO_DEVICE | 5CSXFC6C6U23I7
AUTO_DEVICE_SPEEDGRADE | 7_H6
AUTO_MM_READ_ADDRESS_MAP | <address-map><slave name='add_x_f2sdram.windowed_slave' start='0x0' end='0x40000000' /><slave name='pb_2_ocm.s0' start='0x40000000' end='0x40000400' /><slave name='pcie_hip_avmm.Txs' start='0xD0000000' end='0xE0000000' /></address-map>
AUTO_MM_READ_ADDRESS_WIDTH | AddressWidth = 32
AUTO_MM_WRITE_ADDRESS_MAP | <address-map><slave name='add_x_f2sdram.windowed_slave' start='0x0' end='0x40000000' /><slave name='pb_2_ocm.s0' start='0x40000000' end='0x40000400' /><slave name='pcie_hip_avmm.Txs' start='0xD0000000' end='0xE0000000' /></address-map>
AUTO_MM_WRITE_ADDRESS_WIDTH | AddressWidth = 32
AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_MAP |
AUTO_DESCRIPTOR_READ_MASTER_ADDRESS_WIDTH | AddressWidth = -1
AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_MAP |
AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH | AddressWidth = -1
deviceFamily | Cyclone V
generateLegacySim | false

## Software Assignments

BURST_ENABLE | 1
BURST_WRAPPING_SUPPORT | 0
CHANNEL_ENABLE | 0
CHANNEL_ENABLE_DERIVED | 0
CHANNEL_WIDTH | 8
DATA_FIFO_DEPTH | 256
DATA_WIDTH | 64
DESCRIPTOR_FIFO_DEPTH | 8
DMA_MODE | 0
ENHANCED_FEATURES | 0
ERROR_ENABLE | 0
ERROR_ENABLE_DERIVED | 0
ERROR_WIDTH | 8
MAX_BURST_COUNT | 64
MAX_BYTE | 524288
MAX_STRIDE | 1
PACKET_ENABLE | 0
PACKET_ENABLE_DERIVED | 0
PREFETCHER_ENABLE | 0
PROGRAMMABLE_BURST_ENABLE | 0
RESPONSE_PORT | 2
STRIDE_ENABLE | 0
STRIDE_ENABLE_DERIVED | 0
TRANSFER_TYPE | Full Word Accesses Only

## msi_to_gic_gen_0

altera_msi_to_gic_gen v1.0

pb_lwh2f_pcie | m0 | msi_to_gic_gen_0
csr
m0
vector_slave
pb_rxm_2_msi | m0
vector_slave
clk | clk
clock
custom_reset_synchronizer_0 | reset_out
reset

## Parameters

DEVICE_FAMILY | CYCLONEV
MSG_DATA_WORD | 32
ADDR_WIDTH | 5
DATA_ENTRY_DEPTH | 4
FIFO_DEPTH | 4
MEMORY_TYPE | RAM_BLOCK_TYPE=MLAB
deviceFeaturesSystemInfo | ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## nreset_status

altera_reset_bridge v18.1

custom_reset_synchronizer_0 | clock_out | nreset_status
clk
reset_out
in_reset

## Parameters

ACTIVE_LOW_RESET | 1
SYNCHRONOUS_EDGES | deassert
NUM_RESET_OUTPUTS | 1
USE_RESET_REQUEST | 0
AUTO_CLK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## pb_2_ocm

altera_avalon_mm_bridge v18.1

pcie_hip_avmm | RP_Master | pb_2_ocm
s0
msgdma_0 | mm_read
s0
mm_write
s0
custom_reset_synchronizer_0 | clock_out
clk
reset_out
reset

## Parameters

DATA_WIDTH | 64
SYMBOL_WIDTH | 8
ADDRESS_WIDTH | 10
SYSINFO_ADDR_WIDTH | 10
USE_AUTO_ADDRESS_WIDTH | 1
AUTO_ADDRESS_WIDTH | 10
HDL_ADDR_WIDTH | 10
ADDRESS_UNITS | SYMBOLS
BURSTCOUNT_WIDTH | 7
MAX_BURST_SIZE | 64
MAX_PENDING_RESPONSES | 4
LINEWRAPBURSTS | 0
PIPELINE_COMMAND | 1
PIPELINE_RESPONSE | 1
USE_RESPONSE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## pb_f2sdram

altera_avalon_mm_bridge v18.1

pcie_hip_avmm | RP_Master | pb_f2sdram
s0
msgdma_0 | mm_read
s0
mm_write
s0
custom_reset_synchronizer_0 | clock_out
clk
reset_out
reset
|  | m0 | add_x_f2sdram
|  | windowed_slave

## Parameters

DATA_WIDTH | 64
SYMBOL_WIDTH | 8
ADDRESS_WIDTH | 30
SYSINFO_ADDR_WIDTH | 30
USE_AUTO_ADDRESS_WIDTH | 0
AUTO_ADDRESS_WIDTH | 30
HDL_ADDR_WIDTH | 30
ADDRESS_UNITS | SYMBOLS
BURSTCOUNT_WIDTH | 7
MAX_BURST_SIZE | 64
MAX_PENDING_RESPONSES | 4
LINEWRAPBURSTS | 0
PIPELINE_COMMAND | 1
PIPELINE_RESPONSE | 1
USE_RESPONSE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## pb_lwh2f_pcie

altera_avalon_mm_bridge v18.1

custom_reset_synchronizer_0 | clock_out | pb_lwh2f_pcie
clk
reset_out
reset
|  | m0 | pcie_hip_avmm
|  | Cra
|  | m0 | performance_counter_0
|  | control_slave
|  | m0 | msgdma_0
|  | csr
|  | m0
|  | descriptor_slave
|  | m0 | msi_to_gic_gen_0
|  | csr
|  | m0
|  | vector_slave

## Parameters

DATA_WIDTH | 32
SYMBOL_WIDTH | 8
ADDRESS_WIDTH | 15
SYSINFO_ADDR_WIDTH | 15
USE_AUTO_ADDRESS_WIDTH | 0
AUTO_ADDRESS_WIDTH | 15
HDL_ADDR_WIDTH | 15
ADDRESS_UNITS | SYMBOLS
BURSTCOUNT_WIDTH | 1
MAX_BURST_SIZE | 1
MAX_PENDING_RESPONSES | 1
LINEWRAPBURSTS | 0
PIPELINE_COMMAND | 1
PIPELINE_RESPONSE | 1
USE_RESPONSE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## pb_msgdma_2_txs

altera_avalon_mm_bridge v18.1

msgdma_0 | mm_read | pb_msgdma_2_txs
s0
mm_write
s0
custom_reset_synchronizer_0 | clock_out
clk
reset_out
reset
|  | m0 | pcie_hip_avmm
|  | Txs

## Parameters

DATA_WIDTH | 64
SYMBOL_WIDTH | 8
ADDRESS_WIDTH | 28
SYSINFO_ADDR_WIDTH | 28
USE_AUTO_ADDRESS_WIDTH | 1
AUTO_ADDRESS_WIDTH | 28
HDL_ADDR_WIDTH | 28
ADDRESS_UNITS | SYMBOLS
BURSTCOUNT_WIDTH | 7
MAX_BURST_SIZE | 64
MAX_PENDING_RESPONSES | 4
LINEWRAPBURSTS | 0
PIPELINE_COMMAND | 1
PIPELINE_RESPONSE | 1
USE_RESPONSE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## pb_rxm_2_msi

altera_avalon_mm_bridge v18.1

pcie_hip_avmm | RP_Master | pb_rxm_2_msi
s0
custom_reset_synchronizer_0 | clock_out
clk
reset_out
reset
|  | m0 | msi_to_gic_gen_0
|  | vector_slave

## Parameters

DATA_WIDTH | 32
SYMBOL_WIDTH | 8
ADDRESS_WIDTH | 15
SYSINFO_ADDR_WIDTH | 15
USE_AUTO_ADDRESS_WIDTH | 1
AUTO_ADDRESS_WIDTH | 15
HDL_ADDR_WIDTH | 15
ADDRESS_UNITS | SYMBOLS
BURSTCOUNT_WIDTH | 1
MAX_BURST_SIZE | 1
MAX_PENDING_RESPONSES | 2
LINEWRAPBURSTS | 0
PIPELINE_COMMAND | 1
PIPELINE_RESPONSE | 1
USE_RESPONSE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## pcie_hip_avmm

altera_pcie_cv_hip_avmm v18.1

pb_lwh2f_pcie | m0 | pcie_hip_avmm
Cra
ccb_h2f | m0
Txs
pb_msgdma_2_txs | m0
Txs
alt_xcvr_reconfig_0 | reconfig_from_xcvr
reconfig_from_xcvr
reconfig_to_xcvr
reconfig_to_xcvr
|  | RP_Master | pb_rxm_2_msi
|  | s0
|  | RP_Master | pb_2_ocm
|  | s0
|  | RP_Master | pb_f2sdram
|  | s0
|  | coreclkout | custom_reset_synchronizer_0
|  | clock_in
|  | nreset_status
|  | reset_in
|  | reconfig_busy | alt_xcvr_reconfig_0
|  | reconfig_busy

## Parameters

INTENDED_DEVICE_FAMILY | CYCLONEV
pcie_qsys | 1
altpcie_avmm_hwtcl | 1
lane_mask_hwtcl | x1
gen123_lane_rate_mode_hwtcl | Gen1 (2.5 Gbps)
port_type_hwtcl | Root port
pcie_spec_version_hwtcl | 2.1
rxbuffer_rxreq_hwtcl | Balanced
pll_refclk_freq_hwtcl | 100 MHz
set_pld_clk_x1_625MHz_hwtcl | 0
in_cvp_mode_hwtcl | 0
SLAVE_ADDRESS_MAP_0 | 0
SLAVE_ADDRESS_MAP_1 | 0
SLAVE_ADDRESS_MAP_2 | 0
SLAVE_ADDRESS_MAP_3 | 0
SLAVE_ADDRESS_MAP_4 | 0
SLAVE_ADDRESS_MAP_5 | 0
NUM_PREFETCH_MASTERS | 1
bar0_type_hwtcl | 0
bar0_size_mask_hwtcl | 32
bar0_io_space_hwtcl | Disabled
bar0_64bit_mem_space_hwtcl | Disabled
bar0_prefetchable_hwtcl | Disabled
bar1_type_hwtcl | 0
bar1_size_mask_hwtcl | 0
bar1_io_space_hwtcl | Disabled
bar1_prefetchable_hwtcl | Disabled
bar2_type_hwtcl | 0
bar2_size_mask_hwtcl | 0
bar2_io_space_hwtcl | Disabled
bar2_64bit_mem_space_hwtcl | Disabled
bar2_prefetchable_hwtcl | Disabled
bar3_type_hwtcl | 0
bar3_size_mask_hwtcl | 0
bar3_io_space_hwtcl | Disabled
bar3_prefetchable_hwtcl | Disabled
bar4_type_hwtcl | 0
bar4_size_mask_hwtcl | 0
bar4_io_space_hwtcl | Disabled
bar4_64bit_mem_space_hwtcl | Disabled
bar4_prefetchable_hwtcl | Disabled
bar5_type_hwtcl | 0
bar5_size_mask_hwtcl | 0
bar5_io_space_hwtcl | Disabled
bar5_prefetchable_hwtcl | Disabled
CB_P2A_AVALON_ADDR_B0 | 0x00000000
CB_P2A_AVALON_ADDR_B1 | 0x00000000
CB_P2A_AVALON_ADDR_B2 | 0x00000000
CB_P2A_AVALON_ADDR_B3 | 0x00000000
CB_P2A_AVALON_ADDR_B4 | 0x00000000
CB_P2A_AVALON_ADDR_B5 | 0x00000000
fixed_address_mode | 0
CB_P2A_FIXED_AVALON_ADDR_B0 | 0
CB_P2A_FIXED_AVALON_ADDR_B1 | 0
CB_P2A_FIXED_AVALON_ADDR_B2 | 0
CB_P2A_FIXED_AVALON_ADDR_B3 | 0
CB_P2A_FIXED_AVALON_ADDR_B4 | 0
CB_P2A_FIXED_AVALON_ADDR_B5 | 0
vendor_id_hwtcl | 4466
device_id_hwtcl | 57344
revision_id_hwtcl | 1
class_code_hwtcl | 394240
subsystem_vendor_id_hwtcl | 4466
subsystem_device_id_hwtcl | 57344
max_payload_size_hwtcl | 256
extend_tag_field_hwtcl | 32
completion_timeout_hwtcl | ABCD
enable_completion_timeout_disable_hwtcl | 1
use_aer_hwtcl | 0
ecrc_check_capable_hwtcl | 0
ecrc_gen_capable_hwtcl | 0
use_crc_forwarding_hwtcl | 0
port_link_number_hwtcl | 1
dll_active_report_support_hwtcl | 0
surprise_down_error_support_hwtcl | 0
slotclkcfg_hwtcl | 1
msi_multi_message_capable_hwtcl | 4
msi_64bit_addressing_capable_hwtcl | true
msi_masking_capable_hwtcl | false
msi_support_hwtcl | true
enable_function_msix_support_hwtcl | 0
msix_table_size_hwtcl | 0
msix_table_offset_hwtcl | 0
msix_table_bir_hwtcl | 0
msix_pba_offset_hwtcl | 0
msix_pba_bir_hwtcl | 0
enable_slot_register_hwtcl | 0
slot_power_scale_hwtcl | 0
slot_power_limit_hwtcl | 0
slot_number_hwtcl | 0
rx_ei_l0s_hwtcl | 0
endpoint_l0_latency_hwtcl | 0
endpoint_l1_latency_hwtcl | 0
vsec_id_hwtcl | 40960
vsec_rev_hwtcl | 0
user_id_hwtcl | 0
CG_COMMON_CLOCK_MODE | 1
avmm_width_hwtcl | 64
AVALON_ADDR_WIDTH | 32
avmm_burst_width_hwtcl | 7
CB_PCIE_MODE | 0
CB_PCIE_RX_LITE | 0
CB_RXM_DATA_WIDTH | 64
AST_LITE | 0
CG_RXM_IRQ_NUM | 16
CG_AVALON_S_ADDR_WIDTH | 28
bypass_tl | false
CG_IMPL_CRA_AV_SLAVE_PORT | 1
CG_ENABLE_ADVANCED_INTERRUPT | 0
CG_ENABLE_A2P_INTERRUPT | 0
CG_ENABLE_HIP_STATUS | 0
CG_ENABLE_HIP_STATUS_EXTENSION | 0
TX_S_ADDR_WIDTH | 32
CB_A2P_ADDR_MAP_IS_FIXED | 0
CB_A2P_ADDR_MAP_NUM_ENTRIES | 2
CB_A2P_ADDR_MAP_PASS_THRU_BITS | 27
BYPASSS_A2P_TRANSLATION | 0
CB_RP_S_ADDR_WIDTH | 32
a2p_pass_thru_bits | 27
CB_A2P_ADDR_MAP_FIXED_TABLE_0_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_0_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_1_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_1_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_2_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_2_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_3_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_3_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_4_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_4_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_5_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_5_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_6_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_6_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_7_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_7_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_8_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_8_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_9_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_9_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_10_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_10_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_11_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_11_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_12_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_12_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_13_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_13_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_14_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_14_LOW | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_15_HIGH | 0
CB_A2P_ADDR_MAP_FIXED_TABLE_15_LOW | 0
AddressPage | 0\,1\,2\,3\,4\,5\,6\,7\,8\,9\,10\,11\,12\,13\,14\,15
PCIeAddress63_32 | 0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000
PCIeAddress31_0 | 0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000\,0x00000000
RXM_DATA_WIDTH | 64
RXM_BEN_WIDTH | 8
ast_width_hwtcl | Avalon-ST 64-bit
use_rx_st_be_hwtcl | 0
use_ast_parity | 0
pld_clk_MHz | 1250
reconfig_to_xcvr_width | 140
hip_hard_reset_hwtcl | 1
force_hrc | 0
force_src | 0
reconfig_from_xcvr_width | 92
bypass_cdc_hwtcl | false
single_rx_detect_hwtcl | 1
wrong_device_id_hwtcl | disable
data_pack_rx_hwtcl | disable
ltssm_1ms_timeout_hwtcl | disable
ltssm_freqlocked_check_hwtcl | disable
deskew_comma_hwtcl | skp_eieos_deskw
maximum_current_hwtcl | 0
disable_snoop_packet_hwtcl | false
enable_l0s_aspm_hwtcl | true
extended_tag_reset_hwtcl | false
interrupt_pin_hwtcl | inta
bridge_port_vga_enable_hwtcl | false
bridge_port_ssid_support_hwtcl | false
ssvid_hwtcl | 0
ssid_hwtcl | 0
aspm_config_management_hwtcl | false
atomic_op_routing_hwtcl | false
atomic_op_completer_32bit_hwtcl | false
atomic_op_completer_64bit_hwtcl | false
cas_completer_128bit_hwtcl | false
ltr_mechanism_hwtcl | false
tph_completer_hwtcl | false
extended_format_field_hwtcl | true
atomic_malformed_hwtcl | true
flr_capability_hwtcl | 0
enable_adapter_half_rate_mode_hwtcl | false
skp_os_gen3_count_hwtcl | 0
millisecond_cycle_count_hwtcl | 124250
override_rxbuffer_cred_preset | 0
credit_buffer_allocation_aux_hwtcl | absolute
vc0_rx_flow_ctrl_posted_header_hwtcl | 18
vc0_rx_flow_ctrl_posted_data_hwtcl | 94
vc0_rx_flow_ctrl_nonposted_header_hwtcl | 32
vc0_rx_flow_ctrl_nonposted_data_hwtcl | 0
vc0_rx_flow_ctrl_compl_header_hwtcl | 0
vc0_rx_flow_ctrl_compl_data_hwtcl | 0
cpl_spc_header_hwtcl | 44
cpl_spc_data_hwtcl | 196
coreclkout_hip_phaseshift_hwtcl | 0 ps
pldclk_hip_phase_shift_hwtcl | 0 ps
port_width_be_hwtcl | 8
port_width_data_hwtcl | 64
serial_sim_hwtcl | 0
hip_reconfig_hwtcl | 0
gen3_rxfreqlock_counter_hwtcl | 0
gen3_skip_ph2_ph3_hwtcl | 0
g3_bypass_equlz_hwtcl | 0
expansion_base_address_register_hwtcl | 0
io_window_addr_width_hwtcl | 0
prefetchable_mem_window_addr_width_hwtcl | 0
advanced_default_parameter_override | 0
override_tbpartner_driver_setting_hwtcl | 0
bypass_clk_switch_hwtcl | disable
cvp_rate_sel_hwtcl | full_rate
cvp_data_compressed_hwtcl | false
cvp_data_encrypted_hwtcl | false
cvp_mode_reset_hwtcl | false
cvp_clk_reset_hwtcl | false
core_clk_sel_hwtcl | pld_clk
enable_rx_buffer_checking_hwtcl | false
disable_link_x2_support_hwtcl | false
device_number_hwtcl | 0
pipex1_debug_sel_hwtcl | disable
pclk_out_sel_hwtcl | pclk
no_soft_reset_hwtcl | false
d1_support_hwtcl | false
d2_support_hwtcl | false
d0_pme_hwtcl | false
d1_pme_hwtcl | false
d2_pme_hwtcl | false
d3_hot_pme_hwtcl | false
d3_cold_pme_hwtcl | false
low_priority_vc_hwtcl | single_vc
enable_l1_aspm_hwtcl | false
l1_exit_latency_sameclock_hwtcl | 0
l1_exit_latency_diffclock_hwtcl | 0
hot_plug_support_hwtcl | 0
no_command_completed_hwtcl | false
eie_before_nfts_count_hwtcl | 4
gen2_diffclock_nfts_count_hwtcl | 255
gen2_sameclock_nfts_count_hwtcl | 255
deemphasis_enable_hwtcl | false
l0_exit_latency_sameclock_hwtcl | 6
l0_exit_latency_diffclock_hwtcl | 6
vc0_clk_enable_hwtcl | true
register_pipe_signals_hwtcl | true
tx_cdc_almost_empty_hwtcl | 5
rx_l0s_count_idl_hwtcl | 0
cdc_dummy_insert_limit_hwtcl | 11
ei_delay_powerdown_count_hwtcl | 10
skp_os_schedule_count_hwtcl | 0
fc_init_timer_hwtcl | 1024
l01_entry_latency_hwtcl | 31
flow_control_update_count_hwtcl | 30
flow_control_timeout_count_hwtcl | 200
retry_buffer_last_active_address_hwtcl | 255
reserved_debug_hwtcl | 0
use_tl_cfg_sync_hwtcl | 1
diffclock_nfts_count_hwtcl | 255
sameclock_nfts_count_hwtcl | 255
l2_async_logic_hwtcl | disable
rx_cdc_almost_full_hwtcl | 12
tx_cdc_almost_full_hwtcl | 11
indicator_hwtcl | 0
enable_rx_buffer_checking_advanced_default_hwtcl | false
disable_link_x2_support_advanced_default_hwtcl | false
device_number_advanced_default_hwtcl | 0
pipex1_debug_sel_advanced_default_hwtcl | disable
pclk_out_sel_advanced_default_hwtcl | pclk
no_soft_reset_advanced_default_hwtcl | false
d1_support_advanced_default_hwtcl | false
d2_support_advanced_default_hwtcl | false
d0_pme_advanced_default_hwtcl | false
d1_pme_advanced_default_hwtcl | false
d2_pme_advanced_default_hwtcl | false
d3_hot_pme_advanced_default_hwtcl | false
d3_cold_pme_advanced_default_hwtcl | false
low_priority_vc_advanced_default_hwtcl | single_vc
enable_l1_aspm_advanced_default_hwtcl | false
l1_exit_latency_sameclock_advanced_default_hwtcl | 0
l1_exit_latency_diffclock_advanced_default_hwtcl | 0
hot_plug_support_advanced_default_hwtcl | 0
no_command_completed_advanced_default_hwtcl | false
eie_before_nfts_count_advanced_default_hwtcl | 4
gen2_diffclock_nfts_count_advanced_default_hwtcl | 255
gen2_sameclock_nfts_count_advanced_default_hwtcl | 255
deemphasis_enable_advanced_default_hwtcl | false
l0_exit_latency_sameclock_advanced_default_hwtcl | 6
l0_exit_latency_diffclock_advanced_default_hwtcl | 6
vc0_clk_enable_advanced_default_hwtcl | true
register_pipe_signals_advanced_default_hwtcl | true
tx_cdc_almost_empty_advanced_default_hwtcl | 5
rx_l0s_count_idl_advanced_default_hwtcl | 0
cdc_dummy_insert_limit_advanced_default_hwtcl | 11
ei_delay_powerdown_count_advanced_default_hwtcl | 10
skp_os_schedule_count_advanced_default_hwtcl | 0
fc_init_timer_advanced_default_hwtcl | 1024
l01_entry_latency_advanced_default_hwtcl | 31
flow_control_update_count_advanced_default_hwtcl | 30
flow_control_timeout_count_advanced_default_hwtcl | 200
retry_buffer_last_active_address_advanced_default_hwtcl | 255
reserved_debug_advanced_default_hwtcl | 0
use_tl_cfg_sync_advanced_default_hwtcl | 1
diffclock_nfts_count_advanced_default_hwtcl | 255
sameclock_nfts_count_advanced_default_hwtcl | 255
l2_async_logic_advanced_default_hwtcl | disable
rx_cdc_almost_full_advanced_default_hwtcl | 12
tx_cdc_almost_full_advanced_default_hwtcl | 11
indicator_advanced_default_hwtcl | 0
rpre_emph_a_val_hwtcl | 11
rpre_emph_b_val_hwtcl | 0
rpre_emph_c_val_hwtcl | 22
rpre_emph_d_val_hwtcl | 12
rpre_emph_e_val_hwtcl | 21
rvod_sel_a_val_hwtcl | 50
rvod_sel_b_val_hwtcl | 34
rvod_sel_c_val_hwtcl | 50
rvod_sel_d_val_hwtcl | 50
rvod_sel_e_val_hwtcl | 9
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## performance_counter_0

altera_avalon_performance_counter v18.1

pb_lwh2f_pcie | m0 | performance_counter_0
control_slave
clk | clk
clk
custom_reset_synchronizer_0 | reset_out
reset

## Parameters

numberOfSections | 1
control_slave_address_width | 3
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

HOW_MANY_SECTIONS | 1

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