// soc_system_mm_interconnect_0.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 18.1 646

`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_0 (
		input  wire         pcie_0_coreclk_fanout_clk_clk,                                                               //                                                             pcie_0_coreclk_fanout_clk.clk
		input  wire         pcie_0_coreclkout_out_clk,                                                                   //                                                                 pcie_0_coreclkout_out.clk
		input  wire         mm_clock_crossing_bridge_0_s0_reset_reset_bridge_in_reset_reset,                             //                             mm_clock_crossing_bridge_0_s0_reset_reset_bridge_in_reset.reset
		input  wire         pcie_0_address_span_extender_0_expanded_master_translator_reset_reset_bridge_in_reset_reset, // pcie_0_address_span_extender_0_expanded_master_translator_reset_reset_bridge_in_reset.reset
		input  wire         pcie_0_reset_reset_bridge_in_reset_reset,                                                    //                                                    pcie_0_reset_reset_bridge_in_reset.reset
		input  wire [31:0]  pcie_0_address_span_extender_0_expanded_master_address,                                      //                                        pcie_0_address_span_extender_0_expanded_master.address
		output wire         pcie_0_address_span_extender_0_expanded_master_waitrequest,                                  //                                                                                      .waitrequest
		input  wire [7:0]   pcie_0_address_span_extender_0_expanded_master_burstcount,                                   //                                                                                      .burstcount
		input  wire [31:0]  pcie_0_address_span_extender_0_expanded_master_byteenable,                                   //                                                                                      .byteenable
		input  wire         pcie_0_address_span_extender_0_expanded_master_read,                                         //                                                                                      .read
		output wire [255:0] pcie_0_address_span_extender_0_expanded_master_readdata,                                     //                                                                                      .readdata
		output wire         pcie_0_address_span_extender_0_expanded_master_readdatavalid,                                //                                                                                      .readdatavalid
		input  wire         pcie_0_address_span_extender_0_expanded_master_write,                                        //                                                                                      .write
		input  wire [255:0] pcie_0_address_span_extender_0_expanded_master_writedata,                                    //                                                                                      .writedata
		output wire [31:0]  mm_clock_crossing_bridge_0_s0_address,                                                       //                                                         mm_clock_crossing_bridge_0_s0.address
		output wire         mm_clock_crossing_bridge_0_s0_write,                                                         //                                                                                      .write
		output wire         mm_clock_crossing_bridge_0_s0_read,                                                          //                                                                                      .read
		input  wire [255:0] mm_clock_crossing_bridge_0_s0_readdata,                                                      //                                                                                      .readdata
		output wire [255:0] mm_clock_crossing_bridge_0_s0_writedata,                                                     //                                                                                      .writedata
		output wire [4:0]   mm_clock_crossing_bridge_0_s0_burstcount,                                                    //                                                                                      .burstcount
		output wire [31:0]  mm_clock_crossing_bridge_0_s0_byteenable,                                                    //                                                                                      .byteenable
		input  wire         mm_clock_crossing_bridge_0_s0_readdatavalid,                                                 //                                                                                      .readdatavalid
		input  wire         mm_clock_crossing_bridge_0_s0_waitrequest,                                                   //                                                                                      .waitrequest
		output wire         mm_clock_crossing_bridge_0_s0_debugaccess                                                    //                                                                                      .debugaccess
	);

	wire          pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest;   // pcie_0_address_span_extender_0_expanded_master_agent:av_waitrequest -> pcie_0_address_span_extender_0_expanded_master_translator:uav_waitrequest
	wire  [255:0] pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata;      // pcie_0_address_span_extender_0_expanded_master_agent:av_readdata -> pcie_0_address_span_extender_0_expanded_master_translator:uav_readdata
	wire          pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess;   // pcie_0_address_span_extender_0_expanded_master_translator:uav_debugaccess -> pcie_0_address_span_extender_0_expanded_master_agent:av_debugaccess
	wire   [31:0] pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address;       // pcie_0_address_span_extender_0_expanded_master_translator:uav_address -> pcie_0_address_span_extender_0_expanded_master_agent:av_address
	wire          pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read;          // pcie_0_address_span_extender_0_expanded_master_translator:uav_read -> pcie_0_address_span_extender_0_expanded_master_agent:av_read
	wire   [31:0] pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable;    // pcie_0_address_span_extender_0_expanded_master_translator:uav_byteenable -> pcie_0_address_span_extender_0_expanded_master_agent:av_byteenable
	wire          pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid; // pcie_0_address_span_extender_0_expanded_master_agent:av_readdatavalid -> pcie_0_address_span_extender_0_expanded_master_translator:uav_readdatavalid
	wire          pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock;          // pcie_0_address_span_extender_0_expanded_master_translator:uav_lock -> pcie_0_address_span_extender_0_expanded_master_agent:av_lock
	wire          pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write;         // pcie_0_address_span_extender_0_expanded_master_translator:uav_write -> pcie_0_address_span_extender_0_expanded_master_agent:av_write
	wire  [255:0] pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata;     // pcie_0_address_span_extender_0_expanded_master_translator:uav_writedata -> pcie_0_address_span_extender_0_expanded_master_agent:av_writedata
	wire   [12:0] pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount;    // pcie_0_address_span_extender_0_expanded_master_translator:uav_burstcount -> pcie_0_address_span_extender_0_expanded_master_agent:av_burstcount
	wire          rsp_mux_src_valid;                                                                                 // rsp_mux:src_valid -> pcie_0_address_span_extender_0_expanded_master_agent:rp_valid
	wire  [363:0] rsp_mux_src_data;                                                                                  // rsp_mux:src_data -> pcie_0_address_span_extender_0_expanded_master_agent:rp_data
	wire          rsp_mux_src_ready;                                                                                 // pcie_0_address_span_extender_0_expanded_master_agent:rp_ready -> rsp_mux:src_ready
	wire    [0:0] rsp_mux_src_channel;                                                                               // rsp_mux:src_channel -> pcie_0_address_span_extender_0_expanded_master_agent:rp_channel
	wire          rsp_mux_src_startofpacket;                                                                         // rsp_mux:src_startofpacket -> pcie_0_address_span_extender_0_expanded_master_agent:rp_startofpacket
	wire          rsp_mux_src_endofpacket;                                                                           // rsp_mux:src_endofpacket -> pcie_0_address_span_extender_0_expanded_master_agent:rp_endofpacket
	wire  [255:0] mm_clock_crossing_bridge_0_s0_agent_m0_readdata;                                                   // mm_clock_crossing_bridge_0_s0_translator:uav_readdata -> mm_clock_crossing_bridge_0_s0_agent:m0_readdata
	wire          mm_clock_crossing_bridge_0_s0_agent_m0_waitrequest;                                                // mm_clock_crossing_bridge_0_s0_translator:uav_waitrequest -> mm_clock_crossing_bridge_0_s0_agent:m0_waitrequest
	wire          mm_clock_crossing_bridge_0_s0_agent_m0_debugaccess;                                                // mm_clock_crossing_bridge_0_s0_agent:m0_debugaccess -> mm_clock_crossing_bridge_0_s0_translator:uav_debugaccess
	wire   [31:0] mm_clock_crossing_bridge_0_s0_agent_m0_address;                                                    // mm_clock_crossing_bridge_0_s0_agent:m0_address -> mm_clock_crossing_bridge_0_s0_translator:uav_address
	wire   [31:0] mm_clock_crossing_bridge_0_s0_agent_m0_byteenable;                                                 // mm_clock_crossing_bridge_0_s0_agent:m0_byteenable -> mm_clock_crossing_bridge_0_s0_translator:uav_byteenable
	wire          mm_clock_crossing_bridge_0_s0_agent_m0_read;                                                       // mm_clock_crossing_bridge_0_s0_agent:m0_read -> mm_clock_crossing_bridge_0_s0_translator:uav_read
	wire          mm_clock_crossing_bridge_0_s0_agent_m0_readdatavalid;                                              // mm_clock_crossing_bridge_0_s0_translator:uav_readdatavalid -> mm_clock_crossing_bridge_0_s0_agent:m0_readdatavalid
	wire          mm_clock_crossing_bridge_0_s0_agent_m0_lock;                                                       // mm_clock_crossing_bridge_0_s0_agent:m0_lock -> mm_clock_crossing_bridge_0_s0_translator:uav_lock
	wire  [255:0] mm_clock_crossing_bridge_0_s0_agent_m0_writedata;                                                  // mm_clock_crossing_bridge_0_s0_agent:m0_writedata -> mm_clock_crossing_bridge_0_s0_translator:uav_writedata
	wire          mm_clock_crossing_bridge_0_s0_agent_m0_write;                                                      // mm_clock_crossing_bridge_0_s0_agent:m0_write -> mm_clock_crossing_bridge_0_s0_translator:uav_write
	wire    [9:0] mm_clock_crossing_bridge_0_s0_agent_m0_burstcount;                                                 // mm_clock_crossing_bridge_0_s0_agent:m0_burstcount -> mm_clock_crossing_bridge_0_s0_translator:uav_burstcount
	wire          mm_clock_crossing_bridge_0_s0_agent_rf_source_valid;                                               // mm_clock_crossing_bridge_0_s0_agent:rf_source_valid -> mm_clock_crossing_bridge_0_s0_agent_rsp_fifo:in_valid
	wire  [364:0] mm_clock_crossing_bridge_0_s0_agent_rf_source_data;                                                // mm_clock_crossing_bridge_0_s0_agent:rf_source_data -> mm_clock_crossing_bridge_0_s0_agent_rsp_fifo:in_data
	wire          mm_clock_crossing_bridge_0_s0_agent_rf_source_ready;                                               // mm_clock_crossing_bridge_0_s0_agent_rsp_fifo:in_ready -> mm_clock_crossing_bridge_0_s0_agent:rf_source_ready
	wire          mm_clock_crossing_bridge_0_s0_agent_rf_source_startofpacket;                                       // mm_clock_crossing_bridge_0_s0_agent:rf_source_startofpacket -> mm_clock_crossing_bridge_0_s0_agent_rsp_fifo:in_startofpacket
	wire          mm_clock_crossing_bridge_0_s0_agent_rf_source_endofpacket;                                         // mm_clock_crossing_bridge_0_s0_agent:rf_source_endofpacket -> mm_clock_crossing_bridge_0_s0_agent_rsp_fifo:in_endofpacket
	wire          mm_clock_crossing_bridge_0_s0_agent_rsp_fifo_out_valid;                                            // mm_clock_crossing_bridge_0_s0_agent_rsp_fifo:out_valid -> mm_clock_crossing_bridge_0_s0_agent:rf_sink_valid
	wire  [364:0] mm_clock_crossing_bridge_0_s0_agent_rsp_fifo_out_data;                                             // mm_clock_crossing_bridge_0_s0_agent_rsp_fifo:out_data -> mm_clock_crossing_bridge_0_s0_agent:rf_sink_data
	wire          mm_clock_crossing_bridge_0_s0_agent_rsp_fifo_out_ready;                                            // mm_clock_crossing_bridge_0_s0_agent:rf_sink_ready -> mm_clock_crossing_bridge_0_s0_agent_rsp_fifo:out_ready
	wire          mm_clock_crossing_bridge_0_s0_agent_rsp_fifo_out_startofpacket;                                    // mm_clock_crossing_bridge_0_s0_agent_rsp_fifo:out_startofpacket -> mm_clock_crossing_bridge_0_s0_agent:rf_sink_startofpacket
	wire          mm_clock_crossing_bridge_0_s0_agent_rsp_fifo_out_endofpacket;                                      // mm_clock_crossing_bridge_0_s0_agent_rsp_fifo:out_endofpacket -> mm_clock_crossing_bridge_0_s0_agent:rf_sink_endofpacket
	wire          mm_clock_crossing_bridge_0_s0_agent_rdata_fifo_src_valid;                                          // mm_clock_crossing_bridge_0_s0_agent:rdata_fifo_src_valid -> mm_clock_crossing_bridge_0_s0_agent_rdata_fifo:in_valid
	wire  [257:0] mm_clock_crossing_bridge_0_s0_agent_rdata_fifo_src_data;                                           // mm_clock_crossing_bridge_0_s0_agent:rdata_fifo_src_data -> mm_clock_crossing_bridge_0_s0_agent_rdata_fifo:in_data
	wire          mm_clock_crossing_bridge_0_s0_agent_rdata_fifo_src_ready;                                          // mm_clock_crossing_bridge_0_s0_agent_rdata_fifo:in_ready -> mm_clock_crossing_bridge_0_s0_agent:rdata_fifo_src_ready
	wire          pcie_0_address_span_extender_0_expanded_master_agent_cp_valid;                                     // pcie_0_address_span_extender_0_expanded_master_agent:cp_valid -> router:sink_valid
	wire  [363:0] pcie_0_address_span_extender_0_expanded_master_agent_cp_data;                                      // pcie_0_address_span_extender_0_expanded_master_agent:cp_data -> router:sink_data
	wire          pcie_0_address_span_extender_0_expanded_master_agent_cp_ready;                                     // router:sink_ready -> pcie_0_address_span_extender_0_expanded_master_agent:cp_ready
	wire          pcie_0_address_span_extender_0_expanded_master_agent_cp_startofpacket;                             // pcie_0_address_span_extender_0_expanded_master_agent:cp_startofpacket -> router:sink_startofpacket
	wire          pcie_0_address_span_extender_0_expanded_master_agent_cp_endofpacket;                               // pcie_0_address_span_extender_0_expanded_master_agent:cp_endofpacket -> router:sink_endofpacket
	wire          router_src_valid;                                                                                  // router:src_valid -> cmd_demux:sink_valid
	wire  [363:0] router_src_data;                                                                                   // router:src_data -> cmd_demux:sink_data
	wire          router_src_ready;                                                                                  // cmd_demux:sink_ready -> router:src_ready
	wire    [0:0] router_src_channel;                                                                                // router:src_channel -> cmd_demux:sink_channel
	wire          router_src_startofpacket;                                                                          // router:src_startofpacket -> cmd_demux:sink_startofpacket
	wire          router_src_endofpacket;                                                                            // router:src_endofpacket -> cmd_demux:sink_endofpacket
	wire          mm_clock_crossing_bridge_0_s0_agent_rp_valid;                                                      // mm_clock_crossing_bridge_0_s0_agent:rp_valid -> router_001:sink_valid
	wire  [363:0] mm_clock_crossing_bridge_0_s0_agent_rp_data;                                                       // mm_clock_crossing_bridge_0_s0_agent:rp_data -> router_001:sink_data
	wire          mm_clock_crossing_bridge_0_s0_agent_rp_ready;                                                      // router_001:sink_ready -> mm_clock_crossing_bridge_0_s0_agent:rp_ready
	wire          mm_clock_crossing_bridge_0_s0_agent_rp_startofpacket;                                              // mm_clock_crossing_bridge_0_s0_agent:rp_startofpacket -> router_001:sink_startofpacket
	wire          mm_clock_crossing_bridge_0_s0_agent_rp_endofpacket;                                                // mm_clock_crossing_bridge_0_s0_agent:rp_endofpacket -> router_001:sink_endofpacket
	wire          router_001_src_valid;                                                                              // router_001:src_valid -> rsp_demux:sink_valid
	wire  [363:0] router_001_src_data;                                                                               // router_001:src_data -> rsp_demux:sink_data
	wire          router_001_src_ready;                                                                              // rsp_demux:sink_ready -> router_001:src_ready
	wire    [0:0] router_001_src_channel;                                                                            // router_001:src_channel -> rsp_demux:sink_channel
	wire          router_001_src_startofpacket;                                                                      // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_001_src_endofpacket;                                                                        // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          cmd_mux_src_valid;                                                                                 // cmd_mux:src_valid -> mm_clock_crossing_bridge_0_s0_burst_adapter:sink0_valid
	wire  [363:0] cmd_mux_src_data;                                                                                  // cmd_mux:src_data -> mm_clock_crossing_bridge_0_s0_burst_adapter:sink0_data
	wire          cmd_mux_src_ready;                                                                                 // mm_clock_crossing_bridge_0_s0_burst_adapter:sink0_ready -> cmd_mux:src_ready
	wire    [0:0] cmd_mux_src_channel;                                                                               // cmd_mux:src_channel -> mm_clock_crossing_bridge_0_s0_burst_adapter:sink0_channel
	wire          cmd_mux_src_startofpacket;                                                                         // cmd_mux:src_startofpacket -> mm_clock_crossing_bridge_0_s0_burst_adapter:sink0_startofpacket
	wire          cmd_mux_src_endofpacket;                                                                           // cmd_mux:src_endofpacket -> mm_clock_crossing_bridge_0_s0_burst_adapter:sink0_endofpacket
	wire          mm_clock_crossing_bridge_0_s0_burst_adapter_source0_valid;                                         // mm_clock_crossing_bridge_0_s0_burst_adapter:source0_valid -> mm_clock_crossing_bridge_0_s0_agent:cp_valid
	wire  [363:0] mm_clock_crossing_bridge_0_s0_burst_adapter_source0_data;                                          // mm_clock_crossing_bridge_0_s0_burst_adapter:source0_data -> mm_clock_crossing_bridge_0_s0_agent:cp_data
	wire          mm_clock_crossing_bridge_0_s0_burst_adapter_source0_ready;                                         // mm_clock_crossing_bridge_0_s0_agent:cp_ready -> mm_clock_crossing_bridge_0_s0_burst_adapter:source0_ready
	wire    [0:0] mm_clock_crossing_bridge_0_s0_burst_adapter_source0_channel;                                       // mm_clock_crossing_bridge_0_s0_burst_adapter:source0_channel -> mm_clock_crossing_bridge_0_s0_agent:cp_channel
	wire          mm_clock_crossing_bridge_0_s0_burst_adapter_source0_startofpacket;                                 // mm_clock_crossing_bridge_0_s0_burst_adapter:source0_startofpacket -> mm_clock_crossing_bridge_0_s0_agent:cp_startofpacket
	wire          mm_clock_crossing_bridge_0_s0_burst_adapter_source0_endofpacket;                                   // mm_clock_crossing_bridge_0_s0_burst_adapter:source0_endofpacket -> mm_clock_crossing_bridge_0_s0_agent:cp_endofpacket
	wire          cmd_demux_src0_valid;                                                                              // cmd_demux:src0_valid -> async_fifo:in_valid
	wire  [363:0] cmd_demux_src0_data;                                                                               // cmd_demux:src0_data -> async_fifo:in_data
	wire          cmd_demux_src0_ready;                                                                              // async_fifo:in_ready -> cmd_demux:src0_ready
	wire    [0:0] cmd_demux_src0_channel;                                                                            // cmd_demux:src0_channel -> async_fifo:in_channel
	wire          cmd_demux_src0_startofpacket;                                                                      // cmd_demux:src0_startofpacket -> async_fifo:in_startofpacket
	wire          cmd_demux_src0_endofpacket;                                                                        // cmd_demux:src0_endofpacket -> async_fifo:in_endofpacket
	wire          async_fifo_out_valid;                                                                              // async_fifo:out_valid -> cmd_mux:sink0_valid
	wire  [363:0] async_fifo_out_data;                                                                               // async_fifo:out_data -> cmd_mux:sink0_data
	wire          async_fifo_out_ready;                                                                              // cmd_mux:sink0_ready -> async_fifo:out_ready
	wire    [0:0] async_fifo_out_channel;                                                                            // async_fifo:out_channel -> cmd_mux:sink0_channel
	wire          async_fifo_out_startofpacket;                                                                      // async_fifo:out_startofpacket -> cmd_mux:sink0_startofpacket
	wire          async_fifo_out_endofpacket;                                                                        // async_fifo:out_endofpacket -> cmd_mux:sink0_endofpacket
	wire          rsp_demux_src0_valid;                                                                              // rsp_demux:src0_valid -> async_fifo_001:in_valid
	wire  [363:0] rsp_demux_src0_data;                                                                               // rsp_demux:src0_data -> async_fifo_001:in_data
	wire          rsp_demux_src0_ready;                                                                              // async_fifo_001:in_ready -> rsp_demux:src0_ready
	wire    [0:0] rsp_demux_src0_channel;                                                                            // rsp_demux:src0_channel -> async_fifo_001:in_channel
	wire          rsp_demux_src0_startofpacket;                                                                      // rsp_demux:src0_startofpacket -> async_fifo_001:in_startofpacket
	wire          rsp_demux_src0_endofpacket;                                                                        // rsp_demux:src0_endofpacket -> async_fifo_001:in_endofpacket
	wire          async_fifo_001_out_valid;                                                                          // async_fifo_001:out_valid -> rsp_mux:sink0_valid
	wire  [363:0] async_fifo_001_out_data;                                                                           // async_fifo_001:out_data -> rsp_mux:sink0_data
	wire          async_fifo_001_out_ready;                                                                          // rsp_mux:sink0_ready -> async_fifo_001:out_ready
	wire    [0:0] async_fifo_001_out_channel;                                                                        // async_fifo_001:out_channel -> rsp_mux:sink0_channel
	wire          async_fifo_001_out_startofpacket;                                                                  // async_fifo_001:out_startofpacket -> rsp_mux:sink0_startofpacket
	wire          async_fifo_001_out_endofpacket;                                                                    // async_fifo_001:out_endofpacket -> rsp_mux:sink0_endofpacket
	wire          mm_clock_crossing_bridge_0_s0_agent_rdata_fifo_out_valid;                                          // mm_clock_crossing_bridge_0_s0_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
	wire  [257:0] mm_clock_crossing_bridge_0_s0_agent_rdata_fifo_out_data;                                           // mm_clock_crossing_bridge_0_s0_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
	wire          mm_clock_crossing_bridge_0_s0_agent_rdata_fifo_out_ready;                                          // avalon_st_adapter:in_0_ready -> mm_clock_crossing_bridge_0_s0_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_out_0_valid;                                                                     // avalon_st_adapter:out_0_valid -> mm_clock_crossing_bridge_0_s0_agent:rdata_fifo_sink_valid
	wire  [257:0] avalon_st_adapter_out_0_data;                                                                      // avalon_st_adapter:out_0_data -> mm_clock_crossing_bridge_0_s0_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_out_0_ready;                                                                     // mm_clock_crossing_bridge_0_s0_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
	wire    [0:0] avalon_st_adapter_out_0_error;                                                                     // avalon_st_adapter:out_0_error -> mm_clock_crossing_bridge_0_s0_agent:rdata_fifo_sink_error

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (256),
		.AV_BURSTCOUNT_W             (8),
		.AV_BYTEENABLE_W             (32),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (13),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (32),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) pcie_0_address_span_extender_0_expanded_master_translator (
		.clk                    (pcie_0_coreclk_fanout_clk_clk),                                                                     //                       clk.clk
		.reset                  (pcie_0_address_span_extender_0_expanded_master_translator_reset_reset_bridge_in_reset_reset),       //                     reset.reset
		.uav_address            (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (pcie_0_address_span_extender_0_expanded_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (pcie_0_address_span_extender_0_expanded_master_waitrequest),                                        //                          .waitrequest
		.av_burstcount          (pcie_0_address_span_extender_0_expanded_master_burstcount),                                         //                          .burstcount
		.av_byteenable          (pcie_0_address_span_extender_0_expanded_master_byteenable),                                         //                          .byteenable
		.av_read                (pcie_0_address_span_extender_0_expanded_master_read),                                               //                          .read
		.av_readdata            (pcie_0_address_span_extender_0_expanded_master_readdata),                                           //                          .readdata
		.av_readdatavalid       (pcie_0_address_span_extender_0_expanded_master_readdatavalid),                                      //                          .readdatavalid
		.av_write               (pcie_0_address_span_extender_0_expanded_master_write),                                              //                          .write
		.av_writedata           (pcie_0_address_span_extender_0_expanded_master_writedata),                                          //                          .writedata
		.av_beginbursttransfer  (1'b0),                                                                                              //               (terminated)
		.av_begintransfer       (1'b0),                                                                                              //               (terminated)
		.av_chipselect          (1'b0),                                                                                              //               (terminated)
		.av_lock                (1'b0),                                                                                              //               (terminated)
		.av_debugaccess         (1'b0),                                                                                              //               (terminated)
		.uav_clken              (),                                                                                                  //               (terminated)
		.av_clken               (1'b1),                                                                                              //               (terminated)
		.uav_response           (2'b00),                                                                                             //               (terminated)
		.av_response            (),                                                                                                  //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                                              //               (terminated)
		.av_writeresponsevalid  ()                                                                                                   //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (32),
		.AV_DATA_W                      (256),
		.UAV_DATA_W                     (256),
		.AV_BURSTCOUNT_W                (5),
		.AV_BYTEENABLE_W                (32),
		.UAV_BYTEENABLE_W               (32),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (10),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (32),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) mm_clock_crossing_bridge_0_s0_translator (
		.clk                    (pcie_0_coreclkout_out_clk),                                       //                      clk.clk
		.reset                  (mm_clock_crossing_bridge_0_s0_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (mm_clock_crossing_bridge_0_s0_agent_m0_address),                  // avalon_universal_slave_0.address
		.uav_burstcount         (mm_clock_crossing_bridge_0_s0_agent_m0_burstcount),               //                         .burstcount
		.uav_read               (mm_clock_crossing_bridge_0_s0_agent_m0_read),                     //                         .read
		.uav_write              (mm_clock_crossing_bridge_0_s0_agent_m0_write),                    //                         .write
		.uav_waitrequest        (mm_clock_crossing_bridge_0_s0_agent_m0_waitrequest),              //                         .waitrequest
		.uav_readdatavalid      (mm_clock_crossing_bridge_0_s0_agent_m0_readdatavalid),            //                         .readdatavalid
		.uav_byteenable         (mm_clock_crossing_bridge_0_s0_agent_m0_byteenable),               //                         .byteenable
		.uav_readdata           (mm_clock_crossing_bridge_0_s0_agent_m0_readdata),                 //                         .readdata
		.uav_writedata          (mm_clock_crossing_bridge_0_s0_agent_m0_writedata),                //                         .writedata
		.uav_lock               (mm_clock_crossing_bridge_0_s0_agent_m0_lock),                     //                         .lock
		.uav_debugaccess        (mm_clock_crossing_bridge_0_s0_agent_m0_debugaccess),              //                         .debugaccess
		.av_address             (mm_clock_crossing_bridge_0_s0_address),                           //      avalon_anti_slave_0.address
		.av_write               (mm_clock_crossing_bridge_0_s0_write),                             //                         .write
		.av_read                (mm_clock_crossing_bridge_0_s0_read),                              //                         .read
		.av_readdata            (mm_clock_crossing_bridge_0_s0_readdata),                          //                         .readdata
		.av_writedata           (mm_clock_crossing_bridge_0_s0_writedata),                         //                         .writedata
		.av_burstcount          (mm_clock_crossing_bridge_0_s0_burstcount),                        //                         .burstcount
		.av_byteenable          (mm_clock_crossing_bridge_0_s0_byteenable),                        //                         .byteenable
		.av_readdatavalid       (mm_clock_crossing_bridge_0_s0_readdatavalid),                     //                         .readdatavalid
		.av_waitrequest         (mm_clock_crossing_bridge_0_s0_waitrequest),                       //                         .waitrequest
		.av_debugaccess         (mm_clock_crossing_bridge_0_s0_debugaccess),                       //                         .debugaccess
		.av_begintransfer       (),                                                                //              (terminated)
		.av_beginbursttransfer  (),                                                                //              (terminated)
		.av_writebyteenable     (),                                                                //              (terminated)
		.av_lock                (),                                                                //              (terminated)
		.av_chipselect          (),                                                                //              (terminated)
		.av_clken               (),                                                                //              (terminated)
		.uav_clken              (1'b0),                                                            //              (terminated)
		.av_outputenable        (),                                                                //              (terminated)
		.uav_response           (),                                                                //              (terminated)
		.av_response            (2'b00),                                                           //              (terminated)
		.uav_writeresponsevalid (),                                                                //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                             //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (363),
		.PKT_ORI_BURST_SIZE_L      (361),
		.PKT_RESPONSE_STATUS_H     (360),
		.PKT_RESPONSE_STATUS_L     (359),
		.PKT_QOS_H                 (348),
		.PKT_QOS_L                 (348),
		.PKT_DATA_SIDEBAND_H       (346),
		.PKT_DATA_SIDEBAND_L       (346),
		.PKT_ADDR_SIDEBAND_H       (345),
		.PKT_ADDR_SIDEBAND_L       (345),
		.PKT_BURST_TYPE_H          (344),
		.PKT_BURST_TYPE_L          (343),
		.PKT_CACHE_H               (358),
		.PKT_CACHE_L               (355),
		.PKT_THREAD_ID_H           (351),
		.PKT_THREAD_ID_L           (351),
		.PKT_BURST_SIZE_H          (342),
		.PKT_BURST_SIZE_L          (340),
		.PKT_TRANS_EXCLUSIVE       (325),
		.PKT_TRANS_LOCK            (324),
		.PKT_BEGIN_BURST           (347),
		.PKT_PROTECTION_H          (354),
		.PKT_PROTECTION_L          (352),
		.PKT_BURSTWRAP_H           (339),
		.PKT_BURSTWRAP_L           (339),
		.PKT_BYTE_CNT_H            (338),
		.PKT_BYTE_CNT_L            (326),
		.PKT_ADDR_H                (319),
		.PKT_ADDR_L                (288),
		.PKT_TRANS_COMPRESSED_READ (320),
		.PKT_TRANS_POSTED          (321),
		.PKT_TRANS_WRITE           (322),
		.PKT_TRANS_READ            (323),
		.PKT_DATA_H                (255),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (287),
		.PKT_BYTEEN_L              (256),
		.PKT_SRC_ID_H              (349),
		.PKT_SRC_ID_L              (349),
		.PKT_DEST_ID_H             (350),
		.PKT_DEST_ID_L             (350),
		.ST_DATA_W                 (364),
		.ST_CHANNEL_W              (1),
		.AV_BURSTCOUNT_W           (13),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) pcie_0_address_span_extender_0_expanded_master_agent (
		.clk                   (pcie_0_coreclk_fanout_clk_clk),                                                                     //       clk.clk
		.reset                 (pcie_0_address_span_extender_0_expanded_master_translator_reset_reset_bridge_in_reset_reset),       // clk_reset.reset
		.av_address            (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (pcie_0_address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (pcie_0_address_span_extender_0_expanded_master_agent_cp_valid),                                     //        cp.valid
		.cp_data               (pcie_0_address_span_extender_0_expanded_master_agent_cp_data),                                      //          .data
		.cp_startofpacket      (pcie_0_address_span_extender_0_expanded_master_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (pcie_0_address_span_extender_0_expanded_master_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (pcie_0_address_span_extender_0_expanded_master_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_src_valid),                                                                                 //        rp.valid
		.rp_data               (rsp_mux_src_data),                                                                                  //          .data
		.rp_channel            (rsp_mux_src_channel),                                                                               //          .channel
		.rp_startofpacket      (rsp_mux_src_startofpacket),                                                                         //          .startofpacket
		.rp_endofpacket        (rsp_mux_src_endofpacket),                                                                           //          .endofpacket
		.rp_ready              (rsp_mux_src_ready),                                                                                 //          .ready
		.av_response           (),                                                                                                  // (terminated)
		.av_writeresponsevalid ()                                                                                                   // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (363),
		.PKT_ORI_BURST_SIZE_L      (361),
		.PKT_RESPONSE_STATUS_H     (360),
		.PKT_RESPONSE_STATUS_L     (359),
		.PKT_BURST_SIZE_H          (342),
		.PKT_BURST_SIZE_L          (340),
		.PKT_TRANS_LOCK            (324),
		.PKT_BEGIN_BURST           (347),
		.PKT_PROTECTION_H          (354),
		.PKT_PROTECTION_L          (352),
		.PKT_BURSTWRAP_H           (339),
		.PKT_BURSTWRAP_L           (339),
		.PKT_BYTE_CNT_H            (338),
		.PKT_BYTE_CNT_L            (326),
		.PKT_ADDR_H                (319),
		.PKT_ADDR_L                (288),
		.PKT_TRANS_COMPRESSED_READ (320),
		.PKT_TRANS_POSTED          (321),
		.PKT_TRANS_WRITE           (322),
		.PKT_TRANS_READ            (323),
		.PKT_DATA_H                (255),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (287),
		.PKT_BYTEEN_L              (256),
		.PKT_SRC_ID_H              (349),
		.PKT_SRC_ID_L              (349),
		.PKT_DEST_ID_H             (350),
		.PKT_DEST_ID_L             (350),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (1),
		.ST_DATA_W                 (364),
		.AVS_BURSTCOUNT_W          (10),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) mm_clock_crossing_bridge_0_s0_agent (
		.clk                     (pcie_0_coreclkout_out_clk),                                         //             clk.clk
		.reset                   (mm_clock_crossing_bridge_0_s0_reset_reset_bridge_in_reset_reset),   //       clk_reset.reset
		.m0_address              (mm_clock_crossing_bridge_0_s0_agent_m0_address),                    //              m0.address
		.m0_burstcount           (mm_clock_crossing_bridge_0_s0_agent_m0_burstcount),                 //                .burstcount
		.m0_byteenable           (mm_clock_crossing_bridge_0_s0_agent_m0_byteenable),                 //                .byteenable
		.m0_debugaccess          (mm_clock_crossing_bridge_0_s0_agent_m0_debugaccess),                //                .debugaccess
		.m0_lock                 (mm_clock_crossing_bridge_0_s0_agent_m0_lock),                       //                .lock
		.m0_readdata             (mm_clock_crossing_bridge_0_s0_agent_m0_readdata),                   //                .readdata
		.m0_readdatavalid        (mm_clock_crossing_bridge_0_s0_agent_m0_readdatavalid),              //                .readdatavalid
		.m0_read                 (mm_clock_crossing_bridge_0_s0_agent_m0_read),                       //                .read
		.m0_waitrequest          (mm_clock_crossing_bridge_0_s0_agent_m0_waitrequest),                //                .waitrequest
		.m0_writedata            (mm_clock_crossing_bridge_0_s0_agent_m0_writedata),                  //                .writedata
		.m0_write                (mm_clock_crossing_bridge_0_s0_agent_m0_write),                      //                .write
		.rp_endofpacket          (mm_clock_crossing_bridge_0_s0_agent_rp_endofpacket),                //              rp.endofpacket
		.rp_ready                (mm_clock_crossing_bridge_0_s0_agent_rp_ready),                      //                .ready
		.rp_valid                (mm_clock_crossing_bridge_0_s0_agent_rp_valid),                      //                .valid
		.rp_data                 (mm_clock_crossing_bridge_0_s0_agent_rp_data),                       //                .data
		.rp_startofpacket        (mm_clock_crossing_bridge_0_s0_agent_rp_startofpacket),              //                .startofpacket
		.cp_ready                (mm_clock_crossing_bridge_0_s0_burst_adapter_source0_ready),         //              cp.ready
		.cp_valid                (mm_clock_crossing_bridge_0_s0_burst_adapter_source0_valid),         //                .valid
		.cp_data                 (mm_clock_crossing_bridge_0_s0_burst_adapter_source0_data),          //                .data
		.cp_startofpacket        (mm_clock_crossing_bridge_0_s0_burst_adapter_source0_startofpacket), //                .startofpacket
		.cp_endofpacket          (mm_clock_crossing_bridge_0_s0_burst_adapter_source0_endofpacket),   //                .endofpacket
		.cp_channel              (mm_clock_crossing_bridge_0_s0_burst_adapter_source0_channel),       //                .channel
		.rf_sink_ready           (mm_clock_crossing_bridge_0_s0_agent_rsp_fifo_out_ready),            //         rf_sink.ready
		.rf_sink_valid           (mm_clock_crossing_bridge_0_s0_agent_rsp_fifo_out_valid),            //                .valid
		.rf_sink_startofpacket   (mm_clock_crossing_bridge_0_s0_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
		.rf_sink_endofpacket     (mm_clock_crossing_bridge_0_s0_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
		.rf_sink_data            (mm_clock_crossing_bridge_0_s0_agent_rsp_fifo_out_data),             //                .data
		.rf_source_ready         (mm_clock_crossing_bridge_0_s0_agent_rf_source_ready),               //       rf_source.ready
		.rf_source_valid         (mm_clock_crossing_bridge_0_s0_agent_rf_source_valid),               //                .valid
		.rf_source_startofpacket (mm_clock_crossing_bridge_0_s0_agent_rf_source_startofpacket),       //                .startofpacket
		.rf_source_endofpacket   (mm_clock_crossing_bridge_0_s0_agent_rf_source_endofpacket),         //                .endofpacket
		.rf_source_data          (mm_clock_crossing_bridge_0_s0_agent_rf_source_data),                //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                                     // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                                     //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                                      //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                                     //                .error
		.rdata_fifo_src_ready    (mm_clock_crossing_bridge_0_s0_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (mm_clock_crossing_bridge_0_s0_agent_rdata_fifo_src_valid),          //                .valid
		.rdata_fifo_src_data     (mm_clock_crossing_bridge_0_s0_agent_rdata_fifo_src_data),           //                .data
		.m0_response             (2'b00),                                                             //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                               //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (365),
		.FIFO_DEPTH          (37),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) mm_clock_crossing_bridge_0_s0_agent_rsp_fifo (
		.clk               (pcie_0_coreclkout_out_clk),                                       //       clk.clk
		.reset             (mm_clock_crossing_bridge_0_s0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (mm_clock_crossing_bridge_0_s0_agent_rf_source_data),              //        in.data
		.in_valid          (mm_clock_crossing_bridge_0_s0_agent_rf_source_valid),             //          .valid
		.in_ready          (mm_clock_crossing_bridge_0_s0_agent_rf_source_ready),             //          .ready
		.in_startofpacket  (mm_clock_crossing_bridge_0_s0_agent_rf_source_startofpacket),     //          .startofpacket
		.in_endofpacket    (mm_clock_crossing_bridge_0_s0_agent_rf_source_endofpacket),       //          .endofpacket
		.out_data          (mm_clock_crossing_bridge_0_s0_agent_rsp_fifo_out_data),           //       out.data
		.out_valid         (mm_clock_crossing_bridge_0_s0_agent_rsp_fifo_out_valid),          //          .valid
		.out_ready         (mm_clock_crossing_bridge_0_s0_agent_rsp_fifo_out_ready),          //          .ready
		.out_startofpacket (mm_clock_crossing_bridge_0_s0_agent_rsp_fifo_out_startofpacket),  //          .startofpacket
		.out_endofpacket   (mm_clock_crossing_bridge_0_s0_agent_rsp_fifo_out_endofpacket),    //          .endofpacket
		.csr_address       (2'b00),                                                           // (terminated)
		.csr_read          (1'b0),                                                            // (terminated)
		.csr_write         (1'b0),                                                            // (terminated)
		.csr_readdata      (),                                                                // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                            // (terminated)
		.almost_full_data  (),                                                                // (terminated)
		.almost_empty_data (),                                                                // (terminated)
		.in_empty          (1'b0),                                                            // (terminated)
		.out_empty         (),                                                                // (terminated)
		.in_error          (1'b0),                                                            // (terminated)
		.out_error         (),                                                                // (terminated)
		.in_channel        (1'b0),                                                            // (terminated)
		.out_channel       ()                                                                 // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (258),
		.FIFO_DEPTH          (1024),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (3),
		.USE_MEMORY_BLOCKS   (1),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) mm_clock_crossing_bridge_0_s0_agent_rdata_fifo (
		.clk               (pcie_0_coreclkout_out_clk),                                       //       clk.clk
		.reset             (mm_clock_crossing_bridge_0_s0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (mm_clock_crossing_bridge_0_s0_agent_rdata_fifo_src_data),         //        in.data
		.in_valid          (mm_clock_crossing_bridge_0_s0_agent_rdata_fifo_src_valid),        //          .valid
		.in_ready          (mm_clock_crossing_bridge_0_s0_agent_rdata_fifo_src_ready),        //          .ready
		.out_data          (mm_clock_crossing_bridge_0_s0_agent_rdata_fifo_out_data),         //       out.data
		.out_valid         (mm_clock_crossing_bridge_0_s0_agent_rdata_fifo_out_valid),        //          .valid
		.out_ready         (mm_clock_crossing_bridge_0_s0_agent_rdata_fifo_out_ready),        //          .ready
		.csr_address       (2'b00),                                                           // (terminated)
		.csr_read          (1'b0),                                                            // (terminated)
		.csr_write         (1'b0),                                                            // (terminated)
		.csr_readdata      (),                                                                // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                            // (terminated)
		.almost_full_data  (),                                                                // (terminated)
		.almost_empty_data (),                                                                // (terminated)
		.in_startofpacket  (1'b0),                                                            // (terminated)
		.in_endofpacket    (1'b0),                                                            // (terminated)
		.out_startofpacket (),                                                                // (terminated)
		.out_endofpacket   (),                                                                // (terminated)
		.in_empty          (1'b0),                                                            // (terminated)
		.out_empty         (),                                                                // (terminated)
		.in_error          (1'b0),                                                            // (terminated)
		.out_error         (),                                                                // (terminated)
		.in_channel        (1'b0),                                                            // (terminated)
		.out_channel       ()                                                                 // (terminated)
	);

	soc_system_mm_interconnect_0_router router (
		.sink_ready         (pcie_0_address_span_extender_0_expanded_master_agent_cp_ready),                               //      sink.ready
		.sink_valid         (pcie_0_address_span_extender_0_expanded_master_agent_cp_valid),                               //          .valid
		.sink_data          (pcie_0_address_span_extender_0_expanded_master_agent_cp_data),                                //          .data
		.sink_startofpacket (pcie_0_address_span_extender_0_expanded_master_agent_cp_startofpacket),                       //          .startofpacket
		.sink_endofpacket   (pcie_0_address_span_extender_0_expanded_master_agent_cp_endofpacket),                         //          .endofpacket
		.clk                (pcie_0_coreclk_fanout_clk_clk),                                                               //       clk.clk
		.reset              (pcie_0_address_span_extender_0_expanded_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_src_ready),                                                                            //       src.ready
		.src_valid          (router_src_valid),                                                                            //          .valid
		.src_data           (router_src_data),                                                                             //          .data
		.src_channel        (router_src_channel),                                                                          //          .channel
		.src_startofpacket  (router_src_startofpacket),                                                                    //          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                                                       //          .endofpacket
	);

	soc_system_mm_interconnect_0_router_001 router_001 (
		.sink_ready         (mm_clock_crossing_bridge_0_s0_agent_rp_ready),                    //      sink.ready
		.sink_valid         (mm_clock_crossing_bridge_0_s0_agent_rp_valid),                    //          .valid
		.sink_data          (mm_clock_crossing_bridge_0_s0_agent_rp_data),                     //          .data
		.sink_startofpacket (mm_clock_crossing_bridge_0_s0_agent_rp_startofpacket),            //          .startofpacket
		.sink_endofpacket   (mm_clock_crossing_bridge_0_s0_agent_rp_endofpacket),              //          .endofpacket
		.clk                (pcie_0_coreclkout_out_clk),                                       //       clk.clk
		.reset              (mm_clock_crossing_bridge_0_s0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_001_src_ready),                                            //       src.ready
		.src_valid          (router_001_src_valid),                                            //          .valid
		.src_data           (router_001_src_data),                                             //          .data
		.src_channel        (router_001_src_channel),                                          //          .channel
		.src_startofpacket  (router_001_src_startofpacket),                                    //          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                                       //          .endofpacket
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (319),
		.PKT_ADDR_L                (288),
		.PKT_BEGIN_BURST           (347),
		.PKT_BYTE_CNT_H            (338),
		.PKT_BYTE_CNT_L            (326),
		.PKT_BYTEEN_H              (287),
		.PKT_BYTEEN_L              (256),
		.PKT_BURST_SIZE_H          (342),
		.PKT_BURST_SIZE_L          (340),
		.PKT_BURST_TYPE_H          (344),
		.PKT_BURST_TYPE_L          (343),
		.PKT_BURSTWRAP_H           (339),
		.PKT_BURSTWRAP_L           (339),
		.PKT_TRANS_COMPRESSED_READ (320),
		.PKT_TRANS_WRITE           (322),
		.PKT_TRANS_READ            (323),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (364),
		.ST_CHANNEL_W              (1),
		.OUT_BYTE_CNT_H            (335),
		.OUT_BURSTWRAP_H           (339),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (1),
		.BURSTWRAP_CONST_VALUE     (1),
		.ADAPTER_VERSION           ("13.1")
	) mm_clock_crossing_bridge_0_s0_burst_adapter (
		.clk                   (pcie_0_coreclkout_out_clk),                                         //       cr0.clk
		.reset                 (mm_clock_crossing_bridge_0_s0_reset_reset_bridge_in_reset_reset),   // cr0_reset.reset
		.sink0_valid           (cmd_mux_src_valid),                                                 //     sink0.valid
		.sink0_data            (cmd_mux_src_data),                                                  //          .data
		.sink0_channel         (cmd_mux_src_channel),                                               //          .channel
		.sink0_startofpacket   (cmd_mux_src_startofpacket),                                         //          .startofpacket
		.sink0_endofpacket     (cmd_mux_src_endofpacket),                                           //          .endofpacket
		.sink0_ready           (cmd_mux_src_ready),                                                 //          .ready
		.source0_valid         (mm_clock_crossing_bridge_0_s0_burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (mm_clock_crossing_bridge_0_s0_burst_adapter_source0_data),          //          .data
		.source0_channel       (mm_clock_crossing_bridge_0_s0_burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (mm_clock_crossing_bridge_0_s0_burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (mm_clock_crossing_bridge_0_s0_burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (mm_clock_crossing_bridge_0_s0_burst_adapter_source0_ready)          //          .ready
	);

	soc_system_mm_interconnect_0_cmd_demux cmd_demux (
		.clk                (pcie_0_coreclk_fanout_clk_clk),                                                               //       clk.clk
		.reset              (pcie_0_address_span_extender_0_expanded_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_src_ready),                                                                            //      sink.ready
		.sink_channel       (router_src_channel),                                                                          //          .channel
		.sink_data          (router_src_data),                                                                             //          .data
		.sink_startofpacket (router_src_startofpacket),                                                                    //          .startofpacket
		.sink_endofpacket   (router_src_endofpacket),                                                                      //          .endofpacket
		.sink_valid         (router_src_valid),                                                                            //          .valid
		.src0_ready         (cmd_demux_src0_ready),                                                                        //      src0.ready
		.src0_valid         (cmd_demux_src0_valid),                                                                        //          .valid
		.src0_data          (cmd_demux_src0_data),                                                                         //          .data
		.src0_channel       (cmd_demux_src0_channel),                                                                      //          .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                                                                //          .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket)                                                                   //          .endofpacket
	);

	soc_system_mm_interconnect_0_cmd_mux cmd_mux (
		.clk                 (pcie_0_coreclkout_out_clk),                                       //       clk.clk
		.reset               (mm_clock_crossing_bridge_0_s0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                                               //       src.ready
		.src_valid           (cmd_mux_src_valid),                                               //          .valid
		.src_data            (cmd_mux_src_data),                                                //          .data
		.src_channel         (cmd_mux_src_channel),                                             //          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                                       //          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                                         //          .endofpacket
		.sink0_ready         (async_fifo_out_ready),                                            //     sink0.ready
		.sink0_valid         (async_fifo_out_valid),                                            //          .valid
		.sink0_channel       (async_fifo_out_channel),                                          //          .channel
		.sink0_data          (async_fifo_out_data),                                             //          .data
		.sink0_startofpacket (async_fifo_out_startofpacket),                                    //          .startofpacket
		.sink0_endofpacket   (async_fifo_out_endofpacket)                                       //          .endofpacket
	);

	soc_system_mm_interconnect_0_cmd_demux rsp_demux (
		.clk                (pcie_0_coreclkout_out_clk),                                       //       clk.clk
		.reset              (mm_clock_crossing_bridge_0_s0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_001_src_ready),                                            //      sink.ready
		.sink_channel       (router_001_src_channel),                                          //          .channel
		.sink_data          (router_001_src_data),                                             //          .data
		.sink_startofpacket (router_001_src_startofpacket),                                    //          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),                                      //          .endofpacket
		.sink_valid         (router_001_src_valid),                                            //          .valid
		.src0_ready         (rsp_demux_src0_ready),                                            //      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                                            //          .valid
		.src0_data          (rsp_demux_src0_data),                                             //          .data
		.src0_channel       (rsp_demux_src0_channel),                                          //          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                                    //          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket)                                       //          .endofpacket
	);

	soc_system_mm_interconnect_0_rsp_mux rsp_mux (
		.clk                 (pcie_0_coreclk_fanout_clk_clk),                                                               //       clk.clk
		.reset               (pcie_0_address_span_extender_0_expanded_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                                                                           //       src.ready
		.src_valid           (rsp_mux_src_valid),                                                                           //          .valid
		.src_data            (rsp_mux_src_data),                                                                            //          .data
		.src_channel         (rsp_mux_src_channel),                                                                         //          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                                                                   //          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                                                                     //          .endofpacket
		.sink0_ready         (async_fifo_001_out_ready),                                                                    //     sink0.ready
		.sink0_valid         (async_fifo_001_out_valid),                                                                    //          .valid
		.sink0_channel       (async_fifo_001_out_channel),                                                                  //          .channel
		.sink0_data          (async_fifo_001_out_data),                                                                     //          .data
		.sink0_startofpacket (async_fifo_001_out_startofpacket),                                                            //          .startofpacket
		.sink0_endofpacket   (async_fifo_001_out_endofpacket)                                                               //          .endofpacket
	);

	altera_avalon_dc_fifo #(
		.SYMBOLS_PER_BEAT   (1),
		.BITS_PER_SYMBOL    (364),
		.FIFO_DEPTH         (8),
		.CHANNEL_WIDTH      (1),
		.ERROR_WIDTH        (0),
		.USE_PACKETS        (1),
		.USE_IN_FILL_LEVEL  (0),
		.USE_OUT_FILL_LEVEL (0),
		.WR_SYNC_DEPTH      (3),
		.RD_SYNC_DEPTH      (3)
	) async_fifo (
		.in_clk            (pcie_0_coreclk_fanout_clk_clk),                                                                //        in_clk.clk
		.in_reset_n        (~pcie_0_address_span_extender_0_expanded_master_translator_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset_n
		.out_clk           (pcie_0_coreclkout_out_clk),                                                                    //       out_clk.clk
		.out_reset_n       (~mm_clock_crossing_bridge_0_s0_reset_reset_bridge_in_reset_reset),                             // out_clk_reset.reset_n
		.in_data           (cmd_demux_src0_data),                                                                          //            in.data
		.in_valid          (cmd_demux_src0_valid),                                                                         //              .valid
		.in_ready          (cmd_demux_src0_ready),                                                                         //              .ready
		.in_startofpacket  (cmd_demux_src0_startofpacket),                                                                 //              .startofpacket
		.in_endofpacket    (cmd_demux_src0_endofpacket),                                                                   //              .endofpacket
		.in_channel        (cmd_demux_src0_channel),                                                                       //              .channel
		.out_data          (async_fifo_out_data),                                                                          //           out.data
		.out_valid         (async_fifo_out_valid),                                                                         //              .valid
		.out_ready         (async_fifo_out_ready),                                                                         //              .ready
		.out_startofpacket (async_fifo_out_startofpacket),                                                                 //              .startofpacket
		.out_endofpacket   (async_fifo_out_endofpacket),                                                                   //              .endofpacket
		.out_channel       (async_fifo_out_channel),                                                                       //              .channel
		.in_csr_address    (1'b0),                                                                                         //   (terminated)
		.in_csr_read       (1'b0),                                                                                         //   (terminated)
		.in_csr_write      (1'b0),                                                                                         //   (terminated)
		.in_csr_readdata   (),                                                                                             //   (terminated)
		.in_csr_writedata  (32'b00000000000000000000000000000000),                                                         //   (terminated)
		.out_csr_address   (1'b0),                                                                                         //   (terminated)
		.out_csr_read      (1'b0),                                                                                         //   (terminated)
		.out_csr_write     (1'b0),                                                                                         //   (terminated)
		.out_csr_readdata  (),                                                                                             //   (terminated)
		.out_csr_writedata (32'b00000000000000000000000000000000),                                                         //   (terminated)
		.in_empty          (1'b0),                                                                                         //   (terminated)
		.out_empty         (),                                                                                             //   (terminated)
		.in_error          (1'b0),                                                                                         //   (terminated)
		.out_error         (),                                                                                             //   (terminated)
		.space_avail_data  ()                                                                                              //   (terminated)
	);

	altera_avalon_dc_fifo #(
		.SYMBOLS_PER_BEAT   (1),
		.BITS_PER_SYMBOL    (364),
		.FIFO_DEPTH         (8),
		.CHANNEL_WIDTH      (1),
		.ERROR_WIDTH        (0),
		.USE_PACKETS        (1),
		.USE_IN_FILL_LEVEL  (0),
		.USE_OUT_FILL_LEVEL (0),
		.WR_SYNC_DEPTH      (3),
		.RD_SYNC_DEPTH      (3)
	) async_fifo_001 (
		.in_clk            (pcie_0_coreclkout_out_clk),                                                                    //        in_clk.clk
		.in_reset_n        (~mm_clock_crossing_bridge_0_s0_reset_reset_bridge_in_reset_reset),                             //  in_clk_reset.reset_n
		.out_clk           (pcie_0_coreclk_fanout_clk_clk),                                                                //       out_clk.clk
		.out_reset_n       (~pcie_0_address_span_extender_0_expanded_master_translator_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset_n
		.in_data           (rsp_demux_src0_data),                                                                          //            in.data
		.in_valid          (rsp_demux_src0_valid),                                                                         //              .valid
		.in_ready          (rsp_demux_src0_ready),                                                                         //              .ready
		.in_startofpacket  (rsp_demux_src0_startofpacket),                                                                 //              .startofpacket
		.in_endofpacket    (rsp_demux_src0_endofpacket),                                                                   //              .endofpacket
		.in_channel        (rsp_demux_src0_channel),                                                                       //              .channel
		.out_data          (async_fifo_001_out_data),                                                                      //           out.data
		.out_valid         (async_fifo_001_out_valid),                                                                     //              .valid
		.out_ready         (async_fifo_001_out_ready),                                                                     //              .ready
		.out_startofpacket (async_fifo_001_out_startofpacket),                                                             //              .startofpacket
		.out_endofpacket   (async_fifo_001_out_endofpacket),                                                               //              .endofpacket
		.out_channel       (async_fifo_001_out_channel),                                                                   //              .channel
		.in_csr_address    (1'b0),                                                                                         //   (terminated)
		.in_csr_read       (1'b0),                                                                                         //   (terminated)
		.in_csr_write      (1'b0),                                                                                         //   (terminated)
		.in_csr_readdata   (),                                                                                             //   (terminated)
		.in_csr_writedata  (32'b00000000000000000000000000000000),                                                         //   (terminated)
		.out_csr_address   (1'b0),                                                                                         //   (terminated)
		.out_csr_read      (1'b0),                                                                                         //   (terminated)
		.out_csr_write     (1'b0),                                                                                         //   (terminated)
		.out_csr_readdata  (),                                                                                             //   (terminated)
		.out_csr_writedata (32'b00000000000000000000000000000000),                                                         //   (terminated)
		.in_empty          (1'b0),                                                                                         //   (terminated)
		.out_empty         (),                                                                                             //   (terminated)
		.in_error          (1'b0),                                                                                         //   (terminated)
		.out_error         (),                                                                                             //   (terminated)
		.space_avail_data  ()                                                                                              //   (terminated)
	);

	soc_system_mm_interconnect_0_avalon_st_adapter #(
		.inBitsPerSymbol (258),
		.inUsePackets    (0),
		.inDataWidth     (258),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (258),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter (
		.in_clk_0_clk   (pcie_0_coreclkout_out_clk),                                       // in_clk_0.clk
		.in_rst_0_reset (mm_clock_crossing_bridge_0_s0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (mm_clock_crossing_bridge_0_s0_agent_rdata_fifo_out_data),         //     in_0.data
		.in_0_valid     (mm_clock_crossing_bridge_0_s0_agent_rdata_fifo_out_valid),        //         .valid
		.in_0_ready     (mm_clock_crossing_bridge_0_s0_agent_rdata_fifo_out_ready),        //         .ready
		.out_0_data     (avalon_st_adapter_out_0_data),                                    //    out_0.data
		.out_0_valid    (avalon_st_adapter_out_0_valid),                                   //         .valid
		.out_0_ready    (avalon_st_adapter_out_0_ready),                                   //         .ready
		.out_0_error    (avalon_st_adapter_out_0_error)                                    //         .error
	);

endmodule
