// soc_system_pcie_0.v

// Generated using ACDS version 18.1 646

`timescale 1 ps / 1 ps
module soc_system_pcie_0 (
		output wire [31:0]  address_span_extender_0_expanded_master_address,       // address_span_extender_0_expanded_master.address
		output wire         address_span_extender_0_expanded_master_read,          //                                        .read
		input  wire         address_span_extender_0_expanded_master_waitrequest,   //                                        .waitrequest
		input  wire [255:0] address_span_extender_0_expanded_master_readdata,      //                                        .readdata
		output wire         address_span_extender_0_expanded_master_write,         //                                        .write
		output wire [255:0] address_span_extender_0_expanded_master_writedata,     //                                        .writedata
		input  wire         address_span_extender_0_expanded_master_readdatavalid, //                                        .readdatavalid
		output wire [31:0]  address_span_extender_0_expanded_master_byteenable,    //                                        .byteenable
		output wire [7:0]   address_span_extender_0_expanded_master_burstcount,    //                                        .burstcount
		input  wire [6:0]   alt_xcvr_reconfig_0_reconfig_mgmt_address,             //       alt_xcvr_reconfig_0_reconfig_mgmt.address
		input  wire         alt_xcvr_reconfig_0_reconfig_mgmt_read,                //                                        .read
		output wire [31:0]  alt_xcvr_reconfig_0_reconfig_mgmt_readdata,            //                                        .readdata
		output wire         alt_xcvr_reconfig_0_reconfig_mgmt_waitrequest,         //                                        .waitrequest
		input  wire         alt_xcvr_reconfig_0_reconfig_mgmt_write,               //                                        .write
		input  wire [31:0]  alt_xcvr_reconfig_0_reconfig_mgmt_writedata,           //                                        .writedata
		output wire         ccb_h2f_s0_waitrequest,                                //                              ccb_h2f_s0.waitrequest
		output wire [63:0]  ccb_h2f_s0_readdata,                                   //                                        .readdata
		output wire         ccb_h2f_s0_readdatavalid,                              //                                        .readdatavalid
		input  wire [6:0]   ccb_h2f_s0_burstcount,                                 //                                        .burstcount
		input  wire [63:0]  ccb_h2f_s0_writedata,                                  //                                        .writedata
		input  wire [27:0]  ccb_h2f_s0_address,                                    //                                        .address
		input  wire         ccb_h2f_s0_write,                                      //                                        .write
		input  wire         ccb_h2f_s0_read,                                       //                                        .read
		input  wire [7:0]   ccb_h2f_s0_byteenable,                                 //                                        .byteenable
		input  wire         ccb_h2f_s0_debugaccess,                                //                                        .debugaccess
		input  wire         clk_clk,                                               //                                     clk.clk
		output wire         coreclk_fanout_clk_clk,                                //                      coreclk_fanout_clk.clk
		output wire         coreclk_fanout_clk_reset_reset_n,                      //                coreclk_fanout_clk_reset.reset_n
		output wire         coreclkout_out_clk,                                    //                          coreclkout_out.clk
		output wire         msgdma_0_csr_irq_irq,                                  //                        msgdma_0_csr_irq.irq
		output wire         msi_to_gic_gen_0_interrupt_sender_irq,                 //       msi_to_gic_gen_0_interrupt_sender.irq
		output wire         nreset_status_out_reset_reset_n,                       //                 nreset_status_out_reset.reset_n
		input  wire         pb_2_ocm_m0_waitrequest,                               //                             pb_2_ocm_m0.waitrequest
		input  wire [63:0]  pb_2_ocm_m0_readdata,                                  //                                        .readdata
		input  wire         pb_2_ocm_m0_readdatavalid,                             //                                        .readdatavalid
		output wire [6:0]   pb_2_ocm_m0_burstcount,                                //                                        .burstcount
		output wire [63:0]  pb_2_ocm_m0_writedata,                                 //                                        .writedata
		output wire [15:0]  pb_2_ocm_m0_address,                                   //                                        .address
		output wire         pb_2_ocm_m0_write,                                     //                                        .write
		output wire         pb_2_ocm_m0_read,                                      //                                        .read
		output wire [7:0]   pb_2_ocm_m0_byteenable,                                //                                        .byteenable
		output wire         pb_2_ocm_m0_debugaccess,                               //                                        .debugaccess
		output wire         pb_lwh2f_pcie_s0_waitrequest,                          //                        pb_lwh2f_pcie_s0.waitrequest
		output wire [31:0]  pb_lwh2f_pcie_s0_readdata,                             //                                        .readdata
		output wire         pb_lwh2f_pcie_s0_readdatavalid,                        //                                        .readdatavalid
		input  wire [0:0]   pb_lwh2f_pcie_s0_burstcount,                           //                                        .burstcount
		input  wire [31:0]  pb_lwh2f_pcie_s0_writedata,                            //                                        .writedata
		input  wire [14:0]  pb_lwh2f_pcie_s0_address,                              //                                        .address
		input  wire         pb_lwh2f_pcie_s0_write,                                //                                        .write
		input  wire         pb_lwh2f_pcie_s0_read,                                 //                                        .read
		input  wire [3:0]   pb_lwh2f_pcie_s0_byteenable,                           //                                        .byteenable
		input  wire         pb_lwh2f_pcie_s0_debugaccess,                          //                                        .debugaccess
		output wire         pcie_hip_avmm_cra_irq_irq,                             //                   pcie_hip_avmm_cra_irq.irq
		input  wire [31:0]  pcie_hip_avmm_hip_ctrl_test_in,                        //                  pcie_hip_avmm_hip_ctrl.test_in
		input  wire         pcie_hip_avmm_hip_ctrl_simu_mode_pipe,                 //                                        .simu_mode_pipe
		input  wire         pcie_hip_avmm_hip_pipe_sim_pipe_pclk_in,               //                  pcie_hip_avmm_hip_pipe.sim_pipe_pclk_in
		output wire [1:0]   pcie_hip_avmm_hip_pipe_sim_pipe_rate,                  //                                        .sim_pipe_rate
		output wire [4:0]   pcie_hip_avmm_hip_pipe_sim_ltssmstate,                 //                                        .sim_ltssmstate
		output wire [2:0]   pcie_hip_avmm_hip_pipe_eidleinfersel0,                 //                                        .eidleinfersel0
		output wire [1:0]   pcie_hip_avmm_hip_pipe_powerdown0,                     //                                        .powerdown0
		output wire         pcie_hip_avmm_hip_pipe_rxpolarity0,                    //                                        .rxpolarity0
		output wire         pcie_hip_avmm_hip_pipe_txcompl0,                       //                                        .txcompl0
		output wire [7:0]   pcie_hip_avmm_hip_pipe_txdata0,                        //                                        .txdata0
		output wire         pcie_hip_avmm_hip_pipe_txdatak0,                       //                                        .txdatak0
		output wire         pcie_hip_avmm_hip_pipe_txdetectrx0,                    //                                        .txdetectrx0
		output wire         pcie_hip_avmm_hip_pipe_txelecidle0,                    //                                        .txelecidle0
		output wire         pcie_hip_avmm_hip_pipe_txswing0,                       //                                        .txswing0
		output wire [2:0]   pcie_hip_avmm_hip_pipe_txmargin0,                      //                                        .txmargin0
		output wire         pcie_hip_avmm_hip_pipe_txdeemph0,                      //                                        .txdeemph0
		input  wire         pcie_hip_avmm_hip_pipe_phystatus0,                     //                                        .phystatus0
		input  wire [7:0]   pcie_hip_avmm_hip_pipe_rxdata0,                        //                                        .rxdata0
		input  wire         pcie_hip_avmm_hip_pipe_rxdatak0,                       //                                        .rxdatak0
		input  wire         pcie_hip_avmm_hip_pipe_rxelecidle0,                    //                                        .rxelecidle0
		input  wire [2:0]   pcie_hip_avmm_hip_pipe_rxstatus0,                      //                                        .rxstatus0
		input  wire         pcie_hip_avmm_hip_pipe_rxvalid0,                       //                                        .rxvalid0
		input  wire         pcie_hip_avmm_hip_serial_rx_in0,                       //                pcie_hip_avmm_hip_serial.rx_in0
		output wire         pcie_hip_avmm_hip_serial_tx_out0,                      //                                        .tx_out0
		input  wire         pcie_hip_avmm_npor_npor,                               //                      pcie_hip_avmm_npor.npor
		input  wire         pcie_hip_avmm_npor_pin_perst,                          //                                        .pin_perst
		output wire         pcie_hip_avmm_reconfig_clk_locked_fixedclk_locked,     //       pcie_hip_avmm_reconfig_clk_locked.fixedclk_locked
		input  wire         pcie_hip_avmm_refclk_clk,                              //                    pcie_hip_avmm_refclk.clk
		input  wire         reset_reset_n                                          //                                   reset.reset_n
	);

	wire          pcie_hip_avmm_coreclkout_clk;                                        // pcie_hip_avmm:coreclkout -> [custom_reset_synchronizer_0:clk_in, irq_mapper:clk, mm_interconnect_0:pcie_hip_avmm_coreclkout_clk, mm_interconnect_1:pcie_hip_avmm_coreclkout_clk, mm_interconnect_2:pcie_hip_avmm_coreclkout_clk, rst_controller_002:clk]
	wire          alt_xcvr_reconfig_0_reconfig_busy_reconfig_busy;                     // alt_xcvr_reconfig_0:reconfig_busy -> pcie_hip_avmm:busy_xcvr_reconfig
	wire   [91:0] pcie_hip_avmm_reconfig_from_xcvr_reconfig_from_xcvr;                 // pcie_hip_avmm:reconfig_from_xcvr -> alt_xcvr_reconfig_0:reconfig_from_xcvr
	wire  [139:0] alt_xcvr_reconfig_0_reconfig_to_xcvr_reconfig_to_xcvr;               // alt_xcvr_reconfig_0:reconfig_to_xcvr -> pcie_hip_avmm:reconfig_to_xcvr
	wire          custom_reset_synchronizer_0_reset_out_reset;                         // custom_reset_synchronizer_0:reset_out -> [add_x_f2sdram:reset, alt_xcvr_reconfig_0:mgmt_rst_reset, ccb_h2f:m0_reset, custom_reset_synchronizer_0_reset_out_reset:in, mm_interconnect_0:msgdma_0_reset_n_reset_bridge_in_reset_reset, mm_interconnect_1:pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset, mm_interconnect_2:ccb_h2f_m0_reset_reset_bridge_in_reset_reset, mm_interconnect_3:pb_f2sdram_reset_reset_bridge_in_reset_reset, msgdma_0:reset_n_reset_n, pb_2_ocm:reset, pb_f2sdram:reset, pb_lwh2f_pcie:reset, pb_msgdma_2_txs:reset, pb_rxm_2_msi:reset, rst_controller:reset_in0]
	wire          pcie_hip_avmm_rp_master_waitrequest;                                 // mm_interconnect_0:pcie_hip_avmm_RP_Master_waitrequest -> pcie_hip_avmm:RxmWaitRequest_0_i
	wire   [63:0] pcie_hip_avmm_rp_master_readdata;                                    // mm_interconnect_0:pcie_hip_avmm_RP_Master_readdata -> pcie_hip_avmm:RxmReadData_0_i
	wire   [31:0] pcie_hip_avmm_rp_master_address;                                     // pcie_hip_avmm:RxmAddress_0_o -> mm_interconnect_0:pcie_hip_avmm_RP_Master_address
	wire          pcie_hip_avmm_rp_master_read;                                        // pcie_hip_avmm:RxmRead_0_o -> mm_interconnect_0:pcie_hip_avmm_RP_Master_read
	wire    [7:0] pcie_hip_avmm_rp_master_byteenable;                                  // pcie_hip_avmm:RxmByteEnable_0_o -> mm_interconnect_0:pcie_hip_avmm_RP_Master_byteenable
	wire          pcie_hip_avmm_rp_master_readdatavalid;                               // mm_interconnect_0:pcie_hip_avmm_RP_Master_readdatavalid -> pcie_hip_avmm:RxmReadDataValid_0_i
	wire          pcie_hip_avmm_rp_master_write;                                       // pcie_hip_avmm:RxmWrite_0_o -> mm_interconnect_0:pcie_hip_avmm_RP_Master_write
	wire   [63:0] pcie_hip_avmm_rp_master_writedata;                                   // pcie_hip_avmm:RxmWriteData_0_o -> mm_interconnect_0:pcie_hip_avmm_RP_Master_writedata
	wire    [6:0] pcie_hip_avmm_rp_master_burstcount;                                  // pcie_hip_avmm:RxmBurstCount_0_o -> mm_interconnect_0:pcie_hip_avmm_RP_Master_burstcount
	wire   [63:0] msgdma_0_mm_read_readdata;                                           // mm_interconnect_0:msgdma_0_mm_read_readdata -> msgdma_0:mm_read_readdata
	wire          msgdma_0_mm_read_waitrequest;                                        // mm_interconnect_0:msgdma_0_mm_read_waitrequest -> msgdma_0:mm_read_waitrequest
	wire   [31:0] msgdma_0_mm_read_address;                                            // msgdma_0:mm_read_address -> mm_interconnect_0:msgdma_0_mm_read_address
	wire          msgdma_0_mm_read_read;                                               // msgdma_0:mm_read_read -> mm_interconnect_0:msgdma_0_mm_read_read
	wire    [7:0] msgdma_0_mm_read_byteenable;                                         // msgdma_0:mm_read_byteenable -> mm_interconnect_0:msgdma_0_mm_read_byteenable
	wire          msgdma_0_mm_read_readdatavalid;                                      // mm_interconnect_0:msgdma_0_mm_read_readdatavalid -> msgdma_0:mm_read_readdatavalid
	wire    [6:0] msgdma_0_mm_read_burstcount;                                         // msgdma_0:mm_read_burstcount -> mm_interconnect_0:msgdma_0_mm_read_burstcount
	wire          msgdma_0_mm_write_waitrequest;                                       // mm_interconnect_0:msgdma_0_mm_write_waitrequest -> msgdma_0:mm_write_waitrequest
	wire   [31:0] msgdma_0_mm_write_address;                                           // msgdma_0:mm_write_address -> mm_interconnect_0:msgdma_0_mm_write_address
	wire    [7:0] msgdma_0_mm_write_byteenable;                                        // msgdma_0:mm_write_byteenable -> mm_interconnect_0:msgdma_0_mm_write_byteenable
	wire          msgdma_0_mm_write_write;                                             // msgdma_0:mm_write_write -> mm_interconnect_0:msgdma_0_mm_write_write
	wire   [63:0] msgdma_0_mm_write_writedata;                                         // msgdma_0:mm_write_writedata -> mm_interconnect_0:msgdma_0_mm_write_writedata
	wire    [6:0] msgdma_0_mm_write_burstcount;                                        // msgdma_0:mm_write_burstcount -> mm_interconnect_0:msgdma_0_mm_write_burstcount
	wire   [31:0] mm_interconnect_0_pb_rxm_2_msi_s0_readdata;                          // pb_rxm_2_msi:s0_readdata -> mm_interconnect_0:pb_rxm_2_msi_s0_readdata
	wire          mm_interconnect_0_pb_rxm_2_msi_s0_waitrequest;                       // pb_rxm_2_msi:s0_waitrequest -> mm_interconnect_0:pb_rxm_2_msi_s0_waitrequest
	wire          mm_interconnect_0_pb_rxm_2_msi_s0_debugaccess;                       // mm_interconnect_0:pb_rxm_2_msi_s0_debugaccess -> pb_rxm_2_msi:s0_debugaccess
	wire   [14:0] mm_interconnect_0_pb_rxm_2_msi_s0_address;                           // mm_interconnect_0:pb_rxm_2_msi_s0_address -> pb_rxm_2_msi:s0_address
	wire          mm_interconnect_0_pb_rxm_2_msi_s0_read;                              // mm_interconnect_0:pb_rxm_2_msi_s0_read -> pb_rxm_2_msi:s0_read
	wire    [3:0] mm_interconnect_0_pb_rxm_2_msi_s0_byteenable;                        // mm_interconnect_0:pb_rxm_2_msi_s0_byteenable -> pb_rxm_2_msi:s0_byteenable
	wire          mm_interconnect_0_pb_rxm_2_msi_s0_readdatavalid;                     // pb_rxm_2_msi:s0_readdatavalid -> mm_interconnect_0:pb_rxm_2_msi_s0_readdatavalid
	wire          mm_interconnect_0_pb_rxm_2_msi_s0_write;                             // mm_interconnect_0:pb_rxm_2_msi_s0_write -> pb_rxm_2_msi:s0_write
	wire   [31:0] mm_interconnect_0_pb_rxm_2_msi_s0_writedata;                         // mm_interconnect_0:pb_rxm_2_msi_s0_writedata -> pb_rxm_2_msi:s0_writedata
	wire    [0:0] mm_interconnect_0_pb_rxm_2_msi_s0_burstcount;                        // mm_interconnect_0:pb_rxm_2_msi_s0_burstcount -> pb_rxm_2_msi:s0_burstcount
	wire   [63:0] mm_interconnect_0_pb_2_ocm_s0_readdata;                              // pb_2_ocm:s0_readdata -> mm_interconnect_0:pb_2_ocm_s0_readdata
	wire          mm_interconnect_0_pb_2_ocm_s0_waitrequest;                           // pb_2_ocm:s0_waitrequest -> mm_interconnect_0:pb_2_ocm_s0_waitrequest
	wire          mm_interconnect_0_pb_2_ocm_s0_debugaccess;                           // mm_interconnect_0:pb_2_ocm_s0_debugaccess -> pb_2_ocm:s0_debugaccess
	wire   [15:0] mm_interconnect_0_pb_2_ocm_s0_address;                               // mm_interconnect_0:pb_2_ocm_s0_address -> pb_2_ocm:s0_address
	wire          mm_interconnect_0_pb_2_ocm_s0_read;                                  // mm_interconnect_0:pb_2_ocm_s0_read -> pb_2_ocm:s0_read
	wire    [7:0] mm_interconnect_0_pb_2_ocm_s0_byteenable;                            // mm_interconnect_0:pb_2_ocm_s0_byteenable -> pb_2_ocm:s0_byteenable
	wire          mm_interconnect_0_pb_2_ocm_s0_readdatavalid;                         // pb_2_ocm:s0_readdatavalid -> mm_interconnect_0:pb_2_ocm_s0_readdatavalid
	wire          mm_interconnect_0_pb_2_ocm_s0_write;                                 // mm_interconnect_0:pb_2_ocm_s0_write -> pb_2_ocm:s0_write
	wire   [63:0] mm_interconnect_0_pb_2_ocm_s0_writedata;                             // mm_interconnect_0:pb_2_ocm_s0_writedata -> pb_2_ocm:s0_writedata
	wire    [6:0] mm_interconnect_0_pb_2_ocm_s0_burstcount;                            // mm_interconnect_0:pb_2_ocm_s0_burstcount -> pb_2_ocm:s0_burstcount
	wire   [63:0] mm_interconnect_0_pb_f2sdram_s0_readdata;                            // pb_f2sdram:s0_readdata -> mm_interconnect_0:pb_f2sdram_s0_readdata
	wire          mm_interconnect_0_pb_f2sdram_s0_waitrequest;                         // pb_f2sdram:s0_waitrequest -> mm_interconnect_0:pb_f2sdram_s0_waitrequest
	wire          mm_interconnect_0_pb_f2sdram_s0_debugaccess;                         // mm_interconnect_0:pb_f2sdram_s0_debugaccess -> pb_f2sdram:s0_debugaccess
	wire   [29:0] mm_interconnect_0_pb_f2sdram_s0_address;                             // mm_interconnect_0:pb_f2sdram_s0_address -> pb_f2sdram:s0_address
	wire          mm_interconnect_0_pb_f2sdram_s0_read;                                // mm_interconnect_0:pb_f2sdram_s0_read -> pb_f2sdram:s0_read
	wire    [7:0] mm_interconnect_0_pb_f2sdram_s0_byteenable;                          // mm_interconnect_0:pb_f2sdram_s0_byteenable -> pb_f2sdram:s0_byteenable
	wire          mm_interconnect_0_pb_f2sdram_s0_readdatavalid;                       // pb_f2sdram:s0_readdatavalid -> mm_interconnect_0:pb_f2sdram_s0_readdatavalid
	wire          mm_interconnect_0_pb_f2sdram_s0_write;                               // mm_interconnect_0:pb_f2sdram_s0_write -> pb_f2sdram:s0_write
	wire   [63:0] mm_interconnect_0_pb_f2sdram_s0_writedata;                           // mm_interconnect_0:pb_f2sdram_s0_writedata -> pb_f2sdram:s0_writedata
	wire    [6:0] mm_interconnect_0_pb_f2sdram_s0_burstcount;                          // mm_interconnect_0:pb_f2sdram_s0_burstcount -> pb_f2sdram:s0_burstcount
	wire   [63:0] mm_interconnect_0_pb_msgdma_2_txs_s0_readdata;                       // pb_msgdma_2_txs:s0_readdata -> mm_interconnect_0:pb_msgdma_2_txs_s0_readdata
	wire          mm_interconnect_0_pb_msgdma_2_txs_s0_waitrequest;                    // pb_msgdma_2_txs:s0_waitrequest -> mm_interconnect_0:pb_msgdma_2_txs_s0_waitrequest
	wire          mm_interconnect_0_pb_msgdma_2_txs_s0_debugaccess;                    // mm_interconnect_0:pb_msgdma_2_txs_s0_debugaccess -> pb_msgdma_2_txs:s0_debugaccess
	wire   [27:0] mm_interconnect_0_pb_msgdma_2_txs_s0_address;                        // mm_interconnect_0:pb_msgdma_2_txs_s0_address -> pb_msgdma_2_txs:s0_address
	wire          mm_interconnect_0_pb_msgdma_2_txs_s0_read;                           // mm_interconnect_0:pb_msgdma_2_txs_s0_read -> pb_msgdma_2_txs:s0_read
	wire    [7:0] mm_interconnect_0_pb_msgdma_2_txs_s0_byteenable;                     // mm_interconnect_0:pb_msgdma_2_txs_s0_byteenable -> pb_msgdma_2_txs:s0_byteenable
	wire          mm_interconnect_0_pb_msgdma_2_txs_s0_readdatavalid;                  // pb_msgdma_2_txs:s0_readdatavalid -> mm_interconnect_0:pb_msgdma_2_txs_s0_readdatavalid
	wire          mm_interconnect_0_pb_msgdma_2_txs_s0_write;                          // mm_interconnect_0:pb_msgdma_2_txs_s0_write -> pb_msgdma_2_txs:s0_write
	wire   [63:0] mm_interconnect_0_pb_msgdma_2_txs_s0_writedata;                      // mm_interconnect_0:pb_msgdma_2_txs_s0_writedata -> pb_msgdma_2_txs:s0_writedata
	wire    [6:0] mm_interconnect_0_pb_msgdma_2_txs_s0_burstcount;                     // mm_interconnect_0:pb_msgdma_2_txs_s0_burstcount -> pb_msgdma_2_txs:s0_burstcount
	wire          pb_lwh2f_pcie_m0_waitrequest;                                        // mm_interconnect_1:pb_lwh2f_pcie_m0_waitrequest -> pb_lwh2f_pcie:m0_waitrequest
	wire   [31:0] pb_lwh2f_pcie_m0_readdata;                                           // mm_interconnect_1:pb_lwh2f_pcie_m0_readdata -> pb_lwh2f_pcie:m0_readdata
	wire          pb_lwh2f_pcie_m0_debugaccess;                                        // pb_lwh2f_pcie:m0_debugaccess -> mm_interconnect_1:pb_lwh2f_pcie_m0_debugaccess
	wire   [14:0] pb_lwh2f_pcie_m0_address;                                            // pb_lwh2f_pcie:m0_address -> mm_interconnect_1:pb_lwh2f_pcie_m0_address
	wire          pb_lwh2f_pcie_m0_read;                                               // pb_lwh2f_pcie:m0_read -> mm_interconnect_1:pb_lwh2f_pcie_m0_read
	wire    [3:0] pb_lwh2f_pcie_m0_byteenable;                                         // pb_lwh2f_pcie:m0_byteenable -> mm_interconnect_1:pb_lwh2f_pcie_m0_byteenable
	wire          pb_lwh2f_pcie_m0_readdatavalid;                                      // mm_interconnect_1:pb_lwh2f_pcie_m0_readdatavalid -> pb_lwh2f_pcie:m0_readdatavalid
	wire   [31:0] pb_lwh2f_pcie_m0_writedata;                                          // pb_lwh2f_pcie:m0_writedata -> mm_interconnect_1:pb_lwh2f_pcie_m0_writedata
	wire          pb_lwh2f_pcie_m0_write;                                              // pb_lwh2f_pcie:m0_write -> mm_interconnect_1:pb_lwh2f_pcie_m0_write
	wire    [0:0] pb_lwh2f_pcie_m0_burstcount;                                         // pb_lwh2f_pcie:m0_burstcount -> mm_interconnect_1:pb_lwh2f_pcie_m0_burstcount
	wire          pb_rxm_2_msi_m0_waitrequest;                                         // mm_interconnect_1:pb_rxm_2_msi_m0_waitrequest -> pb_rxm_2_msi:m0_waitrequest
	wire   [31:0] pb_rxm_2_msi_m0_readdata;                                            // mm_interconnect_1:pb_rxm_2_msi_m0_readdata -> pb_rxm_2_msi:m0_readdata
	wire          pb_rxm_2_msi_m0_debugaccess;                                         // pb_rxm_2_msi:m0_debugaccess -> mm_interconnect_1:pb_rxm_2_msi_m0_debugaccess
	wire   [14:0] pb_rxm_2_msi_m0_address;                                             // pb_rxm_2_msi:m0_address -> mm_interconnect_1:pb_rxm_2_msi_m0_address
	wire          pb_rxm_2_msi_m0_read;                                                // pb_rxm_2_msi:m0_read -> mm_interconnect_1:pb_rxm_2_msi_m0_read
	wire    [3:0] pb_rxm_2_msi_m0_byteenable;                                          // pb_rxm_2_msi:m0_byteenable -> mm_interconnect_1:pb_rxm_2_msi_m0_byteenable
	wire          pb_rxm_2_msi_m0_readdatavalid;                                       // mm_interconnect_1:pb_rxm_2_msi_m0_readdatavalid -> pb_rxm_2_msi:m0_readdatavalid
	wire   [31:0] pb_rxm_2_msi_m0_writedata;                                           // pb_rxm_2_msi:m0_writedata -> mm_interconnect_1:pb_rxm_2_msi_m0_writedata
	wire          pb_rxm_2_msi_m0_write;                                               // pb_rxm_2_msi:m0_write -> mm_interconnect_1:pb_rxm_2_msi_m0_write
	wire    [0:0] pb_rxm_2_msi_m0_burstcount;                                          // pb_rxm_2_msi:m0_burstcount -> mm_interconnect_1:pb_rxm_2_msi_m0_burstcount
	wire          mm_interconnect_1_pcie_hip_avmm_cra_chipselect;                      // mm_interconnect_1:pcie_hip_avmm_Cra_chipselect -> pcie_hip_avmm:CraChipSelect_i
	wire   [31:0] mm_interconnect_1_pcie_hip_avmm_cra_readdata;                        // pcie_hip_avmm:CraReadData_o -> mm_interconnect_1:pcie_hip_avmm_Cra_readdata
	wire          mm_interconnect_1_pcie_hip_avmm_cra_waitrequest;                     // pcie_hip_avmm:CraWaitRequest_o -> mm_interconnect_1:pcie_hip_avmm_Cra_waitrequest
	wire   [13:0] mm_interconnect_1_pcie_hip_avmm_cra_address;                         // mm_interconnect_1:pcie_hip_avmm_Cra_address -> pcie_hip_avmm:CraAddress_i
	wire          mm_interconnect_1_pcie_hip_avmm_cra_read;                            // mm_interconnect_1:pcie_hip_avmm_Cra_read -> pcie_hip_avmm:CraRead
	wire    [3:0] mm_interconnect_1_pcie_hip_avmm_cra_byteenable;                      // mm_interconnect_1:pcie_hip_avmm_Cra_byteenable -> pcie_hip_avmm:CraByteEnable_i
	wire          mm_interconnect_1_pcie_hip_avmm_cra_write;                           // mm_interconnect_1:pcie_hip_avmm_Cra_write -> pcie_hip_avmm:CraWrite
	wire   [31:0] mm_interconnect_1_pcie_hip_avmm_cra_writedata;                       // mm_interconnect_1:pcie_hip_avmm_Cra_writedata -> pcie_hip_avmm:CraWriteData_i
	wire   [31:0] mm_interconnect_1_performance_counter_0_control_slave_readdata;      // performance_counter_0:readdata -> mm_interconnect_1:performance_counter_0_control_slave_readdata
	wire    [2:0] mm_interconnect_1_performance_counter_0_control_slave_address;       // mm_interconnect_1:performance_counter_0_control_slave_address -> performance_counter_0:address
	wire          mm_interconnect_1_performance_counter_0_control_slave_begintransfer; // mm_interconnect_1:performance_counter_0_control_slave_begintransfer -> performance_counter_0:begintransfer
	wire          mm_interconnect_1_performance_counter_0_control_slave_write;         // mm_interconnect_1:performance_counter_0_control_slave_write -> performance_counter_0:write
	wire   [31:0] mm_interconnect_1_performance_counter_0_control_slave_writedata;     // mm_interconnect_1:performance_counter_0_control_slave_writedata -> performance_counter_0:writedata
	wire   [31:0] mm_interconnect_1_msgdma_0_csr_readdata;                             // msgdma_0:csr_readdata -> mm_interconnect_1:msgdma_0_csr_readdata
	wire    [2:0] mm_interconnect_1_msgdma_0_csr_address;                              // mm_interconnect_1:msgdma_0_csr_address -> msgdma_0:csr_address
	wire          mm_interconnect_1_msgdma_0_csr_read;                                 // mm_interconnect_1:msgdma_0_csr_read -> msgdma_0:csr_read
	wire    [3:0] mm_interconnect_1_msgdma_0_csr_byteenable;                           // mm_interconnect_1:msgdma_0_csr_byteenable -> msgdma_0:csr_byteenable
	wire          mm_interconnect_1_msgdma_0_csr_write;                                // mm_interconnect_1:msgdma_0_csr_write -> msgdma_0:csr_write
	wire   [31:0] mm_interconnect_1_msgdma_0_csr_writedata;                            // mm_interconnect_1:msgdma_0_csr_writedata -> msgdma_0:csr_writedata
	wire   [31:0] mm_interconnect_1_msi_to_gic_gen_0_csr_readdata;                     // msi_to_gic_gen_0:csr_rddata -> mm_interconnect_1:msi_to_gic_gen_0_csr_readdata
	wire    [1:0] mm_interconnect_1_msi_to_gic_gen_0_csr_address;                      // mm_interconnect_1:msi_to_gic_gen_0_csr_address -> msi_to_gic_gen_0:csr_addr
	wire          mm_interconnect_1_msi_to_gic_gen_0_csr_read;                         // mm_interconnect_1:msi_to_gic_gen_0_csr_read -> msi_to_gic_gen_0:csr_read
	wire          mm_interconnect_1_msi_to_gic_gen_0_csr_write;                        // mm_interconnect_1:msi_to_gic_gen_0_csr_write -> msi_to_gic_gen_0:csr_write
	wire   [31:0] mm_interconnect_1_msi_to_gic_gen_0_csr_writedata;                    // mm_interconnect_1:msi_to_gic_gen_0_csr_writedata -> msi_to_gic_gen_0:csr_wrdata
	wire          mm_interconnect_1_msgdma_0_descriptor_slave_waitrequest;             // msgdma_0:descriptor_slave_waitrequest -> mm_interconnect_1:msgdma_0_descriptor_slave_waitrequest
	wire   [15:0] mm_interconnect_1_msgdma_0_descriptor_slave_byteenable;              // mm_interconnect_1:msgdma_0_descriptor_slave_byteenable -> msgdma_0:descriptor_slave_byteenable
	wire          mm_interconnect_1_msgdma_0_descriptor_slave_write;                   // mm_interconnect_1:msgdma_0_descriptor_slave_write -> msgdma_0:descriptor_slave_write
	wire  [127:0] mm_interconnect_1_msgdma_0_descriptor_slave_writedata;               // mm_interconnect_1:msgdma_0_descriptor_slave_writedata -> msgdma_0:descriptor_slave_writedata
	wire   [31:0] mm_interconnect_1_msi_to_gic_gen_0_vector_slave_readdata;            // msi_to_gic_gen_0:avmm_rddata -> mm_interconnect_1:msi_to_gic_gen_0_vector_slave_readdata
	wire    [4:0] mm_interconnect_1_msi_to_gic_gen_0_vector_slave_address;             // mm_interconnect_1:msi_to_gic_gen_0_vector_slave_address -> msi_to_gic_gen_0:avmm_addr
	wire          mm_interconnect_1_msi_to_gic_gen_0_vector_slave_read;                // mm_interconnect_1:msi_to_gic_gen_0_vector_slave_read -> msi_to_gic_gen_0:avmm_read
	wire          mm_interconnect_1_msi_to_gic_gen_0_vector_slave_write;               // mm_interconnect_1:msi_to_gic_gen_0_vector_slave_write -> msi_to_gic_gen_0:avmm_write
	wire   [31:0] mm_interconnect_1_msi_to_gic_gen_0_vector_slave_writedata;           // mm_interconnect_1:msi_to_gic_gen_0_vector_slave_writedata -> msi_to_gic_gen_0:avmm_wrdata
	wire          ccb_h2f_m0_waitrequest;                                              // mm_interconnect_2:ccb_h2f_m0_waitrequest -> ccb_h2f:m0_waitrequest
	wire   [63:0] ccb_h2f_m0_readdata;                                                 // mm_interconnect_2:ccb_h2f_m0_readdata -> ccb_h2f:m0_readdata
	wire          ccb_h2f_m0_debugaccess;                                              // ccb_h2f:m0_debugaccess -> mm_interconnect_2:ccb_h2f_m0_debugaccess
	wire   [27:0] ccb_h2f_m0_address;                                                  // ccb_h2f:m0_address -> mm_interconnect_2:ccb_h2f_m0_address
	wire          ccb_h2f_m0_read;                                                     // ccb_h2f:m0_read -> mm_interconnect_2:ccb_h2f_m0_read
	wire    [7:0] ccb_h2f_m0_byteenable;                                               // ccb_h2f:m0_byteenable -> mm_interconnect_2:ccb_h2f_m0_byteenable
	wire          ccb_h2f_m0_readdatavalid;                                            // mm_interconnect_2:ccb_h2f_m0_readdatavalid -> ccb_h2f:m0_readdatavalid
	wire   [63:0] ccb_h2f_m0_writedata;                                                // ccb_h2f:m0_writedata -> mm_interconnect_2:ccb_h2f_m0_writedata
	wire          ccb_h2f_m0_write;                                                    // ccb_h2f:m0_write -> mm_interconnect_2:ccb_h2f_m0_write
	wire    [6:0] ccb_h2f_m0_burstcount;                                               // ccb_h2f:m0_burstcount -> mm_interconnect_2:ccb_h2f_m0_burstcount
	wire          pb_msgdma_2_txs_m0_waitrequest;                                      // mm_interconnect_2:pb_msgdma_2_txs_m0_waitrequest -> pb_msgdma_2_txs:m0_waitrequest
	wire   [63:0] pb_msgdma_2_txs_m0_readdata;                                         // mm_interconnect_2:pb_msgdma_2_txs_m0_readdata -> pb_msgdma_2_txs:m0_readdata
	wire          pb_msgdma_2_txs_m0_debugaccess;                                      // pb_msgdma_2_txs:m0_debugaccess -> mm_interconnect_2:pb_msgdma_2_txs_m0_debugaccess
	wire   [27:0] pb_msgdma_2_txs_m0_address;                                          // pb_msgdma_2_txs:m0_address -> mm_interconnect_2:pb_msgdma_2_txs_m0_address
	wire          pb_msgdma_2_txs_m0_read;                                             // pb_msgdma_2_txs:m0_read -> mm_interconnect_2:pb_msgdma_2_txs_m0_read
	wire    [7:0] pb_msgdma_2_txs_m0_byteenable;                                       // pb_msgdma_2_txs:m0_byteenable -> mm_interconnect_2:pb_msgdma_2_txs_m0_byteenable
	wire          pb_msgdma_2_txs_m0_readdatavalid;                                    // mm_interconnect_2:pb_msgdma_2_txs_m0_readdatavalid -> pb_msgdma_2_txs:m0_readdatavalid
	wire   [63:0] pb_msgdma_2_txs_m0_writedata;                                        // pb_msgdma_2_txs:m0_writedata -> mm_interconnect_2:pb_msgdma_2_txs_m0_writedata
	wire          pb_msgdma_2_txs_m0_write;                                            // pb_msgdma_2_txs:m0_write -> mm_interconnect_2:pb_msgdma_2_txs_m0_write
	wire    [6:0] pb_msgdma_2_txs_m0_burstcount;                                       // pb_msgdma_2_txs:m0_burstcount -> mm_interconnect_2:pb_msgdma_2_txs_m0_burstcount
	wire          mm_interconnect_2_pcie_hip_avmm_txs_chipselect;                      // mm_interconnect_2:pcie_hip_avmm_Txs_chipselect -> pcie_hip_avmm:TxsChipSelect_i
	wire   [63:0] mm_interconnect_2_pcie_hip_avmm_txs_readdata;                        // pcie_hip_avmm:TxsReadData_o -> mm_interconnect_2:pcie_hip_avmm_Txs_readdata
	wire          mm_interconnect_2_pcie_hip_avmm_txs_waitrequest;                     // pcie_hip_avmm:TxsWaitRequest_o -> mm_interconnect_2:pcie_hip_avmm_Txs_waitrequest
	wire   [27:0] mm_interconnect_2_pcie_hip_avmm_txs_address;                         // mm_interconnect_2:pcie_hip_avmm_Txs_address -> pcie_hip_avmm:TxsAddress_i
	wire          mm_interconnect_2_pcie_hip_avmm_txs_read;                            // mm_interconnect_2:pcie_hip_avmm_Txs_read -> pcie_hip_avmm:TxsRead_i
	wire    [7:0] mm_interconnect_2_pcie_hip_avmm_txs_byteenable;                      // mm_interconnect_2:pcie_hip_avmm_Txs_byteenable -> pcie_hip_avmm:TxsByteEnable_i
	wire          mm_interconnect_2_pcie_hip_avmm_txs_readdatavalid;                   // pcie_hip_avmm:TxsReadDataValid_o -> mm_interconnect_2:pcie_hip_avmm_Txs_readdatavalid
	wire          mm_interconnect_2_pcie_hip_avmm_txs_write;                           // mm_interconnect_2:pcie_hip_avmm_Txs_write -> pcie_hip_avmm:TxsWrite_i
	wire   [63:0] mm_interconnect_2_pcie_hip_avmm_txs_writedata;                       // mm_interconnect_2:pcie_hip_avmm_Txs_writedata -> pcie_hip_avmm:TxsWriteData_i
	wire    [6:0] mm_interconnect_2_pcie_hip_avmm_txs_burstcount;                      // mm_interconnect_2:pcie_hip_avmm_Txs_burstcount -> pcie_hip_avmm:TxsBurstCount_i
	wire          pb_f2sdram_m0_waitrequest;                                           // mm_interconnect_3:pb_f2sdram_m0_waitrequest -> pb_f2sdram:m0_waitrequest
	wire   [63:0] pb_f2sdram_m0_readdata;                                              // mm_interconnect_3:pb_f2sdram_m0_readdata -> pb_f2sdram:m0_readdata
	wire          pb_f2sdram_m0_debugaccess;                                           // pb_f2sdram:m0_debugaccess -> mm_interconnect_3:pb_f2sdram_m0_debugaccess
	wire   [29:0] pb_f2sdram_m0_address;                                               // pb_f2sdram:m0_address -> mm_interconnect_3:pb_f2sdram_m0_address
	wire          pb_f2sdram_m0_read;                                                  // pb_f2sdram:m0_read -> mm_interconnect_3:pb_f2sdram_m0_read
	wire    [7:0] pb_f2sdram_m0_byteenable;                                            // pb_f2sdram:m0_byteenable -> mm_interconnect_3:pb_f2sdram_m0_byteenable
	wire          pb_f2sdram_m0_readdatavalid;                                         // mm_interconnect_3:pb_f2sdram_m0_readdatavalid -> pb_f2sdram:m0_readdatavalid
	wire   [63:0] pb_f2sdram_m0_writedata;                                             // pb_f2sdram:m0_writedata -> mm_interconnect_3:pb_f2sdram_m0_writedata
	wire          pb_f2sdram_m0_write;                                                 // pb_f2sdram:m0_write -> mm_interconnect_3:pb_f2sdram_m0_write
	wire    [6:0] pb_f2sdram_m0_burstcount;                                            // pb_f2sdram:m0_burstcount -> mm_interconnect_3:pb_f2sdram_m0_burstcount
	wire  [255:0] mm_interconnect_3_add_x_f2sdram_windowed_slave_readdata;             // add_x_f2sdram:avs_s0_readdata -> mm_interconnect_3:add_x_f2sdram_windowed_slave_readdata
	wire          mm_interconnect_3_add_x_f2sdram_windowed_slave_waitrequest;          // add_x_f2sdram:avs_s0_waitrequest -> mm_interconnect_3:add_x_f2sdram_windowed_slave_waitrequest
	wire   [24:0] mm_interconnect_3_add_x_f2sdram_windowed_slave_address;              // mm_interconnect_3:add_x_f2sdram_windowed_slave_address -> add_x_f2sdram:avs_s0_address
	wire          mm_interconnect_3_add_x_f2sdram_windowed_slave_read;                 // mm_interconnect_3:add_x_f2sdram_windowed_slave_read -> add_x_f2sdram:avs_s0_read
	wire   [31:0] mm_interconnect_3_add_x_f2sdram_windowed_slave_byteenable;           // mm_interconnect_3:add_x_f2sdram_windowed_slave_byteenable -> add_x_f2sdram:avs_s0_byteenable
	wire          mm_interconnect_3_add_x_f2sdram_windowed_slave_readdatavalid;        // add_x_f2sdram:avs_s0_readdatavalid -> mm_interconnect_3:add_x_f2sdram_windowed_slave_readdatavalid
	wire          mm_interconnect_3_add_x_f2sdram_windowed_slave_write;                // mm_interconnect_3:add_x_f2sdram_windowed_slave_write -> add_x_f2sdram:avs_s0_write
	wire  [255:0] mm_interconnect_3_add_x_f2sdram_windowed_slave_writedata;            // mm_interconnect_3:add_x_f2sdram_windowed_slave_writedata -> add_x_f2sdram:avs_s0_writedata
	wire    [7:0] mm_interconnect_3_add_x_f2sdram_windowed_slave_burstcount;           // mm_interconnect_3:add_x_f2sdram_windowed_slave_burstcount -> add_x_f2sdram:avs_s0_burstcount
	wire   [15:0] pcie_hip_avmm_rxmirq_irq;                                            // irq_mapper:sender_irq -> pcie_hip_avmm:RxmIrq_i
	wire          rst_controller_reset_out_reset;                                      // rst_controller:reset_out -> [ccb_h2f:s0_reset, mm_interconnect_1:performance_counter_0_reset_reset_bridge_in_reset_reset, msi_to_gic_gen_0:reset_n, performance_counter_0:reset_n]
	wire          rst_controller_001_reset_out_reset;                                  // rst_controller_001:reset_out -> custom_reset_synchronizer_0:reset_in
	wire          pcie_hip_avmm_nreset_status_reset;                                   // pcie_hip_avmm:reset_status -> [rst_controller_001:reset_in1, rst_controller_002:reset_in0]
	wire          rst_controller_002_reset_out_reset;                                  // rst_controller_002:reset_out -> [irq_mapper:reset, mm_interconnect_0:pcie_hip_avmm_RP_Master_translator_reset_reset_bridge_in_reset_reset, mm_interconnect_1:pcie_hip_avmm_Cra_translator_reset_reset_bridge_in_reset_reset, mm_interconnect_2:pcie_hip_avmm_Txs_translator_reset_reset_bridge_in_reset_reset]

	altera_address_span_extender #(
		.DATA_WIDTH           (256),
		.BYTEENABLE_WIDTH     (32),
		.MASTER_ADDRESS_WIDTH (32),
		.SLAVE_ADDRESS_WIDTH  (25),
		.SLAVE_ADDRESS_SHIFT  (5),
		.BURSTCOUNT_WIDTH     (8),
		.CNTL_ADDRESS_WIDTH   (1),
		.SUB_WINDOW_COUNT     (1),
		.MASTER_ADDRESS_DEF   (64'b0000000000000000000000000000000000000000000000000000000000000000)
	) add_x_f2sdram (
		.clk                  (coreclk_fanout_clk_clk),                                               //           clock.clk
		.reset                (custom_reset_synchronizer_0_reset_out_reset),                          //           reset.reset
		.avs_s0_address       (mm_interconnect_3_add_x_f2sdram_windowed_slave_address),               //  windowed_slave.address
		.avs_s0_read          (mm_interconnect_3_add_x_f2sdram_windowed_slave_read),                  //                .read
		.avs_s0_readdata      (mm_interconnect_3_add_x_f2sdram_windowed_slave_readdata),              //                .readdata
		.avs_s0_write         (mm_interconnect_3_add_x_f2sdram_windowed_slave_write),                 //                .write
		.avs_s0_writedata     (mm_interconnect_3_add_x_f2sdram_windowed_slave_writedata),             //                .writedata
		.avs_s0_readdatavalid (mm_interconnect_3_add_x_f2sdram_windowed_slave_readdatavalid),         //                .readdatavalid
		.avs_s0_waitrequest   (mm_interconnect_3_add_x_f2sdram_windowed_slave_waitrequest),           //                .waitrequest
		.avs_s0_byteenable    (mm_interconnect_3_add_x_f2sdram_windowed_slave_byteenable),            //                .byteenable
		.avs_s0_burstcount    (mm_interconnect_3_add_x_f2sdram_windowed_slave_burstcount),            //                .burstcount
		.avm_m0_address       (address_span_extender_0_expanded_master_address),                      // expanded_master.address
		.avm_m0_read          (address_span_extender_0_expanded_master_read),                         //                .read
		.avm_m0_waitrequest   (address_span_extender_0_expanded_master_waitrequest),                  //                .waitrequest
		.avm_m0_readdata      (address_span_extender_0_expanded_master_readdata),                     //                .readdata
		.avm_m0_write         (address_span_extender_0_expanded_master_write),                        //                .write
		.avm_m0_writedata     (address_span_extender_0_expanded_master_writedata),                    //                .writedata
		.avm_m0_readdatavalid (address_span_extender_0_expanded_master_readdatavalid),                //                .readdatavalid
		.avm_m0_byteenable    (address_span_extender_0_expanded_master_byteenable),                   //                .byteenable
		.avm_m0_burstcount    (address_span_extender_0_expanded_master_burstcount),                   //                .burstcount
		.avs_cntl_address     (1'b0),                                                                 //     (terminated)
		.avs_cntl_read        (1'b0),                                                                 //     (terminated)
		.avs_cntl_readdata    (),                                                                     //     (terminated)
		.avs_cntl_write       (1'b0),                                                                 //     (terminated)
		.avs_cntl_writedata   (64'b0000000000000000000000000000000000000000000000000000000000000000), //     (terminated)
		.avs_cntl_byteenable  (8'b00000000)                                                           //     (terminated)
	);

	alt_xcvr_reconfig #(
		.device_family                 ("Cyclone V"),
		.number_of_reconfig_interfaces (2),
		.enable_offset                 (1),
		.enable_lc                     (0),
		.enable_dcd                    (0),
		.enable_dcd_power_up           (1),
		.enable_analog                 (1),
		.enable_eyemon                 (0),
		.enable_ber                    (0),
		.enable_dfe                    (0),
		.enable_adce                   (0),
		.enable_mif                    (0),
		.enable_pll                    (0)
	) alt_xcvr_reconfig_0 (
		.reconfig_busy             (alt_xcvr_reconfig_0_reconfig_busy_reconfig_busy),       //      reconfig_busy.reconfig_busy
		.mgmt_clk_clk              (coreclk_fanout_clk_clk),                                //       mgmt_clk_clk.clk
		.mgmt_rst_reset            (custom_reset_synchronizer_0_reset_out_reset),           //     mgmt_rst_reset.reset
		.reconfig_mgmt_address     (alt_xcvr_reconfig_0_reconfig_mgmt_address),             //      reconfig_mgmt.address
		.reconfig_mgmt_read        (alt_xcvr_reconfig_0_reconfig_mgmt_read),                //                   .read
		.reconfig_mgmt_readdata    (alt_xcvr_reconfig_0_reconfig_mgmt_readdata),            //                   .readdata
		.reconfig_mgmt_waitrequest (alt_xcvr_reconfig_0_reconfig_mgmt_waitrequest),         //                   .waitrequest
		.reconfig_mgmt_write       (alt_xcvr_reconfig_0_reconfig_mgmt_write),               //                   .write
		.reconfig_mgmt_writedata   (alt_xcvr_reconfig_0_reconfig_mgmt_writedata),           //                   .writedata
		.reconfig_to_xcvr          (alt_xcvr_reconfig_0_reconfig_to_xcvr_reconfig_to_xcvr), //   reconfig_to_xcvr.reconfig_to_xcvr
		.reconfig_from_xcvr        (pcie_hip_avmm_reconfig_from_xcvr_reconfig_from_xcvr),   // reconfig_from_xcvr.reconfig_from_xcvr
		.tx_cal_busy               (),                                                      //        (terminated)
		.rx_cal_busy               (),                                                      //        (terminated)
		.cal_busy_in               (1'b0),                                                  //        (terminated)
		.reconfig_mif_address      (),                                                      //        (terminated)
		.reconfig_mif_read         (),                                                      //        (terminated)
		.reconfig_mif_readdata     (16'b0000000000000000),                                  //        (terminated)
		.reconfig_mif_waitrequest  (1'b0)                                                   //        (terminated)
	);

	altera_avalon_mm_clock_crossing_bridge #(
		.DATA_WIDTH          (64),
		.SYMBOL_WIDTH        (8),
		.HDL_ADDR_WIDTH      (28),
		.BURSTCOUNT_WIDTH    (7),
		.COMMAND_FIFO_DEPTH  (4),
		.RESPONSE_FIFO_DEPTH (128),
		.MASTER_SYNC_DEPTH   (2),
		.SLAVE_SYNC_DEPTH    (2)
	) ccb_h2f (
		.m0_clk           (coreclk_fanout_clk_clk),                      //   m0_clk.clk
		.m0_reset         (custom_reset_synchronizer_0_reset_out_reset), // m0_reset.reset
		.s0_clk           (clk_clk),                                     //   s0_clk.clk
		.s0_reset         (rst_controller_reset_out_reset),              // s0_reset.reset
		.s0_waitrequest   (ccb_h2f_s0_waitrequest),                      //       s0.waitrequest
		.s0_readdata      (ccb_h2f_s0_readdata),                         //         .readdata
		.s0_readdatavalid (ccb_h2f_s0_readdatavalid),                    //         .readdatavalid
		.s0_burstcount    (ccb_h2f_s0_burstcount),                       //         .burstcount
		.s0_writedata     (ccb_h2f_s0_writedata),                        //         .writedata
		.s0_address       (ccb_h2f_s0_address),                          //         .address
		.s0_write         (ccb_h2f_s0_write),                            //         .write
		.s0_read          (ccb_h2f_s0_read),                             //         .read
		.s0_byteenable    (ccb_h2f_s0_byteenable),                       //         .byteenable
		.s0_debugaccess   (ccb_h2f_s0_debugaccess),                      //         .debugaccess
		.m0_waitrequest   (ccb_h2f_m0_waitrequest),                      //       m0.waitrequest
		.m0_readdata      (ccb_h2f_m0_readdata),                         //         .readdata
		.m0_readdatavalid (ccb_h2f_m0_readdatavalid),                    //         .readdatavalid
		.m0_burstcount    (ccb_h2f_m0_burstcount),                       //         .burstcount
		.m0_writedata     (ccb_h2f_m0_writedata),                        //         .writedata
		.m0_address       (ccb_h2f_m0_address),                          //         .address
		.m0_write         (ccb_h2f_m0_write),                            //         .write
		.m0_read          (ccb_h2f_m0_read),                             //         .read
		.m0_byteenable    (ccb_h2f_m0_byteenable),                       //         .byteenable
		.m0_debugaccess   (ccb_h2f_m0_debugaccess)                       //         .debugaccess
	);

	reset_sync_block #(
		.SYNC_DEPTH             (3),
		.ADDITIONAL_DEPTH       (10),
		.DISABLE_GLOBAL_NETWORK (1),
		.SYNC_BOTH_EDGES        (0)
	) custom_reset_synchronizer_0 (
		.clk_in    (pcie_hip_avmm_coreclkout_clk),                //  clock_in.clk
		.reset_in  (rst_controller_001_reset_out_reset),          //  reset_in.reset
		.clk_out   (coreclk_fanout_clk_clk),                      // clock_out.clk
		.reset_out (custom_reset_synchronizer_0_reset_out_reset)  // reset_out.reset
	);

	soc_system_pcie_0_msgdma_0 msgdma_0 (
		.mm_read_address              (msgdma_0_mm_read_address),                                //          mm_read.address
		.mm_read_read                 (msgdma_0_mm_read_read),                                   //                 .read
		.mm_read_byteenable           (msgdma_0_mm_read_byteenable),                             //                 .byteenable
		.mm_read_readdata             (msgdma_0_mm_read_readdata),                               //                 .readdata
		.mm_read_waitrequest          (msgdma_0_mm_read_waitrequest),                            //                 .waitrequest
		.mm_read_readdatavalid        (msgdma_0_mm_read_readdatavalid),                          //                 .readdatavalid
		.mm_read_burstcount           (msgdma_0_mm_read_burstcount),                             //                 .burstcount
		.mm_write_address             (msgdma_0_mm_write_address),                               //         mm_write.address
		.mm_write_write               (msgdma_0_mm_write_write),                                 //                 .write
		.mm_write_byteenable          (msgdma_0_mm_write_byteenable),                            //                 .byteenable
		.mm_write_writedata           (msgdma_0_mm_write_writedata),                             //                 .writedata
		.mm_write_waitrequest         (msgdma_0_mm_write_waitrequest),                           //                 .waitrequest
		.mm_write_burstcount          (msgdma_0_mm_write_burstcount),                            //                 .burstcount
		.clock_clk                    (coreclk_fanout_clk_clk),                                  //            clock.clk
		.reset_n_reset_n              (~custom_reset_synchronizer_0_reset_out_reset),            //          reset_n.reset_n
		.csr_writedata                (mm_interconnect_1_msgdma_0_csr_writedata),                //              csr.writedata
		.csr_write                    (mm_interconnect_1_msgdma_0_csr_write),                    //                 .write
		.csr_byteenable               (mm_interconnect_1_msgdma_0_csr_byteenable),               //                 .byteenable
		.csr_readdata                 (mm_interconnect_1_msgdma_0_csr_readdata),                 //                 .readdata
		.csr_read                     (mm_interconnect_1_msgdma_0_csr_read),                     //                 .read
		.csr_address                  (mm_interconnect_1_msgdma_0_csr_address),                  //                 .address
		.descriptor_slave_write       (mm_interconnect_1_msgdma_0_descriptor_slave_write),       // descriptor_slave.write
		.descriptor_slave_waitrequest (mm_interconnect_1_msgdma_0_descriptor_slave_waitrequest), //                 .waitrequest
		.descriptor_slave_writedata   (mm_interconnect_1_msgdma_0_descriptor_slave_writedata),   //                 .writedata
		.descriptor_slave_byteenable  (mm_interconnect_1_msgdma_0_descriptor_slave_byteenable),  //                 .byteenable
		.csr_irq_irq                  (msgdma_0_csr_irq_irq)                                     //          csr_irq.irq
	);

	altera_msi_to_gic_gen #(
		.DEVICE_FAMILY    ("Cyclone V"),
		.MSG_DATA_WORD    (32),
		.ADDR_WIDTH       (5),
		.DATA_ENTRY_DEPTH (4),
		.FIFO_DEPTH       (4),
		.MEMORY_TYPE      ("RAM_BLOCK_TYPE=MLAB")
	) msi_to_gic_gen_0 (
		.clk         (clk_clk),                                                   //            clock.clk
		.reset_n     (~rst_controller_reset_out_reset),                           //            reset.reset_n
		.csr_write   (mm_interconnect_1_msi_to_gic_gen_0_csr_write),              //              csr.write
		.csr_read    (mm_interconnect_1_msi_to_gic_gen_0_csr_read),               //                 .read
		.csr_addr    (mm_interconnect_1_msi_to_gic_gen_0_csr_address),            //                 .address
		.csr_wrdata  (mm_interconnect_1_msi_to_gic_gen_0_csr_writedata),          //                 .writedata
		.csr_rddata  (mm_interconnect_1_msi_to_gic_gen_0_csr_readdata),           //                 .readdata
		.avmm_addr   (mm_interconnect_1_msi_to_gic_gen_0_vector_slave_address),   //     vector_slave.address
		.avmm_wrdata (mm_interconnect_1_msi_to_gic_gen_0_vector_slave_writedata), //                 .writedata
		.avmm_rddata (mm_interconnect_1_msi_to_gic_gen_0_vector_slave_readdata),  //                 .readdata
		.avmm_write  (mm_interconnect_1_msi_to_gic_gen_0_vector_slave_write),     //                 .write
		.avmm_read   (mm_interconnect_1_msi_to_gic_gen_0_vector_slave_read),      //                 .read
		.irq         (msi_to_gic_gen_0_interrupt_sender_irq)                      // interrupt_sender.irq
	);

	altera_avalon_mm_bridge #(
		.DATA_WIDTH        (64),
		.SYMBOL_WIDTH      (8),
		.HDL_ADDR_WIDTH    (16),
		.BURSTCOUNT_WIDTH  (7),
		.PIPELINE_COMMAND  (1),
		.PIPELINE_RESPONSE (1)
	) pb_2_ocm (
		.clk              (coreclk_fanout_clk_clk),                      //   clk.clk
		.reset            (custom_reset_synchronizer_0_reset_out_reset), // reset.reset
		.s0_waitrequest   (mm_interconnect_0_pb_2_ocm_s0_waitrequest),   //    s0.waitrequest
		.s0_readdata      (mm_interconnect_0_pb_2_ocm_s0_readdata),      //      .readdata
		.s0_readdatavalid (mm_interconnect_0_pb_2_ocm_s0_readdatavalid), //      .readdatavalid
		.s0_burstcount    (mm_interconnect_0_pb_2_ocm_s0_burstcount),    //      .burstcount
		.s0_writedata     (mm_interconnect_0_pb_2_ocm_s0_writedata),     //      .writedata
		.s0_address       (mm_interconnect_0_pb_2_ocm_s0_address),       //      .address
		.s0_write         (mm_interconnect_0_pb_2_ocm_s0_write),         //      .write
		.s0_read          (mm_interconnect_0_pb_2_ocm_s0_read),          //      .read
		.s0_byteenable    (mm_interconnect_0_pb_2_ocm_s0_byteenable),    //      .byteenable
		.s0_debugaccess   (mm_interconnect_0_pb_2_ocm_s0_debugaccess),   //      .debugaccess
		.m0_waitrequest   (pb_2_ocm_m0_waitrequest),                     //    m0.waitrequest
		.m0_readdata      (pb_2_ocm_m0_readdata),                        //      .readdata
		.m0_readdatavalid (pb_2_ocm_m0_readdatavalid),                   //      .readdatavalid
		.m0_burstcount    (pb_2_ocm_m0_burstcount),                      //      .burstcount
		.m0_writedata     (pb_2_ocm_m0_writedata),                       //      .writedata
		.m0_address       (pb_2_ocm_m0_address),                         //      .address
		.m0_write         (pb_2_ocm_m0_write),                           //      .write
		.m0_read          (pb_2_ocm_m0_read),                            //      .read
		.m0_byteenable    (pb_2_ocm_m0_byteenable),                      //      .byteenable
		.m0_debugaccess   (pb_2_ocm_m0_debugaccess),                     //      .debugaccess
		.s0_response      (),                                            // (terminated)
		.m0_response      (2'b00)                                        // (terminated)
	);

	altera_avalon_mm_bridge #(
		.DATA_WIDTH        (64),
		.SYMBOL_WIDTH      (8),
		.HDL_ADDR_WIDTH    (30),
		.BURSTCOUNT_WIDTH  (7),
		.PIPELINE_COMMAND  (1),
		.PIPELINE_RESPONSE (1)
	) pb_f2sdram (
		.clk              (coreclk_fanout_clk_clk),                        //   clk.clk
		.reset            (custom_reset_synchronizer_0_reset_out_reset),   // reset.reset
		.s0_waitrequest   (mm_interconnect_0_pb_f2sdram_s0_waitrequest),   //    s0.waitrequest
		.s0_readdata      (mm_interconnect_0_pb_f2sdram_s0_readdata),      //      .readdata
		.s0_readdatavalid (mm_interconnect_0_pb_f2sdram_s0_readdatavalid), //      .readdatavalid
		.s0_burstcount    (mm_interconnect_0_pb_f2sdram_s0_burstcount),    //      .burstcount
		.s0_writedata     (mm_interconnect_0_pb_f2sdram_s0_writedata),     //      .writedata
		.s0_address       (mm_interconnect_0_pb_f2sdram_s0_address),       //      .address
		.s0_write         (mm_interconnect_0_pb_f2sdram_s0_write),         //      .write
		.s0_read          (mm_interconnect_0_pb_f2sdram_s0_read),          //      .read
		.s0_byteenable    (mm_interconnect_0_pb_f2sdram_s0_byteenable),    //      .byteenable
		.s0_debugaccess   (mm_interconnect_0_pb_f2sdram_s0_debugaccess),   //      .debugaccess
		.m0_waitrequest   (pb_f2sdram_m0_waitrequest),                     //    m0.waitrequest
		.m0_readdata      (pb_f2sdram_m0_readdata),                        //      .readdata
		.m0_readdatavalid (pb_f2sdram_m0_readdatavalid),                   //      .readdatavalid
		.m0_burstcount    (pb_f2sdram_m0_burstcount),                      //      .burstcount
		.m0_writedata     (pb_f2sdram_m0_writedata),                       //      .writedata
		.m0_address       (pb_f2sdram_m0_address),                         //      .address
		.m0_write         (pb_f2sdram_m0_write),                           //      .write
		.m0_read          (pb_f2sdram_m0_read),                            //      .read
		.m0_byteenable    (pb_f2sdram_m0_byteenable),                      //      .byteenable
		.m0_debugaccess   (pb_f2sdram_m0_debugaccess),                     //      .debugaccess
		.s0_response      (),                                              // (terminated)
		.m0_response      (2'b00)                                          // (terminated)
	);

	altera_avalon_mm_bridge #(
		.DATA_WIDTH        (32),
		.SYMBOL_WIDTH      (8),
		.HDL_ADDR_WIDTH    (15),
		.BURSTCOUNT_WIDTH  (1),
		.PIPELINE_COMMAND  (1),
		.PIPELINE_RESPONSE (1)
	) pb_lwh2f_pcie (
		.clk              (coreclk_fanout_clk_clk),                      //   clk.clk
		.reset            (custom_reset_synchronizer_0_reset_out_reset), // reset.reset
		.s0_waitrequest   (pb_lwh2f_pcie_s0_waitrequest),                //    s0.waitrequest
		.s0_readdata      (pb_lwh2f_pcie_s0_readdata),                   //      .readdata
		.s0_readdatavalid (pb_lwh2f_pcie_s0_readdatavalid),              //      .readdatavalid
		.s0_burstcount    (pb_lwh2f_pcie_s0_burstcount),                 //      .burstcount
		.s0_writedata     (pb_lwh2f_pcie_s0_writedata),                  //      .writedata
		.s0_address       (pb_lwh2f_pcie_s0_address),                    //      .address
		.s0_write         (pb_lwh2f_pcie_s0_write),                      //      .write
		.s0_read          (pb_lwh2f_pcie_s0_read),                       //      .read
		.s0_byteenable    (pb_lwh2f_pcie_s0_byteenable),                 //      .byteenable
		.s0_debugaccess   (pb_lwh2f_pcie_s0_debugaccess),                //      .debugaccess
		.m0_waitrequest   (pb_lwh2f_pcie_m0_waitrequest),                //    m0.waitrequest
		.m0_readdata      (pb_lwh2f_pcie_m0_readdata),                   //      .readdata
		.m0_readdatavalid (pb_lwh2f_pcie_m0_readdatavalid),              //      .readdatavalid
		.m0_burstcount    (pb_lwh2f_pcie_m0_burstcount),                 //      .burstcount
		.m0_writedata     (pb_lwh2f_pcie_m0_writedata),                  //      .writedata
		.m0_address       (pb_lwh2f_pcie_m0_address),                    //      .address
		.m0_write         (pb_lwh2f_pcie_m0_write),                      //      .write
		.m0_read          (pb_lwh2f_pcie_m0_read),                       //      .read
		.m0_byteenable    (pb_lwh2f_pcie_m0_byteenable),                 //      .byteenable
		.m0_debugaccess   (pb_lwh2f_pcie_m0_debugaccess),                //      .debugaccess
		.s0_response      (),                                            // (terminated)
		.m0_response      (2'b00)                                        // (terminated)
	);

	altera_avalon_mm_bridge #(
		.DATA_WIDTH        (64),
		.SYMBOL_WIDTH      (8),
		.HDL_ADDR_WIDTH    (28),
		.BURSTCOUNT_WIDTH  (7),
		.PIPELINE_COMMAND  (1),
		.PIPELINE_RESPONSE (1)
	) pb_msgdma_2_txs (
		.clk              (coreclk_fanout_clk_clk),                             //   clk.clk
		.reset            (custom_reset_synchronizer_0_reset_out_reset),        // reset.reset
		.s0_waitrequest   (mm_interconnect_0_pb_msgdma_2_txs_s0_waitrequest),   //    s0.waitrequest
		.s0_readdata      (mm_interconnect_0_pb_msgdma_2_txs_s0_readdata),      //      .readdata
		.s0_readdatavalid (mm_interconnect_0_pb_msgdma_2_txs_s0_readdatavalid), //      .readdatavalid
		.s0_burstcount    (mm_interconnect_0_pb_msgdma_2_txs_s0_burstcount),    //      .burstcount
		.s0_writedata     (mm_interconnect_0_pb_msgdma_2_txs_s0_writedata),     //      .writedata
		.s0_address       (mm_interconnect_0_pb_msgdma_2_txs_s0_address),       //      .address
		.s0_write         (mm_interconnect_0_pb_msgdma_2_txs_s0_write),         //      .write
		.s0_read          (mm_interconnect_0_pb_msgdma_2_txs_s0_read),          //      .read
		.s0_byteenable    (mm_interconnect_0_pb_msgdma_2_txs_s0_byteenable),    //      .byteenable
		.s0_debugaccess   (mm_interconnect_0_pb_msgdma_2_txs_s0_debugaccess),   //      .debugaccess
		.m0_waitrequest   (pb_msgdma_2_txs_m0_waitrequest),                     //    m0.waitrequest
		.m0_readdata      (pb_msgdma_2_txs_m0_readdata),                        //      .readdata
		.m0_readdatavalid (pb_msgdma_2_txs_m0_readdatavalid),                   //      .readdatavalid
		.m0_burstcount    (pb_msgdma_2_txs_m0_burstcount),                      //      .burstcount
		.m0_writedata     (pb_msgdma_2_txs_m0_writedata),                       //      .writedata
		.m0_address       (pb_msgdma_2_txs_m0_address),                         //      .address
		.m0_write         (pb_msgdma_2_txs_m0_write),                           //      .write
		.m0_read          (pb_msgdma_2_txs_m0_read),                            //      .read
		.m0_byteenable    (pb_msgdma_2_txs_m0_byteenable),                      //      .byteenable
		.m0_debugaccess   (pb_msgdma_2_txs_m0_debugaccess),                     //      .debugaccess
		.s0_response      (),                                                   // (terminated)
		.m0_response      (2'b00)                                               // (terminated)
	);

	altera_avalon_mm_bridge #(
		.DATA_WIDTH        (32),
		.SYMBOL_WIDTH      (8),
		.HDL_ADDR_WIDTH    (15),
		.BURSTCOUNT_WIDTH  (1),
		.PIPELINE_COMMAND  (1),
		.PIPELINE_RESPONSE (1)
	) pb_rxm_2_msi (
		.clk              (coreclk_fanout_clk_clk),                          //   clk.clk
		.reset            (custom_reset_synchronizer_0_reset_out_reset),     // reset.reset
		.s0_waitrequest   (mm_interconnect_0_pb_rxm_2_msi_s0_waitrequest),   //    s0.waitrequest
		.s0_readdata      (mm_interconnect_0_pb_rxm_2_msi_s0_readdata),      //      .readdata
		.s0_readdatavalid (mm_interconnect_0_pb_rxm_2_msi_s0_readdatavalid), //      .readdatavalid
		.s0_burstcount    (mm_interconnect_0_pb_rxm_2_msi_s0_burstcount),    //      .burstcount
		.s0_writedata     (mm_interconnect_0_pb_rxm_2_msi_s0_writedata),     //      .writedata
		.s0_address       (mm_interconnect_0_pb_rxm_2_msi_s0_address),       //      .address
		.s0_write         (mm_interconnect_0_pb_rxm_2_msi_s0_write),         //      .write
		.s0_read          (mm_interconnect_0_pb_rxm_2_msi_s0_read),          //      .read
		.s0_byteenable    (mm_interconnect_0_pb_rxm_2_msi_s0_byteenable),    //      .byteenable
		.s0_debugaccess   (mm_interconnect_0_pb_rxm_2_msi_s0_debugaccess),   //      .debugaccess
		.m0_waitrequest   (pb_rxm_2_msi_m0_waitrequest),                     //    m0.waitrequest
		.m0_readdata      (pb_rxm_2_msi_m0_readdata),                        //      .readdata
		.m0_readdatavalid (pb_rxm_2_msi_m0_readdatavalid),                   //      .readdatavalid
		.m0_burstcount    (pb_rxm_2_msi_m0_burstcount),                      //      .burstcount
		.m0_writedata     (pb_rxm_2_msi_m0_writedata),                       //      .writedata
		.m0_address       (pb_rxm_2_msi_m0_address),                         //      .address
		.m0_write         (pb_rxm_2_msi_m0_write),                           //      .write
		.m0_read          (pb_rxm_2_msi_m0_read),                            //      .read
		.m0_byteenable    (pb_rxm_2_msi_m0_byteenable),                      //      .byteenable
		.m0_debugaccess   (pb_rxm_2_msi_m0_debugaccess),                     //      .debugaccess
		.s0_response      (),                                                // (terminated)
		.m0_response      (2'b00)                                            // (terminated)
	);

	altpcie_cv_hip_avmm_hwtcl #(
		.lane_mask_hwtcl                          ("x1"),
		.gen123_lane_rate_mode_hwtcl              ("Gen1 (2.5 Gbps)"),
		.port_type_hwtcl                          ("Root port"),
		.pcie_spec_version_hwtcl                  ("2.1"),
		.pll_refclk_freq_hwtcl                    ("100 MHz"),
		.set_pld_clk_x1_625MHz_hwtcl              (0),
		.in_cvp_mode_hwtcl                        (0),
		.bar0_size_mask_hwtcl                     (32),
		.bar0_io_space_hwtcl                      ("Disabled"),
		.bar0_64bit_mem_space_hwtcl               ("Disabled"),
		.bar0_prefetchable_hwtcl                  ("Disabled"),
		.bar1_size_mask_hwtcl                     (0),
		.bar1_io_space_hwtcl                      ("Disabled"),
		.bar1_prefetchable_hwtcl                  ("Disabled"),
		.bar2_size_mask_hwtcl                     (0),
		.bar2_io_space_hwtcl                      ("Disabled"),
		.bar2_64bit_mem_space_hwtcl               ("Disabled"),
		.bar2_prefetchable_hwtcl                  ("Disabled"),
		.bar3_size_mask_hwtcl                     (0),
		.bar3_io_space_hwtcl                      ("Disabled"),
		.bar3_prefetchable_hwtcl                  ("Disabled"),
		.bar4_size_mask_hwtcl                     (0),
		.bar4_io_space_hwtcl                      ("Disabled"),
		.bar4_64bit_mem_space_hwtcl               ("Disabled"),
		.bar4_prefetchable_hwtcl                  ("Disabled"),
		.bar5_size_mask_hwtcl                     (0),
		.bar5_io_space_hwtcl                      ("Disabled"),
		.bar5_prefetchable_hwtcl                  ("Disabled"),
		.CB_P2A_AVALON_ADDR_B0                    (0),
		.CB_P2A_AVALON_ADDR_B1                    (0),
		.CB_P2A_AVALON_ADDR_B2                    (0),
		.CB_P2A_AVALON_ADDR_B3                    (0),
		.CB_P2A_AVALON_ADDR_B4                    (0),
		.CB_P2A_AVALON_ADDR_B5                    (0),
		.vendor_id_hwtcl                          (4466),
		.device_id_hwtcl                          (57344),
		.revision_id_hwtcl                        (1),
		.class_code_hwtcl                         (394240),
		.subsystem_vendor_id_hwtcl                (4466),
		.subsystem_device_id_hwtcl                (57344),
		.max_payload_size_hwtcl                   (256),
		.extend_tag_field_hwtcl                   ("32"),
		.completion_timeout_hwtcl                 ("ABCD"),
		.enable_completion_timeout_disable_hwtcl  (1),
		.use_aer_hwtcl                            (0),
		.ecrc_check_capable_hwtcl                 (0),
		.ecrc_gen_capable_hwtcl                   (0),
		.use_crc_forwarding_hwtcl                 (0),
		.port_link_number_hwtcl                   (1),
		.dll_active_report_support_hwtcl          (0),
		.surprise_down_error_support_hwtcl        (0),
		.slotclkcfg_hwtcl                         (1),
		.msi_multi_message_capable_hwtcl          ("4"),
		.msi_64bit_addressing_capable_hwtcl       ("true"),
		.msi_masking_capable_hwtcl                ("false"),
		.msi_support_hwtcl                        ("true"),
		.enable_function_msix_support_hwtcl       (0),
		.msix_table_size_hwtcl                    (0),
		.msix_table_offset_hwtcl                  ("0"),
		.msix_table_bir_hwtcl                     (0),
		.msix_pba_offset_hwtcl                    ("0"),
		.msix_pba_bir_hwtcl                       (0),
		.enable_slot_register_hwtcl               (0),
		.slot_power_scale_hwtcl                   (0),
		.slot_power_limit_hwtcl                   (0),
		.slot_number_hwtcl                        (0),
		.rx_ei_l0s_hwtcl                          (0),
		.endpoint_l0_latency_hwtcl                (0),
		.endpoint_l1_latency_hwtcl                (0),
		.vsec_id_hwtcl                            (40960),
		.vsec_rev_hwtcl                           (0),
		.user_id_hwtcl                            (0),
		.avmm_width_hwtcl                         (64),
		.AVALON_ADDR_WIDTH                        (32),
		.avmm_burst_width_hwtcl                   (7),
		.CB_PCIE_MODE                             (0),
		.CB_PCIE_RX_LITE                          (0),
		.CB_RXM_DATA_WIDTH                        (64),
		.CG_AVALON_S_ADDR_WIDTH                   (28),
		.CG_IMPL_CRA_AV_SLAVE_PORT                (1),
		.CG_ENABLE_ADVANCED_INTERRUPT             (0),
		.CG_ENABLE_A2P_INTERRUPT                  (0),
		.CB_A2P_ADDR_MAP_IS_FIXED                 (0),
		.CB_A2P_ADDR_MAP_NUM_ENTRIES              (2),
		.BYPASSS_A2P_TRANSLATION                  (0),
		.a2p_pass_thru_bits                       (27),
		.ast_width_hwtcl                          ("Avalon-ST 64-bit"),
		.use_ast_parity                           (0),
		.reconfig_to_xcvr_width                   (140),
		.hip_hard_reset_hwtcl                     (1),
		.reconfig_from_xcvr_width                 (92),
		.bypass_cdc_hwtcl                         ("false"),
		.single_rx_detect_hwtcl                   (1),
		.wrong_device_id_hwtcl                    ("disable"),
		.data_pack_rx_hwtcl                       ("disable"),
		.ltssm_1ms_timeout_hwtcl                  ("disable"),
		.ltssm_freqlocked_check_hwtcl             ("disable"),
		.deskew_comma_hwtcl                       ("skp_eieos_deskw"),
		.maximum_current_hwtcl                    (0),
		.disable_snoop_packet_hwtcl               ("false"),
		.enable_l0s_aspm_hwtcl                    ("true"),
		.extended_tag_reset_hwtcl                 ("false"),
		.interrupt_pin_hwtcl                      ("inta"),
		.bridge_port_vga_enable_hwtcl             ("false"),
		.bridge_port_ssid_support_hwtcl           ("false"),
		.ssvid_hwtcl                              (0),
		.ssid_hwtcl                               (0),
		.aspm_config_management_hwtcl             ("false"),
		.atomic_op_routing_hwtcl                  ("false"),
		.atomic_op_completer_32bit_hwtcl          ("false"),
		.atomic_op_completer_64bit_hwtcl          ("false"),
		.cas_completer_128bit_hwtcl               ("false"),
		.ltr_mechanism_hwtcl                      ("false"),
		.tph_completer_hwtcl                      ("false"),
		.extended_format_field_hwtcl              ("true"),
		.atomic_malformed_hwtcl                   ("true"),
		.flr_capability_hwtcl                     (0),
		.enable_adapter_half_rate_mode_hwtcl      ("false"),
		.skp_os_gen3_count_hwtcl                  (0),
		.millisecond_cycle_count_hwtcl            (124250),
		.credit_buffer_allocation_aux_hwtcl       ("absolute"),
		.vc0_rx_flow_ctrl_posted_header_hwtcl     (18),
		.vc0_rx_flow_ctrl_posted_data_hwtcl       (94),
		.vc0_rx_flow_ctrl_nonposted_header_hwtcl  (32),
		.vc0_rx_flow_ctrl_nonposted_data_hwtcl    (0),
		.vc0_rx_flow_ctrl_compl_header_hwtcl      (0),
		.vc0_rx_flow_ctrl_compl_data_hwtcl        (0),
		.cpl_spc_header_hwtcl                     (44),
		.cpl_spc_data_hwtcl                       (196),
		.coreclkout_hip_phaseshift_hwtcl          ("0 ps"),
		.pldclk_hip_phase_shift_hwtcl             ("0 ps"),
		.port_width_be_hwtcl                      (8),
		.port_width_data_hwtcl                    (64),
		.hip_reconfig_hwtcl                       (0),
		.gen3_rxfreqlock_counter_hwtcl            (0),
		.gen3_skip_ph2_ph3_hwtcl                  (0),
		.g3_bypass_equlz_hwtcl                    (0),
		.expansion_base_address_register_hwtcl    (0),
		.prefetchable_mem_window_addr_width_hwtcl (0),
		.bypass_clk_switch_hwtcl                  ("disable"),
		.cvp_rate_sel_hwtcl                       ("full_rate"),
		.cvp_data_compressed_hwtcl                ("false"),
		.cvp_data_encrypted_hwtcl                 ("false"),
		.cvp_mode_reset_hwtcl                     ("false"),
		.cvp_clk_reset_hwtcl                      ("false"),
		.core_clk_sel_hwtcl                       ("pld_clk"),
		.enable_rx_buffer_checking_hwtcl          ("false"),
		.disable_link_x2_support_hwtcl            ("false"),
		.device_number_hwtcl                      (0),
		.pipex1_debug_sel_hwtcl                   ("disable"),
		.pclk_out_sel_hwtcl                       ("pclk"),
		.no_soft_reset_hwtcl                      ("false"),
		.d1_support_hwtcl                         ("false"),
		.d2_support_hwtcl                         ("false"),
		.d0_pme_hwtcl                             ("false"),
		.d1_pme_hwtcl                             ("false"),
		.d2_pme_hwtcl                             ("false"),
		.d3_hot_pme_hwtcl                         ("false"),
		.d3_cold_pme_hwtcl                        ("false"),
		.low_priority_vc_hwtcl                    ("single_vc"),
		.enable_l1_aspm_hwtcl                     ("false"),
		.l1_exit_latency_sameclock_hwtcl          (0),
		.l1_exit_latency_diffclock_hwtcl          (0),
		.hot_plug_support_hwtcl                   (0),
		.no_command_completed_hwtcl               ("false"),
		.eie_before_nfts_count_hwtcl              (4),
		.gen2_diffclock_nfts_count_hwtcl          (255),
		.gen2_sameclock_nfts_count_hwtcl          (255),
		.deemphasis_enable_hwtcl                  ("false"),
		.l0_exit_latency_sameclock_hwtcl          (6),
		.l0_exit_latency_diffclock_hwtcl          (6),
		.vc0_clk_enable_hwtcl                     ("true"),
		.register_pipe_signals_hwtcl              ("true"),
		.tx_cdc_almost_empty_hwtcl                (5),
		.rx_l0s_count_idl_hwtcl                   (0),
		.cdc_dummy_insert_limit_hwtcl             (11),
		.ei_delay_powerdown_count_hwtcl           (10),
		.skp_os_schedule_count_hwtcl              (0),
		.fc_init_timer_hwtcl                      (1024),
		.l01_entry_latency_hwtcl                  (31),
		.flow_control_update_count_hwtcl          (30),
		.flow_control_timeout_count_hwtcl         (200),
		.retry_buffer_last_active_address_hwtcl   (255),
		.reserved_debug_hwtcl                     (0),
		.use_tl_cfg_sync_hwtcl                    (1),
		.diffclock_nfts_count_hwtcl               (255),
		.sameclock_nfts_count_hwtcl               (255),
		.l2_async_logic_hwtcl                     ("disable"),
		.rx_cdc_almost_full_hwtcl                 (12),
		.tx_cdc_almost_full_hwtcl                 (11),
		.indicator_hwtcl                          (0),
		.rpre_emph_a_val_hwtcl                    (11),
		.rpre_emph_b_val_hwtcl                    (0),
		.rpre_emph_c_val_hwtcl                    (22),
		.rpre_emph_d_val_hwtcl                    (12),
		.rpre_emph_e_val_hwtcl                    (21),
		.rvod_sel_a_val_hwtcl                     (50),
		.rvod_sel_b_val_hwtcl                     (34),
		.rvod_sel_c_val_hwtcl                     (50),
		.rvod_sel_d_val_hwtcl                     (50),
		.rvod_sel_e_val_hwtcl                     (9)
	) pcie_hip_avmm (
		.coreclkout           (pcie_hip_avmm_coreclkout_clk),                          //          coreclkout.clk
		.refclk               (pcie_hip_avmm_refclk_clk),                              //              refclk.clk
		.npor                 (pcie_hip_avmm_npor_npor),                               //                npor.npor
		.pin_perst            (pcie_hip_avmm_npor_pin_perst),                          //                    .pin_perst
		.reset_status         (pcie_hip_avmm_nreset_status_reset),                     //       nreset_status.reset_n
		.test_in              (pcie_hip_avmm_hip_ctrl_test_in),                        //            hip_ctrl.test_in
		.simu_mode_pipe       (pcie_hip_avmm_hip_ctrl_simu_mode_pipe),                 //                    .simu_mode_pipe
		.RxmAddress_0_o       (pcie_hip_avmm_rp_master_address),                       //           RP_Master.address
		.RxmRead_0_o          (pcie_hip_avmm_rp_master_read),                          //                    .read
		.RxmWaitRequest_0_i   (pcie_hip_avmm_rp_master_waitrequest),                   //                    .waitrequest
		.RxmWrite_0_o         (pcie_hip_avmm_rp_master_write),                         //                    .write
		.RxmReadDataValid_0_i (pcie_hip_avmm_rp_master_readdatavalid),                 //                    .readdatavalid
		.RxmReadData_0_i      (pcie_hip_avmm_rp_master_readdata),                      //                    .readdata
		.RxmWriteData_0_o     (pcie_hip_avmm_rp_master_writedata),                     //                    .writedata
		.RxmBurstCount_0_o    (pcie_hip_avmm_rp_master_burstcount),                    //                    .burstcount
		.RxmByteEnable_0_o    (pcie_hip_avmm_rp_master_byteenable),                    //                    .byteenable
		.RxmIrq_i             (pcie_hip_avmm_rxmirq_irq),                              //              RxmIrq.irq
		.reconfig_to_xcvr     (alt_xcvr_reconfig_0_reconfig_to_xcvr_reconfig_to_xcvr), //    reconfig_to_xcvr.reconfig_to_xcvr
		.busy_xcvr_reconfig   (alt_xcvr_reconfig_0_reconfig_busy_reconfig_busy),       //       reconfig_busy.reconfig_busy
		.reconfig_from_xcvr   (pcie_hip_avmm_reconfig_from_xcvr_reconfig_from_xcvr),   //  reconfig_from_xcvr.reconfig_from_xcvr
		.fixedclk_locked      (pcie_hip_avmm_reconfig_clk_locked_fixedclk_locked),     // reconfig_clk_locked.fixedclk_locked
		.rx_in0               (pcie_hip_avmm_hip_serial_rx_in0),                       //          hip_serial.rx_in0
		.tx_out0              (pcie_hip_avmm_hip_serial_tx_out0),                      //                    .tx_out0
		.sim_pipe_pclk_in     (pcie_hip_avmm_hip_pipe_sim_pipe_pclk_in),               //            hip_pipe.sim_pipe_pclk_in
		.sim_pipe_rate        (pcie_hip_avmm_hip_pipe_sim_pipe_rate),                  //                    .sim_pipe_rate
		.sim_ltssmstate       (pcie_hip_avmm_hip_pipe_sim_ltssmstate),                 //                    .sim_ltssmstate
		.eidleinfersel0       (pcie_hip_avmm_hip_pipe_eidleinfersel0),                 //                    .eidleinfersel0
		.powerdown0           (pcie_hip_avmm_hip_pipe_powerdown0),                     //                    .powerdown0
		.rxpolarity0          (pcie_hip_avmm_hip_pipe_rxpolarity0),                    //                    .rxpolarity0
		.txcompl0             (pcie_hip_avmm_hip_pipe_txcompl0),                       //                    .txcompl0
		.txdata0              (pcie_hip_avmm_hip_pipe_txdata0),                        //                    .txdata0
		.txdatak0             (pcie_hip_avmm_hip_pipe_txdatak0),                       //                    .txdatak0
		.txdetectrx0          (pcie_hip_avmm_hip_pipe_txdetectrx0),                    //                    .txdetectrx0
		.txelecidle0          (pcie_hip_avmm_hip_pipe_txelecidle0),                    //                    .txelecidle0
		.txswing0             (pcie_hip_avmm_hip_pipe_txswing0),                       //                    .txswing0
		.txmargin0            (pcie_hip_avmm_hip_pipe_txmargin0),                      //                    .txmargin0
		.txdeemph0            (pcie_hip_avmm_hip_pipe_txdeemph0),                      //                    .txdeemph0
		.phystatus0           (pcie_hip_avmm_hip_pipe_phystatus0),                     //                    .phystatus0
		.rxdata0              (pcie_hip_avmm_hip_pipe_rxdata0),                        //                    .rxdata0
		.rxdatak0             (pcie_hip_avmm_hip_pipe_rxdatak0),                       //                    .rxdatak0
		.rxelecidle0          (pcie_hip_avmm_hip_pipe_rxelecidle0),                    //                    .rxelecidle0
		.rxstatus0            (pcie_hip_avmm_hip_pipe_rxstatus0),                      //                    .rxstatus0
		.rxvalid0             (pcie_hip_avmm_hip_pipe_rxvalid0),                       //                    .rxvalid0
		.TxsChipSelect_i      (mm_interconnect_2_pcie_hip_avmm_txs_chipselect),        //                 Txs.chipselect
		.TxsByteEnable_i      (mm_interconnect_2_pcie_hip_avmm_txs_byteenable),        //                    .byteenable
		.TxsReadData_o        (mm_interconnect_2_pcie_hip_avmm_txs_readdata),          //                    .readdata
		.TxsWriteData_i       (mm_interconnect_2_pcie_hip_avmm_txs_writedata),         //                    .writedata
		.TxsRead_i            (mm_interconnect_2_pcie_hip_avmm_txs_read),              //                    .read
		.TxsWrite_i           (mm_interconnect_2_pcie_hip_avmm_txs_write),             //                    .write
		.TxsBurstCount_i      (mm_interconnect_2_pcie_hip_avmm_txs_burstcount),        //                    .burstcount
		.TxsReadDataValid_o   (mm_interconnect_2_pcie_hip_avmm_txs_readdatavalid),     //                    .readdatavalid
		.TxsWaitRequest_o     (mm_interconnect_2_pcie_hip_avmm_txs_waitrequest),       //                    .waitrequest
		.TxsAddress_i         (mm_interconnect_2_pcie_hip_avmm_txs_address),           //                    .address
		.CraChipSelect_i      (mm_interconnect_1_pcie_hip_avmm_cra_chipselect),        //                 Cra.chipselect
		.CraAddress_i         (mm_interconnect_1_pcie_hip_avmm_cra_address),           //                    .address
		.CraByteEnable_i      (mm_interconnect_1_pcie_hip_avmm_cra_byteenable),        //                    .byteenable
		.CraRead              (mm_interconnect_1_pcie_hip_avmm_cra_read),              //                    .read
		.CraReadData_o        (mm_interconnect_1_pcie_hip_avmm_cra_readdata),          //                    .readdata
		.CraWrite             (mm_interconnect_1_pcie_hip_avmm_cra_write),             //                    .write
		.CraWriteData_i       (mm_interconnect_1_pcie_hip_avmm_cra_writedata),         //                    .writedata
		.CraWaitRequest_o     (mm_interconnect_1_pcie_hip_avmm_cra_waitrequest),       //                    .waitrequest
		.CraIrq_o             (pcie_hip_avmm_cra_irq_irq),                             //              CraIrq.irq
		.rx_in1               (1'b0),                                                  //         (terminated)
		.rx_in2               (1'b0),                                                  //         (terminated)
		.rx_in3               (1'b0),                                                  //         (terminated)
		.rx_in4               (1'b0),                                                  //         (terminated)
		.rx_in5               (1'b0),                                                  //         (terminated)
		.rx_in6               (1'b0),                                                  //         (terminated)
		.rx_in7               (1'b0),                                                  //         (terminated)
		.tx_out1              (),                                                      //         (terminated)
		.tx_out2              (),                                                      //         (terminated)
		.tx_out3              (),                                                      //         (terminated)
		.tx_out4              (),                                                      //         (terminated)
		.tx_out5              (),                                                      //         (terminated)
		.tx_out6              (),                                                      //         (terminated)
		.tx_out7              (),                                                      //         (terminated)
		.eidleinfersel1       (),                                                      //         (terminated)
		.eidleinfersel2       (),                                                      //         (terminated)
		.eidleinfersel3       (),                                                      //         (terminated)
		.eidleinfersel4       (),                                                      //         (terminated)
		.eidleinfersel5       (),                                                      //         (terminated)
		.eidleinfersel6       (),                                                      //         (terminated)
		.eidleinfersel7       (),                                                      //         (terminated)
		.powerdown1           (),                                                      //         (terminated)
		.powerdown2           (),                                                      //         (terminated)
		.powerdown3           (),                                                      //         (terminated)
		.powerdown4           (),                                                      //         (terminated)
		.powerdown5           (),                                                      //         (terminated)
		.powerdown6           (),                                                      //         (terminated)
		.powerdown7           (),                                                      //         (terminated)
		.rxpolarity1          (),                                                      //         (terminated)
		.rxpolarity2          (),                                                      //         (terminated)
		.rxpolarity3          (),                                                      //         (terminated)
		.rxpolarity4          (),                                                      //         (terminated)
		.rxpolarity5          (),                                                      //         (terminated)
		.rxpolarity6          (),                                                      //         (terminated)
		.rxpolarity7          (),                                                      //         (terminated)
		.txcompl1             (),                                                      //         (terminated)
		.txcompl2             (),                                                      //         (terminated)
		.txcompl3             (),                                                      //         (terminated)
		.txcompl4             (),                                                      //         (terminated)
		.txcompl5             (),                                                      //         (terminated)
		.txcompl6             (),                                                      //         (terminated)
		.txcompl7             (),                                                      //         (terminated)
		.txdata1              (),                                                      //         (terminated)
		.txdata2              (),                                                      //         (terminated)
		.txdata3              (),                                                      //         (terminated)
		.txdata4              (),                                                      //         (terminated)
		.txdata5              (),                                                      //         (terminated)
		.txdata6              (),                                                      //         (terminated)
		.txdata7              (),                                                      //         (terminated)
		.txdatak1             (),                                                      //         (terminated)
		.txdatak2             (),                                                      //         (terminated)
		.txdatak3             (),                                                      //         (terminated)
		.txdatak4             (),                                                      //         (terminated)
		.txdatak5             (),                                                      //         (terminated)
		.txdatak6             (),                                                      //         (terminated)
		.txdatak7             (),                                                      //         (terminated)
		.txdetectrx1          (),                                                      //         (terminated)
		.txdetectrx2          (),                                                      //         (terminated)
		.txdetectrx3          (),                                                      //         (terminated)
		.txdetectrx4          (),                                                      //         (terminated)
		.txdetectrx5          (),                                                      //         (terminated)
		.txdetectrx6          (),                                                      //         (terminated)
		.txdetectrx7          (),                                                      //         (terminated)
		.txelecidle1          (),                                                      //         (terminated)
		.txelecidle2          (),                                                      //         (terminated)
		.txelecidle3          (),                                                      //         (terminated)
		.txelecidle4          (),                                                      //         (terminated)
		.txelecidle5          (),                                                      //         (terminated)
		.txelecidle6          (),                                                      //         (terminated)
		.txelecidle7          (),                                                      //         (terminated)
		.txswing1             (),                                                      //         (terminated)
		.txswing2             (),                                                      //         (terminated)
		.txswing3             (),                                                      //         (terminated)
		.txswing4             (),                                                      //         (terminated)
		.txswing5             (),                                                      //         (terminated)
		.txswing6             (),                                                      //         (terminated)
		.txswing7             (),                                                      //         (terminated)
		.txmargin1            (),                                                      //         (terminated)
		.txmargin2            (),                                                      //         (terminated)
		.txmargin3            (),                                                      //         (terminated)
		.txmargin4            (),                                                      //         (terminated)
		.txmargin5            (),                                                      //         (terminated)
		.txmargin6            (),                                                      //         (terminated)
		.txmargin7            (),                                                      //         (terminated)
		.txdeemph1            (),                                                      //         (terminated)
		.txdeemph2            (),                                                      //         (terminated)
		.txdeemph3            (),                                                      //         (terminated)
		.txdeemph4            (),                                                      //         (terminated)
		.txdeemph5            (),                                                      //         (terminated)
		.txdeemph6            (),                                                      //         (terminated)
		.txdeemph7            (),                                                      //         (terminated)
		.phystatus1           (1'b0),                                                  //         (terminated)
		.phystatus2           (1'b0),                                                  //         (terminated)
		.phystatus3           (1'b0),                                                  //         (terminated)
		.phystatus4           (1'b0),                                                  //         (terminated)
		.phystatus5           (1'b0),                                                  //         (terminated)
		.phystatus6           (1'b0),                                                  //         (terminated)
		.phystatus7           (1'b0),                                                  //         (terminated)
		.rxdata1              (8'b00000000),                                           //         (terminated)
		.rxdata2              (8'b00000000),                                           //         (terminated)
		.rxdata3              (8'b00000000),                                           //         (terminated)
		.rxdata4              (8'b00000000),                                           //         (terminated)
		.rxdata5              (8'b00000000),                                           //         (terminated)
		.rxdata6              (8'b00000000),                                           //         (terminated)
		.rxdata7              (8'b00000000),                                           //         (terminated)
		.rxdatak1             (1'b0),                                                  //         (terminated)
		.rxdatak2             (1'b0),                                                  //         (terminated)
		.rxdatak3             (1'b0),                                                  //         (terminated)
		.rxdatak4             (1'b0),                                                  //         (terminated)
		.rxdatak5             (1'b0),                                                  //         (terminated)
		.rxdatak6             (1'b0),                                                  //         (terminated)
		.rxdatak7             (1'b0),                                                  //         (terminated)
		.rxelecidle1          (1'b0),                                                  //         (terminated)
		.rxelecidle2          (1'b0),                                                  //         (terminated)
		.rxelecidle3          (1'b0),                                                  //         (terminated)
		.rxelecidle4          (1'b0),                                                  //         (terminated)
		.rxelecidle5          (1'b0),                                                  //         (terminated)
		.rxelecidle6          (1'b0),                                                  //         (terminated)
		.rxelecidle7          (1'b0),                                                  //         (terminated)
		.rxstatus1            (3'b000),                                                //         (terminated)
		.rxstatus2            (3'b000),                                                //         (terminated)
		.rxstatus3            (3'b000),                                                //         (terminated)
		.rxstatus4            (3'b000),                                                //         (terminated)
		.rxstatus5            (3'b000),                                                //         (terminated)
		.rxstatus6            (3'b000),                                                //         (terminated)
		.rxstatus7            (3'b000),                                                //         (terminated)
		.rxvalid1             (1'b0),                                                  //         (terminated)
		.rxvalid2             (1'b0),                                                  //         (terminated)
		.rxvalid3             (1'b0),                                                  //         (terminated)
		.rxvalid4             (1'b0),                                                  //         (terminated)
		.rxvalid5             (1'b0),                                                  //         (terminated)
		.rxvalid6             (1'b0),                                                  //         (terminated)
		.rxvalid7             (1'b0),                                                  //         (terminated)
		.rxdataskip0          (1'b0),                                                  //         (terminated)
		.rxdataskip1          (1'b0),                                                  //         (terminated)
		.rxdataskip2          (1'b0),                                                  //         (terminated)
		.rxdataskip3          (1'b0),                                                  //         (terminated)
		.rxdataskip4          (1'b0),                                                  //         (terminated)
		.rxdataskip5          (1'b0),                                                  //         (terminated)
		.rxdataskip6          (1'b0),                                                  //         (terminated)
		.rxdataskip7          (1'b0),                                                  //         (terminated)
		.rxblkst0             (1'b0),                                                  //         (terminated)
		.rxblkst1             (1'b0),                                                  //         (terminated)
		.rxblkst2             (1'b0),                                                  //         (terminated)
		.rxblkst3             (1'b0),                                                  //         (terminated)
		.rxblkst4             (1'b0),                                                  //         (terminated)
		.rxblkst5             (1'b0),                                                  //         (terminated)
		.rxblkst6             (1'b0),                                                  //         (terminated)
		.rxblkst7             (1'b0),                                                  //         (terminated)
		.rxsynchd0            (2'b00),                                                 //         (terminated)
		.rxsynchd1            (2'b00),                                                 //         (terminated)
		.rxsynchd2            (2'b00),                                                 //         (terminated)
		.rxsynchd3            (2'b00),                                                 //         (terminated)
		.rxsynchd4            (2'b00),                                                 //         (terminated)
		.rxsynchd5            (2'b00),                                                 //         (terminated)
		.rxsynchd6            (2'b00),                                                 //         (terminated)
		.rxsynchd7            (2'b00),                                                 //         (terminated)
		.rxfreqlocked0        (1'b0),                                                  //         (terminated)
		.rxfreqlocked1        (1'b0),                                                  //         (terminated)
		.rxfreqlocked2        (1'b0),                                                  //         (terminated)
		.rxfreqlocked3        (1'b0),                                                  //         (terminated)
		.rxfreqlocked4        (1'b0),                                                  //         (terminated)
		.rxfreqlocked5        (1'b0),                                                  //         (terminated)
		.rxfreqlocked6        (1'b0),                                                  //         (terminated)
		.rxfreqlocked7        (1'b0),                                                  //         (terminated)
		.currentcoeff0        (),                                                      //         (terminated)
		.currentcoeff1        (),                                                      //         (terminated)
		.currentcoeff2        (),                                                      //         (terminated)
		.currentcoeff3        (),                                                      //         (terminated)
		.currentcoeff4        (),                                                      //         (terminated)
		.currentcoeff5        (),                                                      //         (terminated)
		.currentcoeff6        (),                                                      //         (terminated)
		.currentcoeff7        (),                                                      //         (terminated)
		.currentrxpreset0     (),                                                      //         (terminated)
		.currentrxpreset1     (),                                                      //         (terminated)
		.currentrxpreset2     (),                                                      //         (terminated)
		.currentrxpreset3     (),                                                      //         (terminated)
		.currentrxpreset4     (),                                                      //         (terminated)
		.currentrxpreset5     (),                                                      //         (terminated)
		.currentrxpreset6     (),                                                      //         (terminated)
		.currentrxpreset7     (),                                                      //         (terminated)
		.txsynchd0            (),                                                      //         (terminated)
		.txsynchd1            (),                                                      //         (terminated)
		.txsynchd2            (),                                                      //         (terminated)
		.txsynchd3            (),                                                      //         (terminated)
		.txsynchd4            (),                                                      //         (terminated)
		.txsynchd5            (),                                                      //         (terminated)
		.txsynchd6            (),                                                      //         (terminated)
		.txsynchd7            (),                                                      //         (terminated)
		.txblkst0             (),                                                      //         (terminated)
		.txblkst1             (),                                                      //         (terminated)
		.txblkst2             (),                                                      //         (terminated)
		.txblkst3             (),                                                      //         (terminated)
		.txblkst4             (),                                                      //         (terminated)
		.txblkst5             (),                                                      //         (terminated)
		.txblkst6             (),                                                      //         (terminated)
		.txblkst7             ()                                                       //         (terminated)
	);

	soc_system_pcie_0_performance_counter_0 performance_counter_0 (
		.clk           (clk_clk),                                                             //           clk.clk
		.reset_n       (~rst_controller_reset_out_reset),                                     //         reset.reset_n
		.address       (mm_interconnect_1_performance_counter_0_control_slave_address),       // control_slave.address
		.begintransfer (mm_interconnect_1_performance_counter_0_control_slave_begintransfer), //              .begintransfer
		.readdata      (mm_interconnect_1_performance_counter_0_control_slave_readdata),      //              .readdata
		.write         (mm_interconnect_1_performance_counter_0_control_slave_write),         //              .write
		.writedata     (mm_interconnect_1_performance_counter_0_control_slave_writedata)      //              .writedata
	);

	soc_system_pcie_0_mm_interconnect_0 mm_interconnect_0 (
		.custom_reset_synchronizer_0_clock_out_clk                            (coreclk_fanout_clk_clk),                             //                          custom_reset_synchronizer_0_clock_out.clk
		.pcie_hip_avmm_coreclkout_clk                                         (pcie_hip_avmm_coreclkout_clk),                       //                                       pcie_hip_avmm_coreclkout.clk
		.msgdma_0_reset_n_reset_bridge_in_reset_reset                         (custom_reset_synchronizer_0_reset_out_reset),        //                         msgdma_0_reset_n_reset_bridge_in_reset.reset
		.pcie_hip_avmm_RP_Master_translator_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset),                 // pcie_hip_avmm_RP_Master_translator_reset_reset_bridge_in_reset.reset
		.msgdma_0_mm_read_address                                             (msgdma_0_mm_read_address),                           //                                               msgdma_0_mm_read.address
		.msgdma_0_mm_read_waitrequest                                         (msgdma_0_mm_read_waitrequest),                       //                                                               .waitrequest
		.msgdma_0_mm_read_burstcount                                          (msgdma_0_mm_read_burstcount),                        //                                                               .burstcount
		.msgdma_0_mm_read_byteenable                                          (msgdma_0_mm_read_byteenable),                        //                                                               .byteenable
		.msgdma_0_mm_read_read                                                (msgdma_0_mm_read_read),                              //                                                               .read
		.msgdma_0_mm_read_readdata                                            (msgdma_0_mm_read_readdata),                          //                                                               .readdata
		.msgdma_0_mm_read_readdatavalid                                       (msgdma_0_mm_read_readdatavalid),                     //                                                               .readdatavalid
		.msgdma_0_mm_write_address                                            (msgdma_0_mm_write_address),                          //                                              msgdma_0_mm_write.address
		.msgdma_0_mm_write_waitrequest                                        (msgdma_0_mm_write_waitrequest),                      //                                                               .waitrequest
		.msgdma_0_mm_write_burstcount                                         (msgdma_0_mm_write_burstcount),                       //                                                               .burstcount
		.msgdma_0_mm_write_byteenable                                         (msgdma_0_mm_write_byteenable),                       //                                                               .byteenable
		.msgdma_0_mm_write_write                                              (msgdma_0_mm_write_write),                            //                                                               .write
		.msgdma_0_mm_write_writedata                                          (msgdma_0_mm_write_writedata),                        //                                                               .writedata
		.pcie_hip_avmm_RP_Master_address                                      (pcie_hip_avmm_rp_master_address),                    //                                        pcie_hip_avmm_RP_Master.address
		.pcie_hip_avmm_RP_Master_waitrequest                                  (pcie_hip_avmm_rp_master_waitrequest),                //                                                               .waitrequest
		.pcie_hip_avmm_RP_Master_burstcount                                   (pcie_hip_avmm_rp_master_burstcount),                 //                                                               .burstcount
		.pcie_hip_avmm_RP_Master_byteenable                                   (pcie_hip_avmm_rp_master_byteenable),                 //                                                               .byteenable
		.pcie_hip_avmm_RP_Master_read                                         (pcie_hip_avmm_rp_master_read),                       //                                                               .read
		.pcie_hip_avmm_RP_Master_readdata                                     (pcie_hip_avmm_rp_master_readdata),                   //                                                               .readdata
		.pcie_hip_avmm_RP_Master_readdatavalid                                (pcie_hip_avmm_rp_master_readdatavalid),              //                                                               .readdatavalid
		.pcie_hip_avmm_RP_Master_write                                        (pcie_hip_avmm_rp_master_write),                      //                                                               .write
		.pcie_hip_avmm_RP_Master_writedata                                    (pcie_hip_avmm_rp_master_writedata),                  //                                                               .writedata
		.pb_2_ocm_s0_address                                                  (mm_interconnect_0_pb_2_ocm_s0_address),              //                                                    pb_2_ocm_s0.address
		.pb_2_ocm_s0_write                                                    (mm_interconnect_0_pb_2_ocm_s0_write),                //                                                               .write
		.pb_2_ocm_s0_read                                                     (mm_interconnect_0_pb_2_ocm_s0_read),                 //                                                               .read
		.pb_2_ocm_s0_readdata                                                 (mm_interconnect_0_pb_2_ocm_s0_readdata),             //                                                               .readdata
		.pb_2_ocm_s0_writedata                                                (mm_interconnect_0_pb_2_ocm_s0_writedata),            //                                                               .writedata
		.pb_2_ocm_s0_burstcount                                               (mm_interconnect_0_pb_2_ocm_s0_burstcount),           //                                                               .burstcount
		.pb_2_ocm_s0_byteenable                                               (mm_interconnect_0_pb_2_ocm_s0_byteenable),           //                                                               .byteenable
		.pb_2_ocm_s0_readdatavalid                                            (mm_interconnect_0_pb_2_ocm_s0_readdatavalid),        //                                                               .readdatavalid
		.pb_2_ocm_s0_waitrequest                                              (mm_interconnect_0_pb_2_ocm_s0_waitrequest),          //                                                               .waitrequest
		.pb_2_ocm_s0_debugaccess                                              (mm_interconnect_0_pb_2_ocm_s0_debugaccess),          //                                                               .debugaccess
		.pb_f2sdram_s0_address                                                (mm_interconnect_0_pb_f2sdram_s0_address),            //                                                  pb_f2sdram_s0.address
		.pb_f2sdram_s0_write                                                  (mm_interconnect_0_pb_f2sdram_s0_write),              //                                                               .write
		.pb_f2sdram_s0_read                                                   (mm_interconnect_0_pb_f2sdram_s0_read),               //                                                               .read
		.pb_f2sdram_s0_readdata                                               (mm_interconnect_0_pb_f2sdram_s0_readdata),           //                                                               .readdata
		.pb_f2sdram_s0_writedata                                              (mm_interconnect_0_pb_f2sdram_s0_writedata),          //                                                               .writedata
		.pb_f2sdram_s0_burstcount                                             (mm_interconnect_0_pb_f2sdram_s0_burstcount),         //                                                               .burstcount
		.pb_f2sdram_s0_byteenable                                             (mm_interconnect_0_pb_f2sdram_s0_byteenable),         //                                                               .byteenable
		.pb_f2sdram_s0_readdatavalid                                          (mm_interconnect_0_pb_f2sdram_s0_readdatavalid),      //                                                               .readdatavalid
		.pb_f2sdram_s0_waitrequest                                            (mm_interconnect_0_pb_f2sdram_s0_waitrequest),        //                                                               .waitrequest
		.pb_f2sdram_s0_debugaccess                                            (mm_interconnect_0_pb_f2sdram_s0_debugaccess),        //                                                               .debugaccess
		.pb_msgdma_2_txs_s0_address                                           (mm_interconnect_0_pb_msgdma_2_txs_s0_address),       //                                             pb_msgdma_2_txs_s0.address
		.pb_msgdma_2_txs_s0_write                                             (mm_interconnect_0_pb_msgdma_2_txs_s0_write),         //                                                               .write
		.pb_msgdma_2_txs_s0_read                                              (mm_interconnect_0_pb_msgdma_2_txs_s0_read),          //                                                               .read
		.pb_msgdma_2_txs_s0_readdata                                          (mm_interconnect_0_pb_msgdma_2_txs_s0_readdata),      //                                                               .readdata
		.pb_msgdma_2_txs_s0_writedata                                         (mm_interconnect_0_pb_msgdma_2_txs_s0_writedata),     //                                                               .writedata
		.pb_msgdma_2_txs_s0_burstcount                                        (mm_interconnect_0_pb_msgdma_2_txs_s0_burstcount),    //                                                               .burstcount
		.pb_msgdma_2_txs_s0_byteenable                                        (mm_interconnect_0_pb_msgdma_2_txs_s0_byteenable),    //                                                               .byteenable
		.pb_msgdma_2_txs_s0_readdatavalid                                     (mm_interconnect_0_pb_msgdma_2_txs_s0_readdatavalid), //                                                               .readdatavalid
		.pb_msgdma_2_txs_s0_waitrequest                                       (mm_interconnect_0_pb_msgdma_2_txs_s0_waitrequest),   //                                                               .waitrequest
		.pb_msgdma_2_txs_s0_debugaccess                                       (mm_interconnect_0_pb_msgdma_2_txs_s0_debugaccess),   //                                                               .debugaccess
		.pb_rxm_2_msi_s0_address                                              (mm_interconnect_0_pb_rxm_2_msi_s0_address),          //                                                pb_rxm_2_msi_s0.address
		.pb_rxm_2_msi_s0_write                                                (mm_interconnect_0_pb_rxm_2_msi_s0_write),            //                                                               .write
		.pb_rxm_2_msi_s0_read                                                 (mm_interconnect_0_pb_rxm_2_msi_s0_read),             //                                                               .read
		.pb_rxm_2_msi_s0_readdata                                             (mm_interconnect_0_pb_rxm_2_msi_s0_readdata),         //                                                               .readdata
		.pb_rxm_2_msi_s0_writedata                                            (mm_interconnect_0_pb_rxm_2_msi_s0_writedata),        //                                                               .writedata
		.pb_rxm_2_msi_s0_burstcount                                           (mm_interconnect_0_pb_rxm_2_msi_s0_burstcount),       //                                                               .burstcount
		.pb_rxm_2_msi_s0_byteenable                                           (mm_interconnect_0_pb_rxm_2_msi_s0_byteenable),       //                                                               .byteenable
		.pb_rxm_2_msi_s0_readdatavalid                                        (mm_interconnect_0_pb_rxm_2_msi_s0_readdatavalid),    //                                                               .readdatavalid
		.pb_rxm_2_msi_s0_waitrequest                                          (mm_interconnect_0_pb_rxm_2_msi_s0_waitrequest),      //                                                               .waitrequest
		.pb_rxm_2_msi_s0_debugaccess                                          (mm_interconnect_0_pb_rxm_2_msi_s0_debugaccess)       //                                                               .debugaccess
	);

	soc_system_pcie_0_mm_interconnect_1 mm_interconnect_1 (
		.clk_clk_clk                                                    (clk_clk),                                                             //                                                  clk_clk.clk
		.custom_reset_synchronizer_0_clock_out_clk                      (coreclk_fanout_clk_clk),                                              //                    custom_reset_synchronizer_0_clock_out.clk
		.pcie_hip_avmm_coreclkout_clk                                   (pcie_hip_avmm_coreclkout_clk),                                        //                                 pcie_hip_avmm_coreclkout.clk
		.pb_lwh2f_pcie_reset_reset_bridge_in_reset_reset                (custom_reset_synchronizer_0_reset_out_reset),                         //                pb_lwh2f_pcie_reset_reset_bridge_in_reset.reset
		.pcie_hip_avmm_Cra_translator_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset),                                  // pcie_hip_avmm_Cra_translator_reset_reset_bridge_in_reset.reset
		.performance_counter_0_reset_reset_bridge_in_reset_reset        (rst_controller_reset_out_reset),                                      //        performance_counter_0_reset_reset_bridge_in_reset.reset
		.pb_lwh2f_pcie_m0_address                                       (pb_lwh2f_pcie_m0_address),                                            //                                         pb_lwh2f_pcie_m0.address
		.pb_lwh2f_pcie_m0_waitrequest                                   (pb_lwh2f_pcie_m0_waitrequest),                                        //                                                         .waitrequest
		.pb_lwh2f_pcie_m0_burstcount                                    (pb_lwh2f_pcie_m0_burstcount),                                         //                                                         .burstcount
		.pb_lwh2f_pcie_m0_byteenable                                    (pb_lwh2f_pcie_m0_byteenable),                                         //                                                         .byteenable
		.pb_lwh2f_pcie_m0_read                                          (pb_lwh2f_pcie_m0_read),                                               //                                                         .read
		.pb_lwh2f_pcie_m0_readdata                                      (pb_lwh2f_pcie_m0_readdata),                                           //                                                         .readdata
		.pb_lwh2f_pcie_m0_readdatavalid                                 (pb_lwh2f_pcie_m0_readdatavalid),                                      //                                                         .readdatavalid
		.pb_lwh2f_pcie_m0_write                                         (pb_lwh2f_pcie_m0_write),                                              //                                                         .write
		.pb_lwh2f_pcie_m0_writedata                                     (pb_lwh2f_pcie_m0_writedata),                                          //                                                         .writedata
		.pb_lwh2f_pcie_m0_debugaccess                                   (pb_lwh2f_pcie_m0_debugaccess),                                        //                                                         .debugaccess
		.pb_rxm_2_msi_m0_address                                        (pb_rxm_2_msi_m0_address),                                             //                                          pb_rxm_2_msi_m0.address
		.pb_rxm_2_msi_m0_waitrequest                                    (pb_rxm_2_msi_m0_waitrequest),                                         //                                                         .waitrequest
		.pb_rxm_2_msi_m0_burstcount                                     (pb_rxm_2_msi_m0_burstcount),                                          //                                                         .burstcount
		.pb_rxm_2_msi_m0_byteenable                                     (pb_rxm_2_msi_m0_byteenable),                                          //                                                         .byteenable
		.pb_rxm_2_msi_m0_read                                           (pb_rxm_2_msi_m0_read),                                                //                                                         .read
		.pb_rxm_2_msi_m0_readdata                                       (pb_rxm_2_msi_m0_readdata),                                            //                                                         .readdata
		.pb_rxm_2_msi_m0_readdatavalid                                  (pb_rxm_2_msi_m0_readdatavalid),                                       //                                                         .readdatavalid
		.pb_rxm_2_msi_m0_write                                          (pb_rxm_2_msi_m0_write),                                               //                                                         .write
		.pb_rxm_2_msi_m0_writedata                                      (pb_rxm_2_msi_m0_writedata),                                           //                                                         .writedata
		.pb_rxm_2_msi_m0_debugaccess                                    (pb_rxm_2_msi_m0_debugaccess),                                         //                                                         .debugaccess
		.msgdma_0_csr_address                                           (mm_interconnect_1_msgdma_0_csr_address),                              //                                             msgdma_0_csr.address
		.msgdma_0_csr_write                                             (mm_interconnect_1_msgdma_0_csr_write),                                //                                                         .write
		.msgdma_0_csr_read                                              (mm_interconnect_1_msgdma_0_csr_read),                                 //                                                         .read
		.msgdma_0_csr_readdata                                          (mm_interconnect_1_msgdma_0_csr_readdata),                             //                                                         .readdata
		.msgdma_0_csr_writedata                                         (mm_interconnect_1_msgdma_0_csr_writedata),                            //                                                         .writedata
		.msgdma_0_csr_byteenable                                        (mm_interconnect_1_msgdma_0_csr_byteenable),                           //                                                         .byteenable
		.msgdma_0_descriptor_slave_write                                (mm_interconnect_1_msgdma_0_descriptor_slave_write),                   //                                msgdma_0_descriptor_slave.write
		.msgdma_0_descriptor_slave_writedata                            (mm_interconnect_1_msgdma_0_descriptor_slave_writedata),               //                                                         .writedata
		.msgdma_0_descriptor_slave_byteenable                           (mm_interconnect_1_msgdma_0_descriptor_slave_byteenable),              //                                                         .byteenable
		.msgdma_0_descriptor_slave_waitrequest                          (mm_interconnect_1_msgdma_0_descriptor_slave_waitrequest),             //                                                         .waitrequest
		.msi_to_gic_gen_0_csr_address                                   (mm_interconnect_1_msi_to_gic_gen_0_csr_address),                      //                                     msi_to_gic_gen_0_csr.address
		.msi_to_gic_gen_0_csr_write                                     (mm_interconnect_1_msi_to_gic_gen_0_csr_write),                        //                                                         .write
		.msi_to_gic_gen_0_csr_read                                      (mm_interconnect_1_msi_to_gic_gen_0_csr_read),                         //                                                         .read
		.msi_to_gic_gen_0_csr_readdata                                  (mm_interconnect_1_msi_to_gic_gen_0_csr_readdata),                     //                                                         .readdata
		.msi_to_gic_gen_0_csr_writedata                                 (mm_interconnect_1_msi_to_gic_gen_0_csr_writedata),                    //                                                         .writedata
		.msi_to_gic_gen_0_vector_slave_address                          (mm_interconnect_1_msi_to_gic_gen_0_vector_slave_address),             //                            msi_to_gic_gen_0_vector_slave.address
		.msi_to_gic_gen_0_vector_slave_write                            (mm_interconnect_1_msi_to_gic_gen_0_vector_slave_write),               //                                                         .write
		.msi_to_gic_gen_0_vector_slave_read                             (mm_interconnect_1_msi_to_gic_gen_0_vector_slave_read),                //                                                         .read
		.msi_to_gic_gen_0_vector_slave_readdata                         (mm_interconnect_1_msi_to_gic_gen_0_vector_slave_readdata),            //                                                         .readdata
		.msi_to_gic_gen_0_vector_slave_writedata                        (mm_interconnect_1_msi_to_gic_gen_0_vector_slave_writedata),           //                                                         .writedata
		.pcie_hip_avmm_Cra_address                                      (mm_interconnect_1_pcie_hip_avmm_cra_address),                         //                                        pcie_hip_avmm_Cra.address
		.pcie_hip_avmm_Cra_write                                        (mm_interconnect_1_pcie_hip_avmm_cra_write),                           //                                                         .write
		.pcie_hip_avmm_Cra_read                                         (mm_interconnect_1_pcie_hip_avmm_cra_read),                            //                                                         .read
		.pcie_hip_avmm_Cra_readdata                                     (mm_interconnect_1_pcie_hip_avmm_cra_readdata),                        //                                                         .readdata
		.pcie_hip_avmm_Cra_writedata                                    (mm_interconnect_1_pcie_hip_avmm_cra_writedata),                       //                                                         .writedata
		.pcie_hip_avmm_Cra_byteenable                                   (mm_interconnect_1_pcie_hip_avmm_cra_byteenable),                      //                                                         .byteenable
		.pcie_hip_avmm_Cra_waitrequest                                  (mm_interconnect_1_pcie_hip_avmm_cra_waitrequest),                     //                                                         .waitrequest
		.pcie_hip_avmm_Cra_chipselect                                   (mm_interconnect_1_pcie_hip_avmm_cra_chipselect),                      //                                                         .chipselect
		.performance_counter_0_control_slave_address                    (mm_interconnect_1_performance_counter_0_control_slave_address),       //                      performance_counter_0_control_slave.address
		.performance_counter_0_control_slave_write                      (mm_interconnect_1_performance_counter_0_control_slave_write),         //                                                         .write
		.performance_counter_0_control_slave_readdata                   (mm_interconnect_1_performance_counter_0_control_slave_readdata),      //                                                         .readdata
		.performance_counter_0_control_slave_writedata                  (mm_interconnect_1_performance_counter_0_control_slave_writedata),     //                                                         .writedata
		.performance_counter_0_control_slave_begintransfer              (mm_interconnect_1_performance_counter_0_control_slave_begintransfer)  //                                                         .begintransfer
	);

	soc_system_pcie_0_mm_interconnect_2 mm_interconnect_2 (
		.custom_reset_synchronizer_0_clock_out_clk                      (coreclk_fanout_clk_clk),                            //                    custom_reset_synchronizer_0_clock_out.clk
		.pcie_hip_avmm_coreclkout_clk                                   (pcie_hip_avmm_coreclkout_clk),                      //                                 pcie_hip_avmm_coreclkout.clk
		.ccb_h2f_m0_reset_reset_bridge_in_reset_reset                   (custom_reset_synchronizer_0_reset_out_reset),       //                   ccb_h2f_m0_reset_reset_bridge_in_reset.reset
		.pcie_hip_avmm_Txs_translator_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset),                // pcie_hip_avmm_Txs_translator_reset_reset_bridge_in_reset.reset
		.ccb_h2f_m0_address                                             (ccb_h2f_m0_address),                                //                                               ccb_h2f_m0.address
		.ccb_h2f_m0_waitrequest                                         (ccb_h2f_m0_waitrequest),                            //                                                         .waitrequest
		.ccb_h2f_m0_burstcount                                          (ccb_h2f_m0_burstcount),                             //                                                         .burstcount
		.ccb_h2f_m0_byteenable                                          (ccb_h2f_m0_byteenable),                             //                                                         .byteenable
		.ccb_h2f_m0_read                                                (ccb_h2f_m0_read),                                   //                                                         .read
		.ccb_h2f_m0_readdata                                            (ccb_h2f_m0_readdata),                               //                                                         .readdata
		.ccb_h2f_m0_readdatavalid                                       (ccb_h2f_m0_readdatavalid),                          //                                                         .readdatavalid
		.ccb_h2f_m0_write                                               (ccb_h2f_m0_write),                                  //                                                         .write
		.ccb_h2f_m0_writedata                                           (ccb_h2f_m0_writedata),                              //                                                         .writedata
		.ccb_h2f_m0_debugaccess                                         (ccb_h2f_m0_debugaccess),                            //                                                         .debugaccess
		.pb_msgdma_2_txs_m0_address                                     (pb_msgdma_2_txs_m0_address),                        //                                       pb_msgdma_2_txs_m0.address
		.pb_msgdma_2_txs_m0_waitrequest                                 (pb_msgdma_2_txs_m0_waitrequest),                    //                                                         .waitrequest
		.pb_msgdma_2_txs_m0_burstcount                                  (pb_msgdma_2_txs_m0_burstcount),                     //                                                         .burstcount
		.pb_msgdma_2_txs_m0_byteenable                                  (pb_msgdma_2_txs_m0_byteenable),                     //                                                         .byteenable
		.pb_msgdma_2_txs_m0_read                                        (pb_msgdma_2_txs_m0_read),                           //                                                         .read
		.pb_msgdma_2_txs_m0_readdata                                    (pb_msgdma_2_txs_m0_readdata),                       //                                                         .readdata
		.pb_msgdma_2_txs_m0_readdatavalid                               (pb_msgdma_2_txs_m0_readdatavalid),                  //                                                         .readdatavalid
		.pb_msgdma_2_txs_m0_write                                       (pb_msgdma_2_txs_m0_write),                          //                                                         .write
		.pb_msgdma_2_txs_m0_writedata                                   (pb_msgdma_2_txs_m0_writedata),                      //                                                         .writedata
		.pb_msgdma_2_txs_m0_debugaccess                                 (pb_msgdma_2_txs_m0_debugaccess),                    //                                                         .debugaccess
		.pcie_hip_avmm_Txs_address                                      (mm_interconnect_2_pcie_hip_avmm_txs_address),       //                                        pcie_hip_avmm_Txs.address
		.pcie_hip_avmm_Txs_write                                        (mm_interconnect_2_pcie_hip_avmm_txs_write),         //                                                         .write
		.pcie_hip_avmm_Txs_read                                         (mm_interconnect_2_pcie_hip_avmm_txs_read),          //                                                         .read
		.pcie_hip_avmm_Txs_readdata                                     (mm_interconnect_2_pcie_hip_avmm_txs_readdata),      //                                                         .readdata
		.pcie_hip_avmm_Txs_writedata                                    (mm_interconnect_2_pcie_hip_avmm_txs_writedata),     //                                                         .writedata
		.pcie_hip_avmm_Txs_burstcount                                   (mm_interconnect_2_pcie_hip_avmm_txs_burstcount),    //                                                         .burstcount
		.pcie_hip_avmm_Txs_byteenable                                   (mm_interconnect_2_pcie_hip_avmm_txs_byteenable),    //                                                         .byteenable
		.pcie_hip_avmm_Txs_readdatavalid                                (mm_interconnect_2_pcie_hip_avmm_txs_readdatavalid), //                                                         .readdatavalid
		.pcie_hip_avmm_Txs_waitrequest                                  (mm_interconnect_2_pcie_hip_avmm_txs_waitrequest),   //                                                         .waitrequest
		.pcie_hip_avmm_Txs_chipselect                                   (mm_interconnect_2_pcie_hip_avmm_txs_chipselect)     //                                                         .chipselect
	);

	soc_system_pcie_0_mm_interconnect_3 mm_interconnect_3 (
		.custom_reset_synchronizer_0_clock_out_clk    (coreclk_fanout_clk_clk),                                       //  custom_reset_synchronizer_0_clock_out.clk
		.pb_f2sdram_reset_reset_bridge_in_reset_reset (custom_reset_synchronizer_0_reset_out_reset),                  // pb_f2sdram_reset_reset_bridge_in_reset.reset
		.pb_f2sdram_m0_address                        (pb_f2sdram_m0_address),                                        //                          pb_f2sdram_m0.address
		.pb_f2sdram_m0_waitrequest                    (pb_f2sdram_m0_waitrequest),                                    //                                       .waitrequest
		.pb_f2sdram_m0_burstcount                     (pb_f2sdram_m0_burstcount),                                     //                                       .burstcount
		.pb_f2sdram_m0_byteenable                     (pb_f2sdram_m0_byteenable),                                     //                                       .byteenable
		.pb_f2sdram_m0_read                           (pb_f2sdram_m0_read),                                           //                                       .read
		.pb_f2sdram_m0_readdata                       (pb_f2sdram_m0_readdata),                                       //                                       .readdata
		.pb_f2sdram_m0_readdatavalid                  (pb_f2sdram_m0_readdatavalid),                                  //                                       .readdatavalid
		.pb_f2sdram_m0_write                          (pb_f2sdram_m0_write),                                          //                                       .write
		.pb_f2sdram_m0_writedata                      (pb_f2sdram_m0_writedata),                                      //                                       .writedata
		.pb_f2sdram_m0_debugaccess                    (pb_f2sdram_m0_debugaccess),                                    //                                       .debugaccess
		.add_x_f2sdram_windowed_slave_address         (mm_interconnect_3_add_x_f2sdram_windowed_slave_address),       //           add_x_f2sdram_windowed_slave.address
		.add_x_f2sdram_windowed_slave_write           (mm_interconnect_3_add_x_f2sdram_windowed_slave_write),         //                                       .write
		.add_x_f2sdram_windowed_slave_read            (mm_interconnect_3_add_x_f2sdram_windowed_slave_read),          //                                       .read
		.add_x_f2sdram_windowed_slave_readdata        (mm_interconnect_3_add_x_f2sdram_windowed_slave_readdata),      //                                       .readdata
		.add_x_f2sdram_windowed_slave_writedata       (mm_interconnect_3_add_x_f2sdram_windowed_slave_writedata),     //                                       .writedata
		.add_x_f2sdram_windowed_slave_burstcount      (mm_interconnect_3_add_x_f2sdram_windowed_slave_burstcount),    //                                       .burstcount
		.add_x_f2sdram_windowed_slave_byteenable      (mm_interconnect_3_add_x_f2sdram_windowed_slave_byteenable),    //                                       .byteenable
		.add_x_f2sdram_windowed_slave_readdatavalid   (mm_interconnect_3_add_x_f2sdram_windowed_slave_readdatavalid), //                                       .readdatavalid
		.add_x_f2sdram_windowed_slave_waitrequest     (mm_interconnect_3_add_x_f2sdram_windowed_slave_waitrequest)    //                                       .waitrequest
	);

	soc_system_pcie_0_irq_mapper irq_mapper (
		.clk        (pcie_hip_avmm_coreclkout_clk),       //       clk.clk
		.reset      (rst_controller_002_reset_out_reset), // clk_reset.reset
		.sender_irq (pcie_hip_avmm_rxmirq_irq)            //    sender.irq
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (custom_reset_synchronizer_0_reset_out_reset), // reset_in0.reset
		.clk            (clk_clk),                                     //       clk.clk
		.reset_out      (rst_controller_reset_out_reset),              // reset_out.reset
		.reset_req      (),                                            // (terminated)
		.reset_req_in0  (1'b0),                                        // (terminated)
		.reset_in1      (1'b0),                                        // (terminated)
		.reset_req_in1  (1'b0),                                        // (terminated)
		.reset_in2      (1'b0),                                        // (terminated)
		.reset_req_in2  (1'b0),                                        // (terminated)
		.reset_in3      (1'b0),                                        // (terminated)
		.reset_req_in3  (1'b0),                                        // (terminated)
		.reset_in4      (1'b0),                                        // (terminated)
		.reset_req_in4  (1'b0),                                        // (terminated)
		.reset_in5      (1'b0),                                        // (terminated)
		.reset_req_in5  (1'b0),                                        // (terminated)
		.reset_in6      (1'b0),                                        // (terminated)
		.reset_req_in6  (1'b0),                                        // (terminated)
		.reset_in7      (1'b0),                                        // (terminated)
		.reset_req_in7  (1'b0),                                        // (terminated)
		.reset_in8      (1'b0),                                        // (terminated)
		.reset_req_in8  (1'b0),                                        // (terminated)
		.reset_in9      (1'b0),                                        // (terminated)
		.reset_req_in9  (1'b0),                                        // (terminated)
		.reset_in10     (1'b0),                                        // (terminated)
		.reset_req_in10 (1'b0),                                        // (terminated)
		.reset_in11     (1'b0),                                        // (terminated)
		.reset_req_in11 (1'b0),                                        // (terminated)
		.reset_in12     (1'b0),                                        // (terminated)
		.reset_req_in12 (1'b0),                                        // (terminated)
		.reset_in13     (1'b0),                                        // (terminated)
		.reset_req_in13 (1'b0),                                        // (terminated)
		.reset_in14     (1'b0),                                        // (terminated)
		.reset_req_in14 (1'b0),                                        // (terminated)
		.reset_in15     (1'b0),                                        // (terminated)
		.reset_req_in15 (1'b0)                                         // (terminated)
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (2),
		.OUTPUT_RESET_SYNC_EDGES   ("none"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller_001 (
		.reset_in0      (~reset_reset_n),                     // reset_in0.reset
		.reset_in1      (~pcie_hip_avmm_nreset_status_reset), // reset_in1.reset
		.clk            (),                                   //       clk.clk
		.reset_out      (rst_controller_001_reset_out_reset), // reset_out.reset
		.reset_req      (),                                   // (terminated)
		.reset_req_in0  (1'b0),                               // (terminated)
		.reset_req_in1  (1'b0),                               // (terminated)
		.reset_in2      (1'b0),                               // (terminated)
		.reset_req_in2  (1'b0),                               // (terminated)
		.reset_in3      (1'b0),                               // (terminated)
		.reset_req_in3  (1'b0),                               // (terminated)
		.reset_in4      (1'b0),                               // (terminated)
		.reset_req_in4  (1'b0),                               // (terminated)
		.reset_in5      (1'b0),                               // (terminated)
		.reset_req_in5  (1'b0),                               // (terminated)
		.reset_in6      (1'b0),                               // (terminated)
		.reset_req_in6  (1'b0),                               // (terminated)
		.reset_in7      (1'b0),                               // (terminated)
		.reset_req_in7  (1'b0),                               // (terminated)
		.reset_in8      (1'b0),                               // (terminated)
		.reset_req_in8  (1'b0),                               // (terminated)
		.reset_in9      (1'b0),                               // (terminated)
		.reset_req_in9  (1'b0),                               // (terminated)
		.reset_in10     (1'b0),                               // (terminated)
		.reset_req_in10 (1'b0),                               // (terminated)
		.reset_in11     (1'b0),                               // (terminated)
		.reset_req_in11 (1'b0),                               // (terminated)
		.reset_in12     (1'b0),                               // (terminated)
		.reset_req_in12 (1'b0),                               // (terminated)
		.reset_in13     (1'b0),                               // (terminated)
		.reset_req_in13 (1'b0),                               // (terminated)
		.reset_in14     (1'b0),                               // (terminated)
		.reset_req_in14 (1'b0),                               // (terminated)
		.reset_in15     (1'b0),                               // (terminated)
		.reset_req_in15 (1'b0)                                // (terminated)
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller_002 (
		.reset_in0      (~pcie_hip_avmm_nreset_status_reset), // reset_in0.reset
		.clk            (pcie_hip_avmm_coreclkout_clk),       //       clk.clk
		.reset_out      (rst_controller_002_reset_out_reset), // reset_out.reset
		.reset_req      (),                                   // (terminated)
		.reset_req_in0  (1'b0),                               // (terminated)
		.reset_in1      (1'b0),                               // (terminated)
		.reset_req_in1  (1'b0),                               // (terminated)
		.reset_in2      (1'b0),                               // (terminated)
		.reset_req_in2  (1'b0),                               // (terminated)
		.reset_in3      (1'b0),                               // (terminated)
		.reset_req_in3  (1'b0),                               // (terminated)
		.reset_in4      (1'b0),                               // (terminated)
		.reset_req_in4  (1'b0),                               // (terminated)
		.reset_in5      (1'b0),                               // (terminated)
		.reset_req_in5  (1'b0),                               // (terminated)
		.reset_in6      (1'b0),                               // (terminated)
		.reset_req_in6  (1'b0),                               // (terminated)
		.reset_in7      (1'b0),                               // (terminated)
		.reset_req_in7  (1'b0),                               // (terminated)
		.reset_in8      (1'b0),                               // (terminated)
		.reset_req_in8  (1'b0),                               // (terminated)
		.reset_in9      (1'b0),                               // (terminated)
		.reset_req_in9  (1'b0),                               // (terminated)
		.reset_in10     (1'b0),                               // (terminated)
		.reset_req_in10 (1'b0),                               // (terminated)
		.reset_in11     (1'b0),                               // (terminated)
		.reset_req_in11 (1'b0),                               // (terminated)
		.reset_in12     (1'b0),                               // (terminated)
		.reset_req_in12 (1'b0),                               // (terminated)
		.reset_in13     (1'b0),                               // (terminated)
		.reset_req_in13 (1'b0),                               // (terminated)
		.reset_in14     (1'b0),                               // (terminated)
		.reset_req_in14 (1'b0),                               // (terminated)
		.reset_in15     (1'b0),                               // (terminated)
		.reset_req_in15 (1'b0)                                // (terminated)
	);

	assign coreclk_fanout_clk_reset_reset_n = ~custom_reset_synchronizer_0_reset_out_reset;

	assign coreclkout_out_clk = coreclk_fanout_clk_clk;

	assign nreset_status_out_reset_reset_n = coreclk_fanout_clk_reset_reset_n;

endmodule
