datasheet for cam_dbg

cam_dbg |

2021.05.31.09:50:18 | Datasheet

Overview

Memory Map

## signaltap_ii_logic_analyzer_0

altera_signaltap_ii_logic_analyzer v18.1

## Parameters

device_family | CYCLONEV
sld_data_bits | 32
sld_sample_depth | 4096
gui_ram_type | AUTO
sld_ram_block_type | AUTO
gui_use_segmented | false
gui_num_segments | 2
gui_sample_per_segment |
sld_segment_size | 0
gui_sq | Continuous
sld_storage_qualifier_mode | OFF
sld_storage_qualifier_gap_record | 0
sld_trigger_bits | 4
sld_trigger_level | 1
sld_trigger_in_enabled | 1
gui_trigger_out_enabled | false
sld_enable_advanced_trigger | 0
sld_trigger_level_pipeline | 1
sld_pipeline_factor | 0
sld_trigger_pipeline | 0
sld_ram_pipeline | 0
sld_counter_pipeline | 0
sld_node_info | 806383104
sld_incremental_routing | 0
sld_node_crc_bits | 32
sld_node_crc_hiword | 27747
sld_node_crc_loword | 30497
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

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