module ghrd_top (
    // FPGA peripherals ports
    input       [ 1:0]  fpga_dipsw_pio,
    output      [ 3:0]  fpga_led_pio,
    input               fpga_button_pio,
    output              heart_beat_led,

    // HPS memory controller ports
    output      [15:0]  hps_memory_mem_a,
    output      [ 2:0]  hps_memory_mem_ba,
    output              hps_memory_mem_ck,
    output              hps_memory_mem_ck_n,
    output              hps_memory_mem_cke,
    output              hps_memory_mem_cs_n,
    output              hps_memory_mem_ras_n,
    output              hps_memory_mem_cas_n,
    output              hps_memory_mem_we_n,
    output              hps_memory_mem_reset_n,
    inout       [31:0]  hps_memory_mem_dq,
    inout       [ 3:0]  hps_memory_mem_dqs,
    inout       [ 3:0]  hps_memory_mem_dqs_n,
    output              hps_memory_mem_odt,
    output      [ 3:0]  hps_memory_mem_dm,
    input               hps_memory_oct_rzqin,

    // HPS peripherals
    output              hps_emac1_TX_CLK,
    output              hps_emac1_TXD0,
    output              hps_emac1_TXD1,
    output              hps_emac1_TXD2,
    output              hps_emac1_TXD3,
    input               hps_emac1_RXD0,
    inout               hps_emac1_MDIO,
    output              hps_emac1_MDC,
    input               hps_emac1_RX_CTL,
    output              hps_emac1_TX_CTL,
    input               hps_emac1_RX_CLK,
    input               hps_emac1_RXD1,
    input               hps_emac1_RXD2,
    input               hps_emac1_RXD3,
    inout               hps_qspi_IO0,
    inout               hps_qspi_IO1,
    inout               hps_qspi_IO2,
    inout               hps_qspi_IO3,
    output              hps_qspi_SS0,
    output              hps_qspi_CLK,
    inout               hps_sdio_CMD,
    inout               hps_sdio_D0,
    inout               hps_sdio_D1,
    output              hps_sdio_CLK,
    inout               hps_sdio_D2,
    inout               hps_sdio_D3,
    inout               hps_usb1_D0,
    inout               hps_usb1_D1,
    inout               hps_usb1_D2,
    inout               hps_usb1_D3,
    inout               hps_usb1_D4,
    inout               hps_usb1_D5,
    inout               hps_usb1_D6,
    inout               hps_usb1_D7,
    input               hps_usb1_CLK,
    output              hps_usb1_STP,
    input               hps_usb1_DIR,
    input               hps_usb1_NXT,
    output              hps_spim0_CLK,
    output              hps_spim0_MOSI,
    input               hps_spim0_MISO,
    output              hps_spim0_SS0,
    input               hps_uart0_RX,
    output              hps_uart0_TX,
    inout               hps_i2c0_SDA,
    inout               hps_i2c0_SCL,
    inout               hps_i2c1_SDA,
    inout               hps_i2c1_SCL,
    inout               hps_gpio_GPIO00,
    inout               hps_gpio_GPIO09,
    inout               hps_gpio_GPIO28,
    inout               hps_gpio_GPIO35,
    inout               hps_gpio_GPIO37,
    inout               hps_gpio_GPIO41,			// USB_RESET
    inout               hps_gpio_GPIO54,
    inout               hps_gpio_GPIO55,
    inout               hps_gpio_GPIO61,

    // PCIe signals
    input               pcie_refclk_clk,
    input               pcie_npor_pin_perst,
    input               pcie_hip_rx_in0,
    output              pcie_hip_tx_out0,
    output              pcie_perstn_out,

    // M.2 signals
    output              pewake_n,
    output              clkreq_n,
    
    // DVI Out signals
    output              dvi_clk,
    output      [23:0]  dvi_data,
    output              dvi_de,
    output              dvi_hsync,
    output              dvi_vsync,
    output              dvi_pd_n,
    output              dvi_pwr_en,
    input               dvi_hpd,
    input               dvi_cec,
    inout               dvi_scl,
    inout               dvi_sda,

    // Camera Parallel I/F signals
    input               cam_pclk,
    input       [15:0]  cam_data,
    input               cam_vsync,
    input               cam_hsync,
    output              cam_nrst,
    output              cam_refclk,
    output              cam_ncs,
    input       [ 2:0]  cam_gpio,
    
    // MIPI CSI-2
    input               mipi_hs_clk,
    input       [ 3:0]  mipi_hs_data,
    input               mipi_lp_clk_p,
    input               mipi_lp_clk_n,
    input       [ 3:0]  mipi_lp_data_p,
    input       [ 3:0]  mipi_lp_data_n,
    output      [ 1:0]  mipi0_gpio,
    output      [ 1:0]  mipi1_gpio,
     
    // FPGA clock and reset
    input               fpga_clk_50,
    input               fpga_clk1_50,
    input               fpga_clk_100,
    input               fpga_clk_27
);

// internal wires and registers declaration
wire                fpga_debounced_buttons;
wire    [ 3:0]      fpga_led_internal;
wire                fpga_led_internal_rp_pio;
wire                hps_fpga_reset_n;
wire                pcie_npor_npor;
wire    [ 4:0]      pipe_sim_ltssmstate;
wire                coreclk_fan_clk;
wire                coreclk_fan_reset_n;
wire                pcie_reconfig_clk_locked_fixedclk_locked;
reg                 alive_led;
reg     [25:0]      alive_cnt;
wire    [ 2:0]      hps_reset_req;
wire                hps_cold_reset;
wire                hps_warm_reset;
wire                hps_debug_reset;
wire    [27:0]      stm_hw_events;
wire                pll_locked;
wire	[15:0]		cam_pio;

// connection of internal logics
assign fpga_led_pio     =  fpga_led_internal;
assign stm_hw_events    =  {{21{1'b0}}, fpga_dipsw_pio, fpga_led_internal, fpga_debounced_buttons};
assign pcie_perstn_out  = ~fpga_led_internal_rp_pio;
assign pcie_npor_npor   =  hps_fpga_reset_n & pcie_npor_pin_perst;
assign dvi_pd_n         =  hps_fpga_reset_n;
assign dvi_pwr_en       =  hps_fpga_reset_n;
assign pewake_n         =  1'b1;
assign clkreq_n         =  1'b1;
assign heart_beat_led   =  alive_led;
assign mipi0_gpio[0]	=  cam_pio[3];
assign mipi0_gpio[1]	=  cam_pio[2];
assign mipi1_gpio[0]	=  1'b0;
assign mipi1_gpio[1]	=  1'b0;
assign cam_nrst			=  cam_pio[1];
assign cam_ncs			=  1'b0;

// Camera Video Input signals
reg		[ 1:0]		cam_vsync_r;
reg		[ 1:0]		cam_hsync_r;
reg		[ 9:0]		cam_data_r;

always @( posedge cam_pclk or negedge hps_fpga_reset_n ) begin
    if( !hps_fpga_reset_n ) begin
		cam_vsync_r		<= 2'd0;
		cam_hsync_r		<= 2'd0;
		cam_data_r		<= 10'd0;
	end
	else begin
		cam_vsync_r		<= {cam_vsync_r[0], cam_vsync};
		cam_hsync_r		<= {cam_hsync_r[0], cam_hsync};
		cam_data_r		<= cam_data[9:0];
	end
end

wire				rise_vsync		=  cam_vsync_r[0] & ~cam_vsync_r[1];
wire				cam_enable		=  cam_pio[0];
reg		[ 1:0]		cam_enable_r;

always @( posedge cam_pclk or negedge hps_fpga_reset_n ) begin
    if     ( !hps_fpga_reset_n )	cam_enable_r		<= 2'd0;
	else							cam_enable_r		<= {cam_enable_r[0], cam_enable};
end

// V latch Register
reg					enb_v_r;
reg		[ 1:0]		bit_v_r;
reg		[ 1:0]		size_v_r;
reg		[ 1:0]		align_v_r;

always @( posedge cam_pclk or negedge hps_fpga_reset_n ) begin
    if     ( !hps_fpga_reset_n ) begin
		enb_v_r				<= 1'b0;
		bit_v_r				<= 2'd0;
		size_v_r			<= 2'd0;
		align_v_r			<= 2'd0;
	end
	else if( rise_vsync ) begin
		enb_v_r				<= cam_enable_r[1];
		bit_v_r				<= cam_pio[7:6];
		size_v_r			<= cam_pio[5:4];
		align_v_r			<= cam_pio[9:8];
	end
end

wire	[ 7:0]		cam_data_8cr	= ( bit_v_r == 2'b11 )?
										(cam_data_r[9:2] == 8'hff)?	8'hff
																 :	{cam_data_r[9:2] + cam_data_r[1]}
									: ( bit_v_r == 2'b10 )?
										(cam_data_r[9]   == 1'b1 ||
										 cam_data_r[8:1] == 8'hff)?	8'hff
																 :	{cam_data_r[8:1] + cam_data_r[0]}
									:	(cam_data_r[9:8] != 2'd0)?	8'hff
																 :	cam_data_r[7:0];
reg		[ 7:0]		cam_data_8cr_r;

always @( posedge cam_pclk or negedge hps_fpga_reset_n ) begin
    if     ( !hps_fpga_reset_n )	cam_data_8cr_r		<= 8'd0;
	else							cam_data_8cr_r		<= cam_data_8cr;
end

wire	[10:0]		cam_width		= ( size_v_r == 2'b11 )? 11'd640 : 11'd1920;
wire	[10:0]		cam_height		= ( size_v_r == 2'b11 )? 11'd480 : 11'd1080;
wire	[10:0]		cam_hblank		= ( size_v_r == 2'b11 )? 11'd200 : 11'd400;
wire				raw_vsync		= cam_vsync_r[1] & enb_v_r;
wire				raw_hsync		= cam_hsync_r[1] & enb_v_r;
wire	[ 7:0]		raw_data		= cam_data_8cr_r;
wire				rgb_vsync;
wire				rgb_hsync;
wire	[23:0]		rgb_data;

raw2rgb #(
	.P_RAW_BW		( 8		),
	.P_RGB_BW		( 8		),
	.P_WDH_BW		( 11	),
	.P_HGT_BW		( 11	)
) raw2rgb_inst (
	.i_rst_n		( hps_fpga_reset_n		),
	.i_pclk			( cam_pclk				),
	.i_vsync		( raw_vsync				),
	.i_hsync		( raw_hsync				),
	.i_pdat			( raw_data				),
	.i_width		( cam_width				),
	.i_height		( cam_height			),
	.i_hblank		( cam_hblank			),
	.i_align		( align_v_r				),
	.o_vsync		( rgb_vsync				),
	.o_hsync		( rgb_hsync				),
	.o_pdat			( rgb_data				)
);


// logic for LED display derivation
always @(posedge coreclk_fan_clk or negedge coreclk_fan_reset_n) begin
    if (!coreclk_fan_reset_n) begin
        alive_led <= 1'b0;
        alive_cnt <= 26'd0;
    end else begin
        alive_led <= alive_cnt[25];
        alive_cnt <= alive_cnt + 26'd1;
    end
end

// Video & Camera PLL 74.25MHz & 27MHz
wire				vid_clk;

vid_pll_74_25	vid_pll_74_25_inst (
    .refclk			( fpga_clk_27			),
    .rst			(~hps_fpga_reset_n		),
    .outclk_0		( vid_clk				),			// 74.25MHz
    .outclk_1		( dvi_clk				),			// 74.25MHz( invert )
    .outclk_2		( cam_refclk			),			// 27MHz
    .locked			( pll_locked			)
);

// SoC sub-system module
soc_system soc_inst (
     // HPS I/O Interface
    .hps_0_hps_io_hps_io_emac1_inst_TX_CLK      ( hps_emac1_TX_CLK              ),
    .hps_0_hps_io_hps_io_emac1_inst_TXD0        ( hps_emac1_TXD0                ),
    .hps_0_hps_io_hps_io_emac1_inst_TXD1        ( hps_emac1_TXD1                ),
    .hps_0_hps_io_hps_io_emac1_inst_TXD2        ( hps_emac1_TXD2                ),
    .hps_0_hps_io_hps_io_emac1_inst_TXD3        ( hps_emac1_TXD3                ),
    .hps_0_hps_io_hps_io_emac1_inst_RXD0        ( hps_emac1_RXD0                ),
    .hps_0_hps_io_hps_io_emac1_inst_MDIO        ( hps_emac1_MDIO                ),
    .hps_0_hps_io_hps_io_emac1_inst_MDC         ( hps_emac1_MDC                 ),
    .hps_0_hps_io_hps_io_emac1_inst_RX_CTL      ( hps_emac1_RX_CTL              ),
    .hps_0_hps_io_hps_io_emac1_inst_TX_CTL      ( hps_emac1_TX_CTL              ),
    .hps_0_hps_io_hps_io_emac1_inst_RX_CLK      ( hps_emac1_RX_CLK              ),
    .hps_0_hps_io_hps_io_emac1_inst_RXD1        ( hps_emac1_RXD1                ),
    .hps_0_hps_io_hps_io_emac1_inst_RXD2        ( hps_emac1_RXD2                ),
    .hps_0_hps_io_hps_io_emac1_inst_RXD3        ( hps_emac1_RXD3                ),
    .hps_0_hps_io_hps_io_qspi_inst_IO0          ( hps_qspi_IO0                  ),
    .hps_0_hps_io_hps_io_qspi_inst_IO1          ( hps_qspi_IO1                  ),
    .hps_0_hps_io_hps_io_qspi_inst_IO2          ( hps_qspi_IO2                  ),
    .hps_0_hps_io_hps_io_qspi_inst_IO3          ( hps_qspi_IO3                  ),
    .hps_0_hps_io_hps_io_qspi_inst_SS0          ( hps_qspi_SS0                  ),
    .hps_0_hps_io_hps_io_qspi_inst_CLK          ( hps_qspi_CLK                  ),
    .hps_0_hps_io_hps_io_sdio_inst_CMD          ( hps_sdio_CMD                  ),
    .hps_0_hps_io_hps_io_sdio_inst_D0           ( hps_sdio_D0                   ),
    .hps_0_hps_io_hps_io_sdio_inst_D1           ( hps_sdio_D1                   ),
    .hps_0_hps_io_hps_io_sdio_inst_CLK          ( hps_sdio_CLK                  ),
    .hps_0_hps_io_hps_io_sdio_inst_D2           ( hps_sdio_D2                   ),
    .hps_0_hps_io_hps_io_sdio_inst_D3           ( hps_sdio_D3                   ),
    .hps_0_hps_io_hps_io_usb1_inst_D0           ( hps_usb1_D0                   ),
    .hps_0_hps_io_hps_io_usb1_inst_D1           ( hps_usb1_D1                   ),
    .hps_0_hps_io_hps_io_usb1_inst_D2           ( hps_usb1_D2                   ),
    .hps_0_hps_io_hps_io_usb1_inst_D3           ( hps_usb1_D3                   ),
    .hps_0_hps_io_hps_io_usb1_inst_D4           ( hps_usb1_D4                   ),
    .hps_0_hps_io_hps_io_usb1_inst_D5           ( hps_usb1_D5                   ),
    .hps_0_hps_io_hps_io_usb1_inst_D6           ( hps_usb1_D6                   ),
    .hps_0_hps_io_hps_io_usb1_inst_D7           ( hps_usb1_D7                   ),
    .hps_0_hps_io_hps_io_usb1_inst_CLK          ( hps_usb1_CLK                  ),
    .hps_0_hps_io_hps_io_usb1_inst_STP          ( hps_usb1_STP                  ),
    .hps_0_hps_io_hps_io_usb1_inst_DIR          ( hps_usb1_DIR                  ),
    .hps_0_hps_io_hps_io_usb1_inst_NXT          ( hps_usb1_NXT                  ),
    .hps_0_hps_io_hps_io_spim0_inst_CLK         ( hps_spim0_CLK                 ),
    .hps_0_hps_io_hps_io_spim0_inst_MOSI        ( hps_spim0_MOSI                ),
    .hps_0_hps_io_hps_io_spim0_inst_MISO        ( hps_spim0_MISO                ),
    .hps_0_hps_io_hps_io_spim0_inst_SS0         ( hps_spim0_SS0                 ),
    .hps_0_hps_io_hps_io_uart0_inst_RX          ( hps_uart0_RX                  ),
    .hps_0_hps_io_hps_io_uart0_inst_TX          ( hps_uart0_TX                  ),
    .hps_0_hps_io_hps_io_i2c0_inst_SDA          ( hps_i2c0_SDA                  ),
    .hps_0_hps_io_hps_io_i2c0_inst_SCL          ( hps_i2c0_SCL                  ),
    .hps_0_hps_io_hps_io_i2c1_inst_SDA          ( hps_i2c1_SDA                  ),
    .hps_0_hps_io_hps_io_i2c1_inst_SCL          ( hps_i2c1_SCL                  ),
	.hps_0_hps_io_hps_io_gpio_inst_GPIO00		( hps_gpio_GPIO00				),
	.hps_0_hps_io_hps_io_gpio_inst_GPIO09		( hps_gpio_GPIO09				),
	.hps_0_hps_io_hps_io_gpio_inst_GPIO28		( hps_gpio_GPIO28				),
	.hps_0_hps_io_hps_io_gpio_inst_GPIO35		( hps_gpio_GPIO35				),
	.hps_0_hps_io_hps_io_gpio_inst_GPIO37		( hps_gpio_GPIO37				),
	.hps_0_hps_io_hps_io_gpio_inst_GPIO41		( hps_gpio_GPIO41				),
	.hps_0_hps_io_hps_io_gpio_inst_GPIO54		( hps_gpio_GPIO54				),
	.hps_0_hps_io_hps_io_gpio_inst_GPIO55		( hps_gpio_GPIO55				),
	.hps_0_hps_io_hps_io_gpio_inst_GPIO61		( hps_gpio_GPIO61				),
    .hps_0_f2h_stm_hw_events_stm_hwevents       ( stm_hw_events                 ),
    .pio_rp_reset_external_connection_in_port   ( fpga_led_internal_rp_pio      ),
    .pio_rp_reset_external_connection_out_port  ( fpga_led_internal_rp_pio      ),

    // HPS Memory Interface
    .memory_mem_a                               ( hps_memory_mem_a              ),
    .memory_mem_ba                              ( hps_memory_mem_ba             ),
    .memory_mem_ck                              ( hps_memory_mem_ck             ),
    .memory_mem_ck_n                            ( hps_memory_mem_ck_n           ),
    .memory_mem_cke                             ( hps_memory_mem_cke            ),
    .memory_mem_cs_n                            ( hps_memory_mem_cs_n           ),
    .memory_mem_ras_n                           ( hps_memory_mem_ras_n          ),
    .memory_mem_cas_n                           ( hps_memory_mem_cas_n          ),
    .memory_mem_we_n                            ( hps_memory_mem_we_n           ),
    .memory_mem_reset_n                         ( hps_memory_mem_reset_n        ),
    .memory_mem_dq                              ( hps_memory_mem_dq             ),
    .memory_mem_dqs                             ( hps_memory_mem_dqs            ),
    .memory_mem_dqs_n                           ( hps_memory_mem_dqs_n          ),
    .memory_mem_odt                             ( hps_memory_mem_odt            ),
    .memory_mem_dm                              ( hps_memory_mem_dm             ),
    .memory_oct_rzqin                           ( hps_memory_oct_rzqin          ),

     // FPGA I/O Interface
    .dipsw_pio_external_connection_export       ( fpga_dipsw_pio                ),
    .led_pio_external_connection_in_port        ( fpga_led_internal             ),
    .led_pio_external_connection_out_port       ( fpga_led_internal             ),
    .button_pio_external_connection_export      ( fpga_debounced_buttons        ),

    // PCIe(M.2) Interface
    .pcie_hip_avmm_hip_ctrl_test_in             ( 32'hA8                        ),
    .pcie_hip_avmm_hip_ctrl_simu_mode_pipe      ( 1'b0                          ),
    .pcie_hip_avmm_refclk_clk                   ( pcie_refclk_clk               ),
    .pcie_hip_avmm_npor_npor                    ( pcie_npor_npor                ),
    .pcie_hip_avmm_npor_pin_perst               ( pcie_npor_pin_perst           ),
    .pcie_hip_avmm_reconfig_clk_locked_fixedclk_locked (pcie_reconfig_clk_locked_fixedclk_locked ),
    .pcie_hip_avmm_hip_serial_rx_in0            ( pcie_hip_rx_in0               ),
    .pcie_hip_avmm_hip_serial_tx_out0           ( pcie_hip_tx_out0              ),
    .pcie_hip_avmm_hip_pipe_sim_pipe_pclk_in    ( 1'b0                          ),
    .pcie_hip_avmm_hip_pipe_sim_ltssmstate      ( pipe_sim_ltssmstate           ),
    .pcie_hip_avmm_hip_pipe_phystatus0          ( 1'b0                          ),
    .pcie_hip_avmm_hip_pipe_rxdata0             ( 8'h0                          ),
    .pcie_hip_avmm_hip_pipe_rxdatak0            ( 8'h0                          ),
    .pcie_hip_avmm_hip_pipe_rxelecidle0         ( 1'b0                          ),
    .pcie_hip_avmm_hip_pipe_rxstatus0           ( 3'h0                          ),
    .pcie_hip_avmm_hip_pipe_rxvalid0            ( 1'b0                          ),
    .alt_xcvr_reconfig_0_reconfig_mgmt_address  ( 7'h0                          ),
    .alt_xcvr_reconfig_0_reconfig_mgmt_read     ( 1'b0                          ),
    .alt_xcvr_reconfig_0_reconfig_mgmt_write    ( 1'b0                          ),
    .alt_xcvr_reconfig_0_reconfig_mgmt_writedata( 32'h0                         ),

     // HDMI Interface
    .vid_out_vid_clk                            ( vid_clk                       ),
    .vid_out_vid_data                           ( dvi_data                      ),
    .vid_out_underflow                          (                               ),
    .vid_out_vid_datavalid                      ( dvi_de                        ),
    .vid_out_vid_v_sync                         ( dvi_vsync                     ),
    .vid_out_vid_h_sync                         ( dvi_hsync                     ),
    .vid_out_vid_f                              (                               ),
    .vid_out_vid_h                              (                               ),
    .vid_out_vid_v                              (                               ),
    .vid_clk_clk                                ( vid_clk                       ),
    .vid_reset_reset_n                          ( pll_locked                    ),

     // Camera Interface
    .cam_in_vid_clk                             ( cam_pclk                      ),
    .cam_in_vid_data                            ( rgb_data						),
    .cam_in_vid_de                              ( rgb_hsync						),
    .cam_in_vid_datavalid                       ( 1'b1                          ),
    .cam_in_vid_locked                          ( enb_v_r						),
    .cam_in_vid_f                               ( 1'b0                          ),	// clocked video field signal for interlaced
    .cam_in_vid_v_sync                          (~rgb_vsync						),
    .cam_in_vid_h_sync                          (~rgb_hsync						),
    .cam_in_vid_hd_sdn                          ( 1'b1                          ),	// color plane format  0:sequential, 1:parallel

    .cam_in_vid_color_encoding                  ( 8'b0                          ),
    .cam_in_vid_bit_width                       ( 8'b0                          ),
    .cam_in_sof                                 (                               ),
    .cam_in_sof_locked                          (                               ),
    .cam_in_refclk_div                          (                               ),
    .cam_in_clipping                            (                               ),
    .cam_in_padding                             (                               ),
    .cam_in_overflow                            (                               ),
	.cam_pio_export								( cam_pio						),
	
     // Clock & Reset
    .coreclk_fanout_clk_clk                     ( coreclk_fan_clk               ),
    .coreclk_fanout_clk_reset_reset_n           ( coreclk_fan_reset_n           ),
    .clk_clk                                    ( fpga_clk_50                   ),
    .hps_0_h2f_reset_reset_n                    ( hps_fpga_reset_n              ),
    .reset_reset_n                              ( hps_fpga_reset_n              ),
    .issp_hps_resets_source                     ( hps_reset_req                 ),
    .hps_0_f2h_cold_reset_req_reset_n           (~hps_cold_reset                ),
    .hps_0_f2h_warm_reset_req_reset_n           (~hps_warm_reset                ),
    .hps_0_f2h_debug_reset_req_reset_n          (~hps_debug_reset               )
);

// Debounce logic to clean out glitches within 1ms
debounce debounce_inst (
    .clk        ( fpga_clk_50               ),
    .reset_n    ( hps_fpga_reset_n          ),
    .data_in    ( fpga_button_pio           ),
    .data_out   ( fpga_debounced_buttons    )
);
defparam debounce_inst.WIDTH         = 1;
defparam debounce_inst.POLARITY      = "LOW";
defparam debounce_inst.TIMEOUT       = 50000;       // at 50Mhz this is a debounce time of 1ms
defparam debounce_inst.TIMEOUT_WIDTH = 16;          // ceil(log2(TIMEOUT))

altera_edge_detector pulse_cold_reset (
    .clk        ( fpga_clk_50       ),
    .rst_n      ( hps_fpga_reset_n  ),
    .signal_in  ( hps_reset_req[0]  ),
    .pulse_out  ( hps_cold_reset    )
);
defparam pulse_cold_reset.PULSE_EXT             = 6;
defparam pulse_cold_reset.EDGE_TYPE             = 1;
defparam pulse_cold_reset.IGNORE_RST_WHILE_BUSY = 1;

altera_edge_detector pulse_warm_reset (
    .clk        ( fpga_clk_50       ),
    .rst_n      ( hps_fpga_reset_n  ),
    .signal_in  ( hps_reset_req[1]  ),
    .pulse_out  ( hps_warm_reset    )
);
defparam pulse_warm_reset.PULSE_EXT             = 2;
defparam pulse_warm_reset.EDGE_TYPE             = 1;
defparam pulse_warm_reset.IGNORE_RST_WHILE_BUSY = 1;

altera_edge_detector pulse_debug_reset (
    .clk        ( fpga_clk_50       ),
    .rst_n      ( hps_fpga_reset_n  ),
    .signal_in  ( hps_reset_req[2]  ),
    .pulse_out  ( hps_debug_reset   )
);
defparam pulse_debug_reset.PULSE_EXT             = 32;
defparam pulse_debug_reset.EDGE_TYPE             = 1;
defparam pulse_debug_reset.IGNORE_RST_WHILE_BUSY = 1;

endmodule
