// soc_system_pcie_0_mm_interconnect_2.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 18.1 646

`timescale 1 ps / 1 ps
module soc_system_pcie_0_mm_interconnect_2 (
		input  wire        custom_reset_synchronizer_0_clock_out_clk,                      //                    custom_reset_synchronizer_0_clock_out.clk
		input  wire        pcie_hip_avmm_coreclkout_clk,                                   //                                 pcie_hip_avmm_coreclkout.clk
		input  wire        ccb_h2f_m0_reset_reset_bridge_in_reset_reset,                   //                   ccb_h2f_m0_reset_reset_bridge_in_reset.reset
		input  wire        pcie_hip_avmm_Txs_translator_reset_reset_bridge_in_reset_reset, // pcie_hip_avmm_Txs_translator_reset_reset_bridge_in_reset.reset
		input  wire [27:0] ccb_h2f_m0_address,                                             //                                               ccb_h2f_m0.address
		output wire        ccb_h2f_m0_waitrequest,                                         //                                                         .waitrequest
		input  wire [6:0]  ccb_h2f_m0_burstcount,                                          //                                                         .burstcount
		input  wire [7:0]  ccb_h2f_m0_byteenable,                                          //                                                         .byteenable
		input  wire        ccb_h2f_m0_read,                                                //                                                         .read
		output wire [63:0] ccb_h2f_m0_readdata,                                            //                                                         .readdata
		output wire        ccb_h2f_m0_readdatavalid,                                       //                                                         .readdatavalid
		input  wire        ccb_h2f_m0_write,                                               //                                                         .write
		input  wire [63:0] ccb_h2f_m0_writedata,                                           //                                                         .writedata
		input  wire        ccb_h2f_m0_debugaccess,                                         //                                                         .debugaccess
		input  wire [27:0] pb_msgdma_2_txs_m0_address,                                     //                                       pb_msgdma_2_txs_m0.address
		output wire        pb_msgdma_2_txs_m0_waitrequest,                                 //                                                         .waitrequest
		input  wire [6:0]  pb_msgdma_2_txs_m0_burstcount,                                  //                                                         .burstcount
		input  wire [7:0]  pb_msgdma_2_txs_m0_byteenable,                                  //                                                         .byteenable
		input  wire        pb_msgdma_2_txs_m0_read,                                        //                                                         .read
		output wire [63:0] pb_msgdma_2_txs_m0_readdata,                                    //                                                         .readdata
		output wire        pb_msgdma_2_txs_m0_readdatavalid,                               //                                                         .readdatavalid
		input  wire        pb_msgdma_2_txs_m0_write,                                       //                                                         .write
		input  wire [63:0] pb_msgdma_2_txs_m0_writedata,                                   //                                                         .writedata
		input  wire        pb_msgdma_2_txs_m0_debugaccess,                                 //                                                         .debugaccess
		output wire [27:0] pcie_hip_avmm_Txs_address,                                      //                                        pcie_hip_avmm_Txs.address
		output wire        pcie_hip_avmm_Txs_write,                                        //                                                         .write
		output wire        pcie_hip_avmm_Txs_read,                                         //                                                         .read
		input  wire [63:0] pcie_hip_avmm_Txs_readdata,                                     //                                                         .readdata
		output wire [63:0] pcie_hip_avmm_Txs_writedata,                                    //                                                         .writedata
		output wire [6:0]  pcie_hip_avmm_Txs_burstcount,                                   //                                                         .burstcount
		output wire [7:0]  pcie_hip_avmm_Txs_byteenable,                                   //                                                         .byteenable
		input  wire        pcie_hip_avmm_Txs_readdatavalid,                                //                                                         .readdatavalid
		input  wire        pcie_hip_avmm_Txs_waitrequest,                                  //                                                         .waitrequest
		output wire        pcie_hip_avmm_Txs_chipselect                                    //                                                         .chipselect
	);

	wire          ccb_h2f_m0_translator_avalon_universal_master_0_waitrequest;           // ccb_h2f_m0_agent:av_waitrequest -> ccb_h2f_m0_translator:uav_waitrequest
	wire   [63:0] ccb_h2f_m0_translator_avalon_universal_master_0_readdata;              // ccb_h2f_m0_agent:av_readdata -> ccb_h2f_m0_translator:uav_readdata
	wire          ccb_h2f_m0_translator_avalon_universal_master_0_debugaccess;           // ccb_h2f_m0_translator:uav_debugaccess -> ccb_h2f_m0_agent:av_debugaccess
	wire   [27:0] ccb_h2f_m0_translator_avalon_universal_master_0_address;               // ccb_h2f_m0_translator:uav_address -> ccb_h2f_m0_agent:av_address
	wire          ccb_h2f_m0_translator_avalon_universal_master_0_read;                  // ccb_h2f_m0_translator:uav_read -> ccb_h2f_m0_agent:av_read
	wire    [7:0] ccb_h2f_m0_translator_avalon_universal_master_0_byteenable;            // ccb_h2f_m0_translator:uav_byteenable -> ccb_h2f_m0_agent:av_byteenable
	wire          ccb_h2f_m0_translator_avalon_universal_master_0_readdatavalid;         // ccb_h2f_m0_agent:av_readdatavalid -> ccb_h2f_m0_translator:uav_readdatavalid
	wire          ccb_h2f_m0_translator_avalon_universal_master_0_lock;                  // ccb_h2f_m0_translator:uav_lock -> ccb_h2f_m0_agent:av_lock
	wire          ccb_h2f_m0_translator_avalon_universal_master_0_write;                 // ccb_h2f_m0_translator:uav_write -> ccb_h2f_m0_agent:av_write
	wire   [63:0] ccb_h2f_m0_translator_avalon_universal_master_0_writedata;             // ccb_h2f_m0_translator:uav_writedata -> ccb_h2f_m0_agent:av_writedata
	wire    [9:0] ccb_h2f_m0_translator_avalon_universal_master_0_burstcount;            // ccb_h2f_m0_translator:uav_burstcount -> ccb_h2f_m0_agent:av_burstcount
	wire          rsp_mux_src_valid;                                                     // rsp_mux:src_valid -> ccb_h2f_m0_agent:rp_valid
	wire  [140:0] rsp_mux_src_data;                                                      // rsp_mux:src_data -> ccb_h2f_m0_agent:rp_data
	wire          rsp_mux_src_ready;                                                     // ccb_h2f_m0_agent:rp_ready -> rsp_mux:src_ready
	wire    [1:0] rsp_mux_src_channel;                                                   // rsp_mux:src_channel -> ccb_h2f_m0_agent:rp_channel
	wire          rsp_mux_src_startofpacket;                                             // rsp_mux:src_startofpacket -> ccb_h2f_m0_agent:rp_startofpacket
	wire          rsp_mux_src_endofpacket;                                               // rsp_mux:src_endofpacket -> ccb_h2f_m0_agent:rp_endofpacket
	wire          pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_waitrequest;   // pb_msgdma_2_txs_m0_agent:av_waitrequest -> pb_msgdma_2_txs_m0_translator:uav_waitrequest
	wire   [63:0] pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_readdata;      // pb_msgdma_2_txs_m0_agent:av_readdata -> pb_msgdma_2_txs_m0_translator:uav_readdata
	wire          pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_debugaccess;   // pb_msgdma_2_txs_m0_translator:uav_debugaccess -> pb_msgdma_2_txs_m0_agent:av_debugaccess
	wire   [27:0] pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_address;       // pb_msgdma_2_txs_m0_translator:uav_address -> pb_msgdma_2_txs_m0_agent:av_address
	wire          pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_read;          // pb_msgdma_2_txs_m0_translator:uav_read -> pb_msgdma_2_txs_m0_agent:av_read
	wire    [7:0] pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_byteenable;    // pb_msgdma_2_txs_m0_translator:uav_byteenable -> pb_msgdma_2_txs_m0_agent:av_byteenable
	wire          pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_readdatavalid; // pb_msgdma_2_txs_m0_agent:av_readdatavalid -> pb_msgdma_2_txs_m0_translator:uav_readdatavalid
	wire          pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_lock;          // pb_msgdma_2_txs_m0_translator:uav_lock -> pb_msgdma_2_txs_m0_agent:av_lock
	wire          pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_write;         // pb_msgdma_2_txs_m0_translator:uav_write -> pb_msgdma_2_txs_m0_agent:av_write
	wire   [63:0] pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_writedata;     // pb_msgdma_2_txs_m0_translator:uav_writedata -> pb_msgdma_2_txs_m0_agent:av_writedata
	wire    [9:0] pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_burstcount;    // pb_msgdma_2_txs_m0_translator:uav_burstcount -> pb_msgdma_2_txs_m0_agent:av_burstcount
	wire          rsp_mux_001_src_valid;                                                 // rsp_mux_001:src_valid -> pb_msgdma_2_txs_m0_agent:rp_valid
	wire  [140:0] rsp_mux_001_src_data;                                                  // rsp_mux_001:src_data -> pb_msgdma_2_txs_m0_agent:rp_data
	wire          rsp_mux_001_src_ready;                                                 // pb_msgdma_2_txs_m0_agent:rp_ready -> rsp_mux_001:src_ready
	wire    [1:0] rsp_mux_001_src_channel;                                               // rsp_mux_001:src_channel -> pb_msgdma_2_txs_m0_agent:rp_channel
	wire          rsp_mux_001_src_startofpacket;                                         // rsp_mux_001:src_startofpacket -> pb_msgdma_2_txs_m0_agent:rp_startofpacket
	wire          rsp_mux_001_src_endofpacket;                                           // rsp_mux_001:src_endofpacket -> pb_msgdma_2_txs_m0_agent:rp_endofpacket
	wire   [63:0] pcie_hip_avmm_txs_agent_m0_readdata;                                   // pcie_hip_avmm_Txs_translator:uav_readdata -> pcie_hip_avmm_Txs_agent:m0_readdata
	wire          pcie_hip_avmm_txs_agent_m0_waitrequest;                                // pcie_hip_avmm_Txs_translator:uav_waitrequest -> pcie_hip_avmm_Txs_agent:m0_waitrequest
	wire          pcie_hip_avmm_txs_agent_m0_debugaccess;                                // pcie_hip_avmm_Txs_agent:m0_debugaccess -> pcie_hip_avmm_Txs_translator:uav_debugaccess
	wire   [27:0] pcie_hip_avmm_txs_agent_m0_address;                                    // pcie_hip_avmm_Txs_agent:m0_address -> pcie_hip_avmm_Txs_translator:uav_address
	wire    [7:0] pcie_hip_avmm_txs_agent_m0_byteenable;                                 // pcie_hip_avmm_Txs_agent:m0_byteenable -> pcie_hip_avmm_Txs_translator:uav_byteenable
	wire          pcie_hip_avmm_txs_agent_m0_read;                                       // pcie_hip_avmm_Txs_agent:m0_read -> pcie_hip_avmm_Txs_translator:uav_read
	wire          pcie_hip_avmm_txs_agent_m0_readdatavalid;                              // pcie_hip_avmm_Txs_translator:uav_readdatavalid -> pcie_hip_avmm_Txs_agent:m0_readdatavalid
	wire          pcie_hip_avmm_txs_agent_m0_lock;                                       // pcie_hip_avmm_Txs_agent:m0_lock -> pcie_hip_avmm_Txs_translator:uav_lock
	wire   [63:0] pcie_hip_avmm_txs_agent_m0_writedata;                                  // pcie_hip_avmm_Txs_agent:m0_writedata -> pcie_hip_avmm_Txs_translator:uav_writedata
	wire          pcie_hip_avmm_txs_agent_m0_write;                                      // pcie_hip_avmm_Txs_agent:m0_write -> pcie_hip_avmm_Txs_translator:uav_write
	wire    [9:0] pcie_hip_avmm_txs_agent_m0_burstcount;                                 // pcie_hip_avmm_Txs_agent:m0_burstcount -> pcie_hip_avmm_Txs_translator:uav_burstcount
	wire          pcie_hip_avmm_txs_agent_rf_source_valid;                               // pcie_hip_avmm_Txs_agent:rf_source_valid -> pcie_hip_avmm_Txs_agent_rsp_fifo:in_valid
	wire  [141:0] pcie_hip_avmm_txs_agent_rf_source_data;                                // pcie_hip_avmm_Txs_agent:rf_source_data -> pcie_hip_avmm_Txs_agent_rsp_fifo:in_data
	wire          pcie_hip_avmm_txs_agent_rf_source_ready;                               // pcie_hip_avmm_Txs_agent_rsp_fifo:in_ready -> pcie_hip_avmm_Txs_agent:rf_source_ready
	wire          pcie_hip_avmm_txs_agent_rf_source_startofpacket;                       // pcie_hip_avmm_Txs_agent:rf_source_startofpacket -> pcie_hip_avmm_Txs_agent_rsp_fifo:in_startofpacket
	wire          pcie_hip_avmm_txs_agent_rf_source_endofpacket;                         // pcie_hip_avmm_Txs_agent:rf_source_endofpacket -> pcie_hip_avmm_Txs_agent_rsp_fifo:in_endofpacket
	wire          pcie_hip_avmm_txs_agent_rsp_fifo_out_valid;                            // pcie_hip_avmm_Txs_agent_rsp_fifo:out_valid -> pcie_hip_avmm_Txs_agent:rf_sink_valid
	wire  [141:0] pcie_hip_avmm_txs_agent_rsp_fifo_out_data;                             // pcie_hip_avmm_Txs_agent_rsp_fifo:out_data -> pcie_hip_avmm_Txs_agent:rf_sink_data
	wire          pcie_hip_avmm_txs_agent_rsp_fifo_out_ready;                            // pcie_hip_avmm_Txs_agent:rf_sink_ready -> pcie_hip_avmm_Txs_agent_rsp_fifo:out_ready
	wire          pcie_hip_avmm_txs_agent_rsp_fifo_out_startofpacket;                    // pcie_hip_avmm_Txs_agent_rsp_fifo:out_startofpacket -> pcie_hip_avmm_Txs_agent:rf_sink_startofpacket
	wire          pcie_hip_avmm_txs_agent_rsp_fifo_out_endofpacket;                      // pcie_hip_avmm_Txs_agent_rsp_fifo:out_endofpacket -> pcie_hip_avmm_Txs_agent:rf_sink_endofpacket
	wire          pcie_hip_avmm_txs_agent_rdata_fifo_src_valid;                          // pcie_hip_avmm_Txs_agent:rdata_fifo_src_valid -> pcie_hip_avmm_Txs_agent_rdata_fifo:in_valid
	wire   [65:0] pcie_hip_avmm_txs_agent_rdata_fifo_src_data;                           // pcie_hip_avmm_Txs_agent:rdata_fifo_src_data -> pcie_hip_avmm_Txs_agent_rdata_fifo:in_data
	wire          pcie_hip_avmm_txs_agent_rdata_fifo_src_ready;                          // pcie_hip_avmm_Txs_agent_rdata_fifo:in_ready -> pcie_hip_avmm_Txs_agent:rdata_fifo_src_ready
	wire          ccb_h2f_m0_agent_cp_valid;                                             // ccb_h2f_m0_agent:cp_valid -> router:sink_valid
	wire  [140:0] ccb_h2f_m0_agent_cp_data;                                              // ccb_h2f_m0_agent:cp_data -> router:sink_data
	wire          ccb_h2f_m0_agent_cp_ready;                                             // router:sink_ready -> ccb_h2f_m0_agent:cp_ready
	wire          ccb_h2f_m0_agent_cp_startofpacket;                                     // ccb_h2f_m0_agent:cp_startofpacket -> router:sink_startofpacket
	wire          ccb_h2f_m0_agent_cp_endofpacket;                                       // ccb_h2f_m0_agent:cp_endofpacket -> router:sink_endofpacket
	wire          router_src_valid;                                                      // router:src_valid -> cmd_demux:sink_valid
	wire  [140:0] router_src_data;                                                       // router:src_data -> cmd_demux:sink_data
	wire          router_src_ready;                                                      // cmd_demux:sink_ready -> router:src_ready
	wire    [1:0] router_src_channel;                                                    // router:src_channel -> cmd_demux:sink_channel
	wire          router_src_startofpacket;                                              // router:src_startofpacket -> cmd_demux:sink_startofpacket
	wire          router_src_endofpacket;                                                // router:src_endofpacket -> cmd_demux:sink_endofpacket
	wire          pb_msgdma_2_txs_m0_agent_cp_valid;                                     // pb_msgdma_2_txs_m0_agent:cp_valid -> router_001:sink_valid
	wire  [140:0] pb_msgdma_2_txs_m0_agent_cp_data;                                      // pb_msgdma_2_txs_m0_agent:cp_data -> router_001:sink_data
	wire          pb_msgdma_2_txs_m0_agent_cp_ready;                                     // router_001:sink_ready -> pb_msgdma_2_txs_m0_agent:cp_ready
	wire          pb_msgdma_2_txs_m0_agent_cp_startofpacket;                             // pb_msgdma_2_txs_m0_agent:cp_startofpacket -> router_001:sink_startofpacket
	wire          pb_msgdma_2_txs_m0_agent_cp_endofpacket;                               // pb_msgdma_2_txs_m0_agent:cp_endofpacket -> router_001:sink_endofpacket
	wire          router_001_src_valid;                                                  // router_001:src_valid -> cmd_demux_001:sink_valid
	wire  [140:0] router_001_src_data;                                                   // router_001:src_data -> cmd_demux_001:sink_data
	wire          router_001_src_ready;                                                  // cmd_demux_001:sink_ready -> router_001:src_ready
	wire    [1:0] router_001_src_channel;                                                // router_001:src_channel -> cmd_demux_001:sink_channel
	wire          router_001_src_startofpacket;                                          // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
	wire          router_001_src_endofpacket;                                            // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
	wire          router_002_src_valid;                                                  // router_002:src_valid -> rsp_demux:sink_valid
	wire  [140:0] router_002_src_data;                                                   // router_002:src_data -> rsp_demux:sink_data
	wire          router_002_src_ready;                                                  // rsp_demux:sink_ready -> router_002:src_ready
	wire    [1:0] router_002_src_channel;                                                // router_002:src_channel -> rsp_demux:sink_channel
	wire          router_002_src_startofpacket;                                          // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_002_src_endofpacket;                                            // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          cmd_demux_src0_valid;                                                  // cmd_demux:src0_valid -> async_fifo:in_valid
	wire  [140:0] cmd_demux_src0_data;                                                   // cmd_demux:src0_data -> async_fifo:in_data
	wire          cmd_demux_src0_ready;                                                  // async_fifo:in_ready -> cmd_demux:src0_ready
	wire    [1:0] cmd_demux_src0_channel;                                                // cmd_demux:src0_channel -> async_fifo:in_channel
	wire          cmd_demux_src0_startofpacket;                                          // cmd_demux:src0_startofpacket -> async_fifo:in_startofpacket
	wire          cmd_demux_src0_endofpacket;                                            // cmd_demux:src0_endofpacket -> async_fifo:in_endofpacket
	wire          async_fifo_out_valid;                                                  // async_fifo:out_valid -> cmd_mux:sink0_valid
	wire  [140:0] async_fifo_out_data;                                                   // async_fifo:out_data -> cmd_mux:sink0_data
	wire          async_fifo_out_ready;                                                  // cmd_mux:sink0_ready -> async_fifo:out_ready
	wire    [1:0] async_fifo_out_channel;                                                // async_fifo:out_channel -> cmd_mux:sink0_channel
	wire          async_fifo_out_startofpacket;                                          // async_fifo:out_startofpacket -> cmd_mux:sink0_startofpacket
	wire          async_fifo_out_endofpacket;                                            // async_fifo:out_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_001_src0_valid;                                              // cmd_demux_001:src0_valid -> async_fifo_001:in_valid
	wire  [140:0] cmd_demux_001_src0_data;                                               // cmd_demux_001:src0_data -> async_fifo_001:in_data
	wire          cmd_demux_001_src0_ready;                                              // async_fifo_001:in_ready -> cmd_demux_001:src0_ready
	wire    [1:0] cmd_demux_001_src0_channel;                                            // cmd_demux_001:src0_channel -> async_fifo_001:in_channel
	wire          cmd_demux_001_src0_startofpacket;                                      // cmd_demux_001:src0_startofpacket -> async_fifo_001:in_startofpacket
	wire          cmd_demux_001_src0_endofpacket;                                        // cmd_demux_001:src0_endofpacket -> async_fifo_001:in_endofpacket
	wire          async_fifo_001_out_valid;                                              // async_fifo_001:out_valid -> cmd_mux:sink1_valid
	wire  [140:0] async_fifo_001_out_data;                                               // async_fifo_001:out_data -> cmd_mux:sink1_data
	wire          async_fifo_001_out_ready;                                              // cmd_mux:sink1_ready -> async_fifo_001:out_ready
	wire    [1:0] async_fifo_001_out_channel;                                            // async_fifo_001:out_channel -> cmd_mux:sink1_channel
	wire          async_fifo_001_out_startofpacket;                                      // async_fifo_001:out_startofpacket -> cmd_mux:sink1_startofpacket
	wire          async_fifo_001_out_endofpacket;                                        // async_fifo_001:out_endofpacket -> cmd_mux:sink1_endofpacket
	wire          rsp_demux_src0_valid;                                                  // rsp_demux:src0_valid -> async_fifo_002:in_valid
	wire  [140:0] rsp_demux_src0_data;                                                   // rsp_demux:src0_data -> async_fifo_002:in_data
	wire          rsp_demux_src0_ready;                                                  // async_fifo_002:in_ready -> rsp_demux:src0_ready
	wire    [1:0] rsp_demux_src0_channel;                                                // rsp_demux:src0_channel -> async_fifo_002:in_channel
	wire          rsp_demux_src0_startofpacket;                                          // rsp_demux:src0_startofpacket -> async_fifo_002:in_startofpacket
	wire          rsp_demux_src0_endofpacket;                                            // rsp_demux:src0_endofpacket -> async_fifo_002:in_endofpacket
	wire          async_fifo_002_out_valid;                                              // async_fifo_002:out_valid -> rsp_mux:sink0_valid
	wire  [140:0] async_fifo_002_out_data;                                               // async_fifo_002:out_data -> rsp_mux:sink0_data
	wire          async_fifo_002_out_ready;                                              // rsp_mux:sink0_ready -> async_fifo_002:out_ready
	wire    [1:0] async_fifo_002_out_channel;                                            // async_fifo_002:out_channel -> rsp_mux:sink0_channel
	wire          async_fifo_002_out_startofpacket;                                      // async_fifo_002:out_startofpacket -> rsp_mux:sink0_startofpacket
	wire          async_fifo_002_out_endofpacket;                                        // async_fifo_002:out_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_src1_valid;                                                  // rsp_demux:src1_valid -> async_fifo_003:in_valid
	wire  [140:0] rsp_demux_src1_data;                                                   // rsp_demux:src1_data -> async_fifo_003:in_data
	wire          rsp_demux_src1_ready;                                                  // async_fifo_003:in_ready -> rsp_demux:src1_ready
	wire    [1:0] rsp_demux_src1_channel;                                                // rsp_demux:src1_channel -> async_fifo_003:in_channel
	wire          rsp_demux_src1_startofpacket;                                          // rsp_demux:src1_startofpacket -> async_fifo_003:in_startofpacket
	wire          rsp_demux_src1_endofpacket;                                            // rsp_demux:src1_endofpacket -> async_fifo_003:in_endofpacket
	wire          async_fifo_003_out_valid;                                              // async_fifo_003:out_valid -> rsp_mux_001:sink0_valid
	wire  [140:0] async_fifo_003_out_data;                                               // async_fifo_003:out_data -> rsp_mux_001:sink0_data
	wire          async_fifo_003_out_ready;                                              // rsp_mux_001:sink0_ready -> async_fifo_003:out_ready
	wire    [1:0] async_fifo_003_out_channel;                                            // async_fifo_003:out_channel -> rsp_mux_001:sink0_channel
	wire          async_fifo_003_out_startofpacket;                                      // async_fifo_003:out_startofpacket -> rsp_mux_001:sink0_startofpacket
	wire          async_fifo_003_out_endofpacket;                                        // async_fifo_003:out_endofpacket -> rsp_mux_001:sink0_endofpacket
	wire          cmd_mux_src_valid;                                                     // cmd_mux:src_valid -> agent_pipeline:in_valid
	wire  [140:0] cmd_mux_src_data;                                                      // cmd_mux:src_data -> agent_pipeline:in_data
	wire          cmd_mux_src_ready;                                                     // agent_pipeline:in_ready -> cmd_mux:src_ready
	wire    [1:0] cmd_mux_src_channel;                                                   // cmd_mux:src_channel -> agent_pipeline:in_channel
	wire          cmd_mux_src_startofpacket;                                             // cmd_mux:src_startofpacket -> agent_pipeline:in_startofpacket
	wire          cmd_mux_src_endofpacket;                                               // cmd_mux:src_endofpacket -> agent_pipeline:in_endofpacket
	wire          agent_pipeline_source0_valid;                                          // agent_pipeline:out_valid -> pcie_hip_avmm_Txs_agent:cp_valid
	wire  [140:0] agent_pipeline_source0_data;                                           // agent_pipeline:out_data -> pcie_hip_avmm_Txs_agent:cp_data
	wire          agent_pipeline_source0_ready;                                          // pcie_hip_avmm_Txs_agent:cp_ready -> agent_pipeline:out_ready
	wire    [1:0] agent_pipeline_source0_channel;                                        // agent_pipeline:out_channel -> pcie_hip_avmm_Txs_agent:cp_channel
	wire          agent_pipeline_source0_startofpacket;                                  // agent_pipeline:out_startofpacket -> pcie_hip_avmm_Txs_agent:cp_startofpacket
	wire          agent_pipeline_source0_endofpacket;                                    // agent_pipeline:out_endofpacket -> pcie_hip_avmm_Txs_agent:cp_endofpacket
	wire          pcie_hip_avmm_txs_agent_rp_valid;                                      // pcie_hip_avmm_Txs_agent:rp_valid -> agent_pipeline_001:in_valid
	wire  [140:0] pcie_hip_avmm_txs_agent_rp_data;                                       // pcie_hip_avmm_Txs_agent:rp_data -> agent_pipeline_001:in_data
	wire          pcie_hip_avmm_txs_agent_rp_ready;                                      // agent_pipeline_001:in_ready -> pcie_hip_avmm_Txs_agent:rp_ready
	wire          pcie_hip_avmm_txs_agent_rp_startofpacket;                              // pcie_hip_avmm_Txs_agent:rp_startofpacket -> agent_pipeline_001:in_startofpacket
	wire          pcie_hip_avmm_txs_agent_rp_endofpacket;                                // pcie_hip_avmm_Txs_agent:rp_endofpacket -> agent_pipeline_001:in_endofpacket
	wire          agent_pipeline_001_source0_valid;                                      // agent_pipeline_001:out_valid -> router_002:sink_valid
	wire  [140:0] agent_pipeline_001_source0_data;                                       // agent_pipeline_001:out_data -> router_002:sink_data
	wire          agent_pipeline_001_source0_ready;                                      // router_002:sink_ready -> agent_pipeline_001:out_ready
	wire          agent_pipeline_001_source0_startofpacket;                              // agent_pipeline_001:out_startofpacket -> router_002:sink_startofpacket
	wire          agent_pipeline_001_source0_endofpacket;                                // agent_pipeline_001:out_endofpacket -> router_002:sink_endofpacket
	wire          pcie_hip_avmm_txs_agent_rdata_fifo_out_valid;                          // pcie_hip_avmm_Txs_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
	wire   [65:0] pcie_hip_avmm_txs_agent_rdata_fifo_out_data;                           // pcie_hip_avmm_Txs_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
	wire          pcie_hip_avmm_txs_agent_rdata_fifo_out_ready;                          // avalon_st_adapter:in_0_ready -> pcie_hip_avmm_Txs_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_out_0_valid;                                         // avalon_st_adapter:out_0_valid -> pcie_hip_avmm_Txs_agent:rdata_fifo_sink_valid
	wire   [65:0] avalon_st_adapter_out_0_data;                                          // avalon_st_adapter:out_0_data -> pcie_hip_avmm_Txs_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_out_0_ready;                                         // pcie_hip_avmm_Txs_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
	wire    [0:0] avalon_st_adapter_out_0_error;                                         // avalon_st_adapter:out_0_error -> pcie_hip_avmm_Txs_agent:rdata_fifo_sink_error

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (28),
		.AV_DATA_W                   (64),
		.AV_BURSTCOUNT_W             (7),
		.AV_BYTEENABLE_W             (8),
		.UAV_ADDRESS_W               (28),
		.UAV_BURSTCOUNT_W            (10),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (8),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) ccb_h2f_m0_translator (
		.clk                    (custom_reset_synchronizer_0_clock_out_clk),                     //                       clk.clk
		.reset                  (ccb_h2f_m0_reset_reset_bridge_in_reset_reset),                  //                     reset.reset
		.uav_address            (ccb_h2f_m0_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (ccb_h2f_m0_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (ccb_h2f_m0_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (ccb_h2f_m0_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (ccb_h2f_m0_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (ccb_h2f_m0_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (ccb_h2f_m0_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (ccb_h2f_m0_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (ccb_h2f_m0_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (ccb_h2f_m0_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (ccb_h2f_m0_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (ccb_h2f_m0_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (ccb_h2f_m0_waitrequest),                                        //                          .waitrequest
		.av_burstcount          (ccb_h2f_m0_burstcount),                                         //                          .burstcount
		.av_byteenable          (ccb_h2f_m0_byteenable),                                         //                          .byteenable
		.av_read                (ccb_h2f_m0_read),                                               //                          .read
		.av_readdata            (ccb_h2f_m0_readdata),                                           //                          .readdata
		.av_readdatavalid       (ccb_h2f_m0_readdatavalid),                                      //                          .readdatavalid
		.av_write               (ccb_h2f_m0_write),                                              //                          .write
		.av_writedata           (ccb_h2f_m0_writedata),                                          //                          .writedata
		.av_debugaccess         (ccb_h2f_m0_debugaccess),                                        //                          .debugaccess
		.av_beginbursttransfer  (1'b0),                                                          //               (terminated)
		.av_begintransfer       (1'b0),                                                          //               (terminated)
		.av_chipselect          (1'b0),                                                          //               (terminated)
		.av_lock                (1'b0),                                                          //               (terminated)
		.uav_clken              (),                                                              //               (terminated)
		.av_clken               (1'b1),                                                          //               (terminated)
		.uav_response           (2'b00),                                                         //               (terminated)
		.av_response            (),                                                              //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                          //               (terminated)
		.av_writeresponsevalid  ()                                                               //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (28),
		.AV_DATA_W                   (64),
		.AV_BURSTCOUNT_W             (7),
		.AV_BYTEENABLE_W             (8),
		.UAV_ADDRESS_W               (28),
		.UAV_BURSTCOUNT_W            (10),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (8),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) pb_msgdma_2_txs_m0_translator (
		.clk                    (custom_reset_synchronizer_0_clock_out_clk),                             //                       clk.clk
		.reset                  (ccb_h2f_m0_reset_reset_bridge_in_reset_reset),                          //                     reset.reset
		.uav_address            (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (pb_msgdma_2_txs_m0_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (pb_msgdma_2_txs_m0_waitrequest),                                        //                          .waitrequest
		.av_burstcount          (pb_msgdma_2_txs_m0_burstcount),                                         //                          .burstcount
		.av_byteenable          (pb_msgdma_2_txs_m0_byteenable),                                         //                          .byteenable
		.av_read                (pb_msgdma_2_txs_m0_read),                                               //                          .read
		.av_readdata            (pb_msgdma_2_txs_m0_readdata),                                           //                          .readdata
		.av_readdatavalid       (pb_msgdma_2_txs_m0_readdatavalid),                                      //                          .readdatavalid
		.av_write               (pb_msgdma_2_txs_m0_write),                                              //                          .write
		.av_writedata           (pb_msgdma_2_txs_m0_writedata),                                          //                          .writedata
		.av_debugaccess         (pb_msgdma_2_txs_m0_debugaccess),                                        //                          .debugaccess
		.av_beginbursttransfer  (1'b0),                                                                  //               (terminated)
		.av_begintransfer       (1'b0),                                                                  //               (terminated)
		.av_chipselect          (1'b0),                                                                  //               (terminated)
		.av_lock                (1'b0),                                                                  //               (terminated)
		.uav_clken              (),                                                                      //               (terminated)
		.av_clken               (1'b1),                                                                  //               (terminated)
		.uav_response           (2'b00),                                                                 //               (terminated)
		.av_response            (),                                                                      //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                  //               (terminated)
		.av_writeresponsevalid  ()                                                                       //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (28),
		.AV_DATA_W                      (64),
		.UAV_DATA_W                     (64),
		.AV_BURSTCOUNT_W                (7),
		.AV_BYTEENABLE_W                (8),
		.UAV_BYTEENABLE_W               (8),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (10),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (8),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (1),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) pcie_hip_avmm_txs_translator (
		.clk                    (pcie_hip_avmm_coreclkout_clk),                                   //                      clk.clk
		.reset                  (pcie_hip_avmm_Txs_translator_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (pcie_hip_avmm_txs_agent_m0_address),                             // avalon_universal_slave_0.address
		.uav_burstcount         (pcie_hip_avmm_txs_agent_m0_burstcount),                          //                         .burstcount
		.uav_read               (pcie_hip_avmm_txs_agent_m0_read),                                //                         .read
		.uav_write              (pcie_hip_avmm_txs_agent_m0_write),                               //                         .write
		.uav_waitrequest        (pcie_hip_avmm_txs_agent_m0_waitrequest),                         //                         .waitrequest
		.uav_readdatavalid      (pcie_hip_avmm_txs_agent_m0_readdatavalid),                       //                         .readdatavalid
		.uav_byteenable         (pcie_hip_avmm_txs_agent_m0_byteenable),                          //                         .byteenable
		.uav_readdata           (pcie_hip_avmm_txs_agent_m0_readdata),                            //                         .readdata
		.uav_writedata          (pcie_hip_avmm_txs_agent_m0_writedata),                           //                         .writedata
		.uav_lock               (pcie_hip_avmm_txs_agent_m0_lock),                                //                         .lock
		.uav_debugaccess        (pcie_hip_avmm_txs_agent_m0_debugaccess),                         //                         .debugaccess
		.av_address             (pcie_hip_avmm_Txs_address),                                      //      avalon_anti_slave_0.address
		.av_write               (pcie_hip_avmm_Txs_write),                                        //                         .write
		.av_read                (pcie_hip_avmm_Txs_read),                                         //                         .read
		.av_readdata            (pcie_hip_avmm_Txs_readdata),                                     //                         .readdata
		.av_writedata           (pcie_hip_avmm_Txs_writedata),                                    //                         .writedata
		.av_burstcount          (pcie_hip_avmm_Txs_burstcount),                                   //                         .burstcount
		.av_byteenable          (pcie_hip_avmm_Txs_byteenable),                                   //                         .byteenable
		.av_readdatavalid       (pcie_hip_avmm_Txs_readdatavalid),                                //                         .readdatavalid
		.av_waitrequest         (pcie_hip_avmm_Txs_waitrequest),                                  //                         .waitrequest
		.av_chipselect          (pcie_hip_avmm_Txs_chipselect),                                   //                         .chipselect
		.av_begintransfer       (),                                                               //              (terminated)
		.av_beginbursttransfer  (),                                                               //              (terminated)
		.av_writebyteenable     (),                                                               //              (terminated)
		.av_lock                (),                                                               //              (terminated)
		.av_clken               (),                                                               //              (terminated)
		.uav_clken              (1'b0),                                                           //              (terminated)
		.av_debugaccess         (),                                                               //              (terminated)
		.av_outputenable        (),                                                               //              (terminated)
		.uav_response           (),                                                               //              (terminated)
		.av_response            (2'b00),                                                          //              (terminated)
		.uav_writeresponsevalid (),                                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                            //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (140),
		.PKT_ORI_BURST_SIZE_L      (138),
		.PKT_RESPONSE_STATUS_H     (137),
		.PKT_RESPONSE_STATUS_L     (136),
		.PKT_QOS_H                 (125),
		.PKT_QOS_L                 (125),
		.PKT_DATA_SIDEBAND_H       (123),
		.PKT_DATA_SIDEBAND_L       (123),
		.PKT_ADDR_SIDEBAND_H       (122),
		.PKT_ADDR_SIDEBAND_L       (122),
		.PKT_BURST_TYPE_H          (121),
		.PKT_BURST_TYPE_L          (120),
		.PKT_CACHE_H               (135),
		.PKT_CACHE_L               (132),
		.PKT_THREAD_ID_H           (128),
		.PKT_THREAD_ID_L           (128),
		.PKT_BURST_SIZE_H          (119),
		.PKT_BURST_SIZE_L          (117),
		.PKT_TRANS_EXCLUSIVE       (105),
		.PKT_TRANS_LOCK            (104),
		.PKT_BEGIN_BURST           (124),
		.PKT_PROTECTION_H          (131),
		.PKT_PROTECTION_L          (129),
		.PKT_BURSTWRAP_H           (116),
		.PKT_BURSTWRAP_L           (116),
		.PKT_BYTE_CNT_H            (115),
		.PKT_BYTE_CNT_L            (106),
		.PKT_ADDR_H                (99),
		.PKT_ADDR_L                (72),
		.PKT_TRANS_COMPRESSED_READ (100),
		.PKT_TRANS_POSTED          (101),
		.PKT_TRANS_WRITE           (102),
		.PKT_TRANS_READ            (103),
		.PKT_DATA_H                (63),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_SRC_ID_H              (126),
		.PKT_SRC_ID_L              (126),
		.PKT_DEST_ID_H             (127),
		.PKT_DEST_ID_L             (127),
		.ST_DATA_W                 (141),
		.ST_CHANNEL_W              (2),
		.AV_BURSTCOUNT_W           (10),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) ccb_h2f_m0_agent (
		.clk                   (custom_reset_synchronizer_0_clock_out_clk),                     //       clk.clk
		.reset                 (ccb_h2f_m0_reset_reset_bridge_in_reset_reset),                  // clk_reset.reset
		.av_address            (ccb_h2f_m0_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (ccb_h2f_m0_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (ccb_h2f_m0_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (ccb_h2f_m0_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (ccb_h2f_m0_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (ccb_h2f_m0_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (ccb_h2f_m0_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (ccb_h2f_m0_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (ccb_h2f_m0_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (ccb_h2f_m0_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (ccb_h2f_m0_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (ccb_h2f_m0_agent_cp_valid),                                     //        cp.valid
		.cp_data               (ccb_h2f_m0_agent_cp_data),                                      //          .data
		.cp_startofpacket      (ccb_h2f_m0_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (ccb_h2f_m0_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (ccb_h2f_m0_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_src_valid),                                             //        rp.valid
		.rp_data               (rsp_mux_src_data),                                              //          .data
		.rp_channel            (rsp_mux_src_channel),                                           //          .channel
		.rp_startofpacket      (rsp_mux_src_startofpacket),                                     //          .startofpacket
		.rp_endofpacket        (rsp_mux_src_endofpacket),                                       //          .endofpacket
		.rp_ready              (rsp_mux_src_ready),                                             //          .ready
		.av_response           (),                                                              // (terminated)
		.av_writeresponsevalid ()                                                               // (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (140),
		.PKT_ORI_BURST_SIZE_L      (138),
		.PKT_RESPONSE_STATUS_H     (137),
		.PKT_RESPONSE_STATUS_L     (136),
		.PKT_QOS_H                 (125),
		.PKT_QOS_L                 (125),
		.PKT_DATA_SIDEBAND_H       (123),
		.PKT_DATA_SIDEBAND_L       (123),
		.PKT_ADDR_SIDEBAND_H       (122),
		.PKT_ADDR_SIDEBAND_L       (122),
		.PKT_BURST_TYPE_H          (121),
		.PKT_BURST_TYPE_L          (120),
		.PKT_CACHE_H               (135),
		.PKT_CACHE_L               (132),
		.PKT_THREAD_ID_H           (128),
		.PKT_THREAD_ID_L           (128),
		.PKT_BURST_SIZE_H          (119),
		.PKT_BURST_SIZE_L          (117),
		.PKT_TRANS_EXCLUSIVE       (105),
		.PKT_TRANS_LOCK            (104),
		.PKT_BEGIN_BURST           (124),
		.PKT_PROTECTION_H          (131),
		.PKT_PROTECTION_L          (129),
		.PKT_BURSTWRAP_H           (116),
		.PKT_BURSTWRAP_L           (116),
		.PKT_BYTE_CNT_H            (115),
		.PKT_BYTE_CNT_L            (106),
		.PKT_ADDR_H                (99),
		.PKT_ADDR_L                (72),
		.PKT_TRANS_COMPRESSED_READ (100),
		.PKT_TRANS_POSTED          (101),
		.PKT_TRANS_WRITE           (102),
		.PKT_TRANS_READ            (103),
		.PKT_DATA_H                (63),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_SRC_ID_H              (126),
		.PKT_SRC_ID_L              (126),
		.PKT_DEST_ID_H             (127),
		.PKT_DEST_ID_L             (127),
		.ST_DATA_W                 (141),
		.ST_CHANNEL_W              (2),
		.AV_BURSTCOUNT_W           (10),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (1),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) pb_msgdma_2_txs_m0_agent (
		.clk                   (custom_reset_synchronizer_0_clock_out_clk),                             //       clk.clk
		.reset                 (ccb_h2f_m0_reset_reset_bridge_in_reset_reset),                          // clk_reset.reset
		.av_address            (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (pb_msgdma_2_txs_m0_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (pb_msgdma_2_txs_m0_agent_cp_valid),                                     //        cp.valid
		.cp_data               (pb_msgdma_2_txs_m0_agent_cp_data),                                      //          .data
		.cp_startofpacket      (pb_msgdma_2_txs_m0_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (pb_msgdma_2_txs_m0_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (pb_msgdma_2_txs_m0_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_001_src_valid),                                                 //        rp.valid
		.rp_data               (rsp_mux_001_src_data),                                                  //          .data
		.rp_channel            (rsp_mux_001_src_channel),                                               //          .channel
		.rp_startofpacket      (rsp_mux_001_src_startofpacket),                                         //          .startofpacket
		.rp_endofpacket        (rsp_mux_001_src_endofpacket),                                           //          .endofpacket
		.rp_ready              (rsp_mux_001_src_ready),                                                 //          .ready
		.av_response           (),                                                                      // (terminated)
		.av_writeresponsevalid ()                                                                       // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (140),
		.PKT_ORI_BURST_SIZE_L      (138),
		.PKT_RESPONSE_STATUS_H     (137),
		.PKT_RESPONSE_STATUS_L     (136),
		.PKT_BURST_SIZE_H          (119),
		.PKT_BURST_SIZE_L          (117),
		.PKT_TRANS_LOCK            (104),
		.PKT_BEGIN_BURST           (124),
		.PKT_PROTECTION_H          (131),
		.PKT_PROTECTION_L          (129),
		.PKT_BURSTWRAP_H           (116),
		.PKT_BURSTWRAP_L           (116),
		.PKT_BYTE_CNT_H            (115),
		.PKT_BYTE_CNT_L            (106),
		.PKT_ADDR_H                (99),
		.PKT_ADDR_L                (72),
		.PKT_TRANS_COMPRESSED_READ (100),
		.PKT_TRANS_POSTED          (101),
		.PKT_TRANS_WRITE           (102),
		.PKT_TRANS_READ            (103),
		.PKT_DATA_H                (63),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_SRC_ID_H              (126),
		.PKT_SRC_ID_L              (126),
		.PKT_DEST_ID_H             (127),
		.PKT_DEST_ID_L             (127),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (2),
		.ST_DATA_W                 (141),
		.AVS_BURSTCOUNT_W          (10),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) pcie_hip_avmm_txs_agent (
		.clk                     (pcie_hip_avmm_coreclkout_clk),                                   //             clk.clk
		.reset                   (pcie_hip_avmm_Txs_translator_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (pcie_hip_avmm_txs_agent_m0_address),                             //              m0.address
		.m0_burstcount           (pcie_hip_avmm_txs_agent_m0_burstcount),                          //                .burstcount
		.m0_byteenable           (pcie_hip_avmm_txs_agent_m0_byteenable),                          //                .byteenable
		.m0_debugaccess          (pcie_hip_avmm_txs_agent_m0_debugaccess),                         //                .debugaccess
		.m0_lock                 (pcie_hip_avmm_txs_agent_m0_lock),                                //                .lock
		.m0_readdata             (pcie_hip_avmm_txs_agent_m0_readdata),                            //                .readdata
		.m0_readdatavalid        (pcie_hip_avmm_txs_agent_m0_readdatavalid),                       //                .readdatavalid
		.m0_read                 (pcie_hip_avmm_txs_agent_m0_read),                                //                .read
		.m0_waitrequest          (pcie_hip_avmm_txs_agent_m0_waitrequest),                         //                .waitrequest
		.m0_writedata            (pcie_hip_avmm_txs_agent_m0_writedata),                           //                .writedata
		.m0_write                (pcie_hip_avmm_txs_agent_m0_write),                               //                .write
		.rp_endofpacket          (pcie_hip_avmm_txs_agent_rp_endofpacket),                         //              rp.endofpacket
		.rp_ready                (pcie_hip_avmm_txs_agent_rp_ready),                               //                .ready
		.rp_valid                (pcie_hip_avmm_txs_agent_rp_valid),                               //                .valid
		.rp_data                 (pcie_hip_avmm_txs_agent_rp_data),                                //                .data
		.rp_startofpacket        (pcie_hip_avmm_txs_agent_rp_startofpacket),                       //                .startofpacket
		.cp_ready                (agent_pipeline_source0_ready),                                   //              cp.ready
		.cp_valid                (agent_pipeline_source0_valid),                                   //                .valid
		.cp_data                 (agent_pipeline_source0_data),                                    //                .data
		.cp_startofpacket        (agent_pipeline_source0_startofpacket),                           //                .startofpacket
		.cp_endofpacket          (agent_pipeline_source0_endofpacket),                             //                .endofpacket
		.cp_channel              (agent_pipeline_source0_channel),                                 //                .channel
		.rf_sink_ready           (pcie_hip_avmm_txs_agent_rsp_fifo_out_ready),                     //         rf_sink.ready
		.rf_sink_valid           (pcie_hip_avmm_txs_agent_rsp_fifo_out_valid),                     //                .valid
		.rf_sink_startofpacket   (pcie_hip_avmm_txs_agent_rsp_fifo_out_startofpacket),             //                .startofpacket
		.rf_sink_endofpacket     (pcie_hip_avmm_txs_agent_rsp_fifo_out_endofpacket),               //                .endofpacket
		.rf_sink_data            (pcie_hip_avmm_txs_agent_rsp_fifo_out_data),                      //                .data
		.rf_source_ready         (pcie_hip_avmm_txs_agent_rf_source_ready),                        //       rf_source.ready
		.rf_source_valid         (pcie_hip_avmm_txs_agent_rf_source_valid),                        //                .valid
		.rf_source_startofpacket (pcie_hip_avmm_txs_agent_rf_source_startofpacket),                //                .startofpacket
		.rf_source_endofpacket   (pcie_hip_avmm_txs_agent_rf_source_endofpacket),                  //                .endofpacket
		.rf_source_data          (pcie_hip_avmm_txs_agent_rf_source_data),                         //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                                  // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                                  //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                                   //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                                  //                .error
		.rdata_fifo_src_ready    (pcie_hip_avmm_txs_agent_rdata_fifo_src_ready),                   //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (pcie_hip_avmm_txs_agent_rdata_fifo_src_valid),                   //                .valid
		.rdata_fifo_src_data     (pcie_hip_avmm_txs_agent_rdata_fifo_src_data),                    //                .data
		.m0_response             (2'b00),                                                          //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (142),
		.FIFO_DEPTH          (9),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) pcie_hip_avmm_txs_agent_rsp_fifo (
		.clk               (pcie_hip_avmm_coreclkout_clk),                                   //       clk.clk
		.reset             (pcie_hip_avmm_Txs_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (pcie_hip_avmm_txs_agent_rf_source_data),                         //        in.data
		.in_valid          (pcie_hip_avmm_txs_agent_rf_source_valid),                        //          .valid
		.in_ready          (pcie_hip_avmm_txs_agent_rf_source_ready),                        //          .ready
		.in_startofpacket  (pcie_hip_avmm_txs_agent_rf_source_startofpacket),                //          .startofpacket
		.in_endofpacket    (pcie_hip_avmm_txs_agent_rf_source_endofpacket),                  //          .endofpacket
		.out_data          (pcie_hip_avmm_txs_agent_rsp_fifo_out_data),                      //       out.data
		.out_valid         (pcie_hip_avmm_txs_agent_rsp_fifo_out_valid),                     //          .valid
		.out_ready         (pcie_hip_avmm_txs_agent_rsp_fifo_out_ready),                     //          .ready
		.out_startofpacket (pcie_hip_avmm_txs_agent_rsp_fifo_out_startofpacket),             //          .startofpacket
		.out_endofpacket   (pcie_hip_avmm_txs_agent_rsp_fifo_out_endofpacket),               //          .endofpacket
		.csr_address       (2'b00),                                                          // (terminated)
		.csr_read          (1'b0),                                                           // (terminated)
		.csr_write         (1'b0),                                                           // (terminated)
		.csr_readdata      (),                                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                           // (terminated)
		.almost_full_data  (),                                                               // (terminated)
		.almost_empty_data (),                                                               // (terminated)
		.in_empty          (1'b0),                                                           // (terminated)
		.out_empty         (),                                                               // (terminated)
		.in_error          (1'b0),                                                           // (terminated)
		.out_error         (),                                                               // (terminated)
		.in_channel        (1'b0),                                                           // (terminated)
		.out_channel       ()                                                                // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (66),
		.FIFO_DEPTH          (1024),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (3),
		.USE_MEMORY_BLOCKS   (1),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) pcie_hip_avmm_txs_agent_rdata_fifo (
		.clk               (pcie_hip_avmm_coreclkout_clk),                                   //       clk.clk
		.reset             (pcie_hip_avmm_Txs_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (pcie_hip_avmm_txs_agent_rdata_fifo_src_data),                    //        in.data
		.in_valid          (pcie_hip_avmm_txs_agent_rdata_fifo_src_valid),                   //          .valid
		.in_ready          (pcie_hip_avmm_txs_agent_rdata_fifo_src_ready),                   //          .ready
		.out_data          (pcie_hip_avmm_txs_agent_rdata_fifo_out_data),                    //       out.data
		.out_valid         (pcie_hip_avmm_txs_agent_rdata_fifo_out_valid),                   //          .valid
		.out_ready         (pcie_hip_avmm_txs_agent_rdata_fifo_out_ready),                   //          .ready
		.csr_address       (2'b00),                                                          // (terminated)
		.csr_read          (1'b0),                                                           // (terminated)
		.csr_write         (1'b0),                                                           // (terminated)
		.csr_readdata      (),                                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                           // (terminated)
		.almost_full_data  (),                                                               // (terminated)
		.almost_empty_data (),                                                               // (terminated)
		.in_startofpacket  (1'b0),                                                           // (terminated)
		.in_endofpacket    (1'b0),                                                           // (terminated)
		.out_startofpacket (),                                                               // (terminated)
		.out_endofpacket   (),                                                               // (terminated)
		.in_empty          (1'b0),                                                           // (terminated)
		.out_empty         (),                                                               // (terminated)
		.in_error          (1'b0),                                                           // (terminated)
		.out_error         (),                                                               // (terminated)
		.in_channel        (1'b0),                                                           // (terminated)
		.out_channel       ()                                                                // (terminated)
	);

	soc_system_pcie_0_mm_interconnect_2_router router (
		.sink_ready         (ccb_h2f_m0_agent_cp_ready),                    //      sink.ready
		.sink_valid         (ccb_h2f_m0_agent_cp_valid),                    //          .valid
		.sink_data          (ccb_h2f_m0_agent_cp_data),                     //          .data
		.sink_startofpacket (ccb_h2f_m0_agent_cp_startofpacket),            //          .startofpacket
		.sink_endofpacket   (ccb_h2f_m0_agent_cp_endofpacket),              //          .endofpacket
		.clk                (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset              (ccb_h2f_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_src_ready),                             //       src.ready
		.src_valid          (router_src_valid),                             //          .valid
		.src_data           (router_src_data),                              //          .data
		.src_channel        (router_src_channel),                           //          .channel
		.src_startofpacket  (router_src_startofpacket),                     //          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                        //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_2_router router_001 (
		.sink_ready         (pb_msgdma_2_txs_m0_agent_cp_ready),            //      sink.ready
		.sink_valid         (pb_msgdma_2_txs_m0_agent_cp_valid),            //          .valid
		.sink_data          (pb_msgdma_2_txs_m0_agent_cp_data),             //          .data
		.sink_startofpacket (pb_msgdma_2_txs_m0_agent_cp_startofpacket),    //          .startofpacket
		.sink_endofpacket   (pb_msgdma_2_txs_m0_agent_cp_endofpacket),      //          .endofpacket
		.clk                (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset              (ccb_h2f_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_001_src_ready),                         //       src.ready
		.src_valid          (router_001_src_valid),                         //          .valid
		.src_data           (router_001_src_data),                          //          .data
		.src_channel        (router_001_src_channel),                       //          .channel
		.src_startofpacket  (router_001_src_startofpacket),                 //          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                    //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_2_router_002 router_002 (
		.sink_ready         (agent_pipeline_001_source0_ready),                               //      sink.ready
		.sink_valid         (agent_pipeline_001_source0_valid),                               //          .valid
		.sink_data          (agent_pipeline_001_source0_data),                                //          .data
		.sink_startofpacket (agent_pipeline_001_source0_startofpacket),                       //          .startofpacket
		.sink_endofpacket   (agent_pipeline_001_source0_endofpacket),                         //          .endofpacket
		.clk                (pcie_hip_avmm_coreclkout_clk),                                   //       clk.clk
		.reset              (pcie_hip_avmm_Txs_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_002_src_ready),                                           //       src.ready
		.src_valid          (router_002_src_valid),                                           //          .valid
		.src_data           (router_002_src_data),                                            //          .data
		.src_channel        (router_002_src_channel),                                         //          .channel
		.src_startofpacket  (router_002_src_startofpacket),                                   //          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                                      //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_2_cmd_demux cmd_demux (
		.clk                (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset              (ccb_h2f_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_src_ready),                             //      sink.ready
		.sink_channel       (router_src_channel),                           //          .channel
		.sink_data          (router_src_data),                              //          .data
		.sink_startofpacket (router_src_startofpacket),                     //          .startofpacket
		.sink_endofpacket   (router_src_endofpacket),                       //          .endofpacket
		.sink_valid         (router_src_valid),                             //          .valid
		.src0_ready         (cmd_demux_src0_ready),                         //      src0.ready
		.src0_valid         (cmd_demux_src0_valid),                         //          .valid
		.src0_data          (cmd_demux_src0_data),                          //          .data
		.src0_channel       (cmd_demux_src0_channel),                       //          .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                 //          .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket)                    //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_2_cmd_demux cmd_demux_001 (
		.clk                (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset              (ccb_h2f_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_001_src_ready),                         //      sink.ready
		.sink_channel       (router_001_src_channel),                       //          .channel
		.sink_data          (router_001_src_data),                          //          .data
		.sink_startofpacket (router_001_src_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),                   //          .endofpacket
		.sink_valid         (router_001_src_valid),                         //          .valid
		.src0_ready         (cmd_demux_001_src0_ready),                     //      src0.ready
		.src0_valid         (cmd_demux_001_src0_valid),                     //          .valid
		.src0_data          (cmd_demux_001_src0_data),                      //          .data
		.src0_channel       (cmd_demux_001_src0_channel),                   //          .channel
		.src0_startofpacket (cmd_demux_001_src0_startofpacket),             //          .startofpacket
		.src0_endofpacket   (cmd_demux_001_src0_endofpacket)                //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_2_cmd_mux cmd_mux (
		.clk                 (pcie_hip_avmm_coreclkout_clk),                                   //       clk.clk
		.reset               (pcie_hip_avmm_Txs_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                                              //       src.ready
		.src_valid           (cmd_mux_src_valid),                                              //          .valid
		.src_data            (cmd_mux_src_data),                                               //          .data
		.src_channel         (cmd_mux_src_channel),                                            //          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                                      //          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                                        //          .endofpacket
		.sink0_ready         (async_fifo_out_ready),                                           //     sink0.ready
		.sink0_valid         (async_fifo_out_valid),                                           //          .valid
		.sink0_channel       (async_fifo_out_channel),                                         //          .channel
		.sink0_data          (async_fifo_out_data),                                            //          .data
		.sink0_startofpacket (async_fifo_out_startofpacket),                                   //          .startofpacket
		.sink0_endofpacket   (async_fifo_out_endofpacket),                                     //          .endofpacket
		.sink1_ready         (async_fifo_001_out_ready),                                       //     sink1.ready
		.sink1_valid         (async_fifo_001_out_valid),                                       //          .valid
		.sink1_channel       (async_fifo_001_out_channel),                                     //          .channel
		.sink1_data          (async_fifo_001_out_data),                                        //          .data
		.sink1_startofpacket (async_fifo_001_out_startofpacket),                               //          .startofpacket
		.sink1_endofpacket   (async_fifo_001_out_endofpacket)                                  //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_2_rsp_demux rsp_demux (
		.clk                (pcie_hip_avmm_coreclkout_clk),                                   //       clk.clk
		.reset              (pcie_hip_avmm_Txs_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_002_src_ready),                                           //      sink.ready
		.sink_channel       (router_002_src_channel),                                         //          .channel
		.sink_data          (router_002_src_data),                                            //          .data
		.sink_startofpacket (router_002_src_startofpacket),                                   //          .startofpacket
		.sink_endofpacket   (router_002_src_endofpacket),                                     //          .endofpacket
		.sink_valid         (router_002_src_valid),                                           //          .valid
		.src0_ready         (rsp_demux_src0_ready),                                           //      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                                           //          .valid
		.src0_data          (rsp_demux_src0_data),                                            //          .data
		.src0_channel       (rsp_demux_src0_channel),                                         //          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                                   //          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket),                                     //          .endofpacket
		.src1_ready         (rsp_demux_src1_ready),                                           //      src1.ready
		.src1_valid         (rsp_demux_src1_valid),                                           //          .valid
		.src1_data          (rsp_demux_src1_data),                                            //          .data
		.src1_channel       (rsp_demux_src1_channel),                                         //          .channel
		.src1_startofpacket (rsp_demux_src1_startofpacket),                                   //          .startofpacket
		.src1_endofpacket   (rsp_demux_src1_endofpacket)                                      //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_2_rsp_mux rsp_mux (
		.clk                 (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset               (ccb_h2f_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                            //       src.ready
		.src_valid           (rsp_mux_src_valid),                            //          .valid
		.src_data            (rsp_mux_src_data),                             //          .data
		.src_channel         (rsp_mux_src_channel),                          //          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                    //          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                      //          .endofpacket
		.sink0_ready         (async_fifo_002_out_ready),                     //     sink0.ready
		.sink0_valid         (async_fifo_002_out_valid),                     //          .valid
		.sink0_channel       (async_fifo_002_out_channel),                   //          .channel
		.sink0_data          (async_fifo_002_out_data),                      //          .data
		.sink0_startofpacket (async_fifo_002_out_startofpacket),             //          .startofpacket
		.sink0_endofpacket   (async_fifo_002_out_endofpacket)                //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_2_rsp_mux rsp_mux_001 (
		.clk                 (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset               (ccb_h2f_m0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_001_src_ready),                        //       src.ready
		.src_valid           (rsp_mux_001_src_valid),                        //          .valid
		.src_data            (rsp_mux_001_src_data),                         //          .data
		.src_channel         (rsp_mux_001_src_channel),                      //          .channel
		.src_startofpacket   (rsp_mux_001_src_startofpacket),                //          .startofpacket
		.src_endofpacket     (rsp_mux_001_src_endofpacket),                  //          .endofpacket
		.sink0_ready         (async_fifo_003_out_ready),                     //     sink0.ready
		.sink0_valid         (async_fifo_003_out_valid),                     //          .valid
		.sink0_channel       (async_fifo_003_out_channel),                   //          .channel
		.sink0_data          (async_fifo_003_out_data),                      //          .data
		.sink0_startofpacket (async_fifo_003_out_startofpacket),             //          .startofpacket
		.sink0_endofpacket   (async_fifo_003_out_endofpacket)                //          .endofpacket
	);

	altera_avalon_dc_fifo #(
		.SYMBOLS_PER_BEAT   (1),
		.BITS_PER_SYMBOL    (141),
		.FIFO_DEPTH         (8),
		.CHANNEL_WIDTH      (2),
		.ERROR_WIDTH        (0),
		.USE_PACKETS        (1),
		.USE_IN_FILL_LEVEL  (0),
		.USE_OUT_FILL_LEVEL (0),
		.WR_SYNC_DEPTH      (3),
		.RD_SYNC_DEPTH      (3)
	) async_fifo (
		.in_clk            (custom_reset_synchronizer_0_clock_out_clk),                       //        in_clk.clk
		.in_reset_n        (~ccb_h2f_m0_reset_reset_bridge_in_reset_reset),                   //  in_clk_reset.reset_n
		.out_clk           (pcie_hip_avmm_coreclkout_clk),                                    //       out_clk.clk
		.out_reset_n       (~pcie_hip_avmm_Txs_translator_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset_n
		.in_data           (cmd_demux_src0_data),                                             //            in.data
		.in_valid          (cmd_demux_src0_valid),                                            //              .valid
		.in_ready          (cmd_demux_src0_ready),                                            //              .ready
		.in_startofpacket  (cmd_demux_src0_startofpacket),                                    //              .startofpacket
		.in_endofpacket    (cmd_demux_src0_endofpacket),                                      //              .endofpacket
		.in_channel        (cmd_demux_src0_channel),                                          //              .channel
		.out_data          (async_fifo_out_data),                                             //           out.data
		.out_valid         (async_fifo_out_valid),                                            //              .valid
		.out_ready         (async_fifo_out_ready),                                            //              .ready
		.out_startofpacket (async_fifo_out_startofpacket),                                    //              .startofpacket
		.out_endofpacket   (async_fifo_out_endofpacket),                                      //              .endofpacket
		.out_channel       (async_fifo_out_channel),                                          //              .channel
		.in_csr_address    (1'b0),                                                            //   (terminated)
		.in_csr_read       (1'b0),                                                            //   (terminated)
		.in_csr_write      (1'b0),                                                            //   (terminated)
		.in_csr_readdata   (),                                                                //   (terminated)
		.in_csr_writedata  (32'b00000000000000000000000000000000),                            //   (terminated)
		.out_csr_address   (1'b0),                                                            //   (terminated)
		.out_csr_read      (1'b0),                                                            //   (terminated)
		.out_csr_write     (1'b0),                                                            //   (terminated)
		.out_csr_readdata  (),                                                                //   (terminated)
		.out_csr_writedata (32'b00000000000000000000000000000000),                            //   (terminated)
		.in_empty          (1'b0),                                                            //   (terminated)
		.out_empty         (),                                                                //   (terminated)
		.in_error          (1'b0),                                                            //   (terminated)
		.out_error         (),                                                                //   (terminated)
		.space_avail_data  ()                                                                 //   (terminated)
	);

	altera_avalon_dc_fifo #(
		.SYMBOLS_PER_BEAT   (1),
		.BITS_PER_SYMBOL    (141),
		.FIFO_DEPTH         (8),
		.CHANNEL_WIDTH      (2),
		.ERROR_WIDTH        (0),
		.USE_PACKETS        (1),
		.USE_IN_FILL_LEVEL  (0),
		.USE_OUT_FILL_LEVEL (0),
		.WR_SYNC_DEPTH      (3),
		.RD_SYNC_DEPTH      (3)
	) async_fifo_001 (
		.in_clk            (custom_reset_synchronizer_0_clock_out_clk),                       //        in_clk.clk
		.in_reset_n        (~ccb_h2f_m0_reset_reset_bridge_in_reset_reset),                   //  in_clk_reset.reset_n
		.out_clk           (pcie_hip_avmm_coreclkout_clk),                                    //       out_clk.clk
		.out_reset_n       (~pcie_hip_avmm_Txs_translator_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset_n
		.in_data           (cmd_demux_001_src0_data),                                         //            in.data
		.in_valid          (cmd_demux_001_src0_valid),                                        //              .valid
		.in_ready          (cmd_demux_001_src0_ready),                                        //              .ready
		.in_startofpacket  (cmd_demux_001_src0_startofpacket),                                //              .startofpacket
		.in_endofpacket    (cmd_demux_001_src0_endofpacket),                                  //              .endofpacket
		.in_channel        (cmd_demux_001_src0_channel),                                      //              .channel
		.out_data          (async_fifo_001_out_data),                                         //           out.data
		.out_valid         (async_fifo_001_out_valid),                                        //              .valid
		.out_ready         (async_fifo_001_out_ready),                                        //              .ready
		.out_startofpacket (async_fifo_001_out_startofpacket),                                //              .startofpacket
		.out_endofpacket   (async_fifo_001_out_endofpacket),                                  //              .endofpacket
		.out_channel       (async_fifo_001_out_channel),                                      //              .channel
		.in_csr_address    (1'b0),                                                            //   (terminated)
		.in_csr_read       (1'b0),                                                            //   (terminated)
		.in_csr_write      (1'b0),                                                            //   (terminated)
		.in_csr_readdata   (),                                                                //   (terminated)
		.in_csr_writedata  (32'b00000000000000000000000000000000),                            //   (terminated)
		.out_csr_address   (1'b0),                                                            //   (terminated)
		.out_csr_read      (1'b0),                                                            //   (terminated)
		.out_csr_write     (1'b0),                                                            //   (terminated)
		.out_csr_readdata  (),                                                                //   (terminated)
		.out_csr_writedata (32'b00000000000000000000000000000000),                            //   (terminated)
		.in_empty          (1'b0),                                                            //   (terminated)
		.out_empty         (),                                                                //   (terminated)
		.in_error          (1'b0),                                                            //   (terminated)
		.out_error         (),                                                                //   (terminated)
		.space_avail_data  ()                                                                 //   (terminated)
	);

	altera_avalon_dc_fifo #(
		.SYMBOLS_PER_BEAT   (1),
		.BITS_PER_SYMBOL    (141),
		.FIFO_DEPTH         (8),
		.CHANNEL_WIDTH      (2),
		.ERROR_WIDTH        (0),
		.USE_PACKETS        (1),
		.USE_IN_FILL_LEVEL  (0),
		.USE_OUT_FILL_LEVEL (0),
		.WR_SYNC_DEPTH      (3),
		.RD_SYNC_DEPTH      (3)
	) async_fifo_002 (
		.in_clk            (pcie_hip_avmm_coreclkout_clk),                                    //        in_clk.clk
		.in_reset_n        (~pcie_hip_avmm_Txs_translator_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset_n
		.out_clk           (custom_reset_synchronizer_0_clock_out_clk),                       //       out_clk.clk
		.out_reset_n       (~ccb_h2f_m0_reset_reset_bridge_in_reset_reset),                   // out_clk_reset.reset_n
		.in_data           (rsp_demux_src0_data),                                             //            in.data
		.in_valid          (rsp_demux_src0_valid),                                            //              .valid
		.in_ready          (rsp_demux_src0_ready),                                            //              .ready
		.in_startofpacket  (rsp_demux_src0_startofpacket),                                    //              .startofpacket
		.in_endofpacket    (rsp_demux_src0_endofpacket),                                      //              .endofpacket
		.in_channel        (rsp_demux_src0_channel),                                          //              .channel
		.out_data          (async_fifo_002_out_data),                                         //           out.data
		.out_valid         (async_fifo_002_out_valid),                                        //              .valid
		.out_ready         (async_fifo_002_out_ready),                                        //              .ready
		.out_startofpacket (async_fifo_002_out_startofpacket),                                //              .startofpacket
		.out_endofpacket   (async_fifo_002_out_endofpacket),                                  //              .endofpacket
		.out_channel       (async_fifo_002_out_channel),                                      //              .channel
		.in_csr_address    (1'b0),                                                            //   (terminated)
		.in_csr_read       (1'b0),                                                            //   (terminated)
		.in_csr_write      (1'b0),                                                            //   (terminated)
		.in_csr_readdata   (),                                                                //   (terminated)
		.in_csr_writedata  (32'b00000000000000000000000000000000),                            //   (terminated)
		.out_csr_address   (1'b0),                                                            //   (terminated)
		.out_csr_read      (1'b0),                                                            //   (terminated)
		.out_csr_write     (1'b0),                                                            //   (terminated)
		.out_csr_readdata  (),                                                                //   (terminated)
		.out_csr_writedata (32'b00000000000000000000000000000000),                            //   (terminated)
		.in_empty          (1'b0),                                                            //   (terminated)
		.out_empty         (),                                                                //   (terminated)
		.in_error          (1'b0),                                                            //   (terminated)
		.out_error         (),                                                                //   (terminated)
		.space_avail_data  ()                                                                 //   (terminated)
	);

	altera_avalon_dc_fifo #(
		.SYMBOLS_PER_BEAT   (1),
		.BITS_PER_SYMBOL    (141),
		.FIFO_DEPTH         (8),
		.CHANNEL_WIDTH      (2),
		.ERROR_WIDTH        (0),
		.USE_PACKETS        (1),
		.USE_IN_FILL_LEVEL  (0),
		.USE_OUT_FILL_LEVEL (0),
		.WR_SYNC_DEPTH      (3),
		.RD_SYNC_DEPTH      (3)
	) async_fifo_003 (
		.in_clk            (pcie_hip_avmm_coreclkout_clk),                                    //        in_clk.clk
		.in_reset_n        (~pcie_hip_avmm_Txs_translator_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset_n
		.out_clk           (custom_reset_synchronizer_0_clock_out_clk),                       //       out_clk.clk
		.out_reset_n       (~ccb_h2f_m0_reset_reset_bridge_in_reset_reset),                   // out_clk_reset.reset_n
		.in_data           (rsp_demux_src1_data),                                             //            in.data
		.in_valid          (rsp_demux_src1_valid),                                            //              .valid
		.in_ready          (rsp_demux_src1_ready),                                            //              .ready
		.in_startofpacket  (rsp_demux_src1_startofpacket),                                    //              .startofpacket
		.in_endofpacket    (rsp_demux_src1_endofpacket),                                      //              .endofpacket
		.in_channel        (rsp_demux_src1_channel),                                          //              .channel
		.out_data          (async_fifo_003_out_data),                                         //           out.data
		.out_valid         (async_fifo_003_out_valid),                                        //              .valid
		.out_ready         (async_fifo_003_out_ready),                                        //              .ready
		.out_startofpacket (async_fifo_003_out_startofpacket),                                //              .startofpacket
		.out_endofpacket   (async_fifo_003_out_endofpacket),                                  //              .endofpacket
		.out_channel       (async_fifo_003_out_channel),                                      //              .channel
		.in_csr_address    (1'b0),                                                            //   (terminated)
		.in_csr_read       (1'b0),                                                            //   (terminated)
		.in_csr_write      (1'b0),                                                            //   (terminated)
		.in_csr_readdata   (),                                                                //   (terminated)
		.in_csr_writedata  (32'b00000000000000000000000000000000),                            //   (terminated)
		.out_csr_address   (1'b0),                                                            //   (terminated)
		.out_csr_read      (1'b0),                                                            //   (terminated)
		.out_csr_write     (1'b0),                                                            //   (terminated)
		.out_csr_readdata  (),                                                                //   (terminated)
		.out_csr_writedata (32'b00000000000000000000000000000000),                            //   (terminated)
		.in_empty          (1'b0),                                                            //   (terminated)
		.out_empty         (),                                                                //   (terminated)
		.in_error          (1'b0),                                                            //   (terminated)
		.out_error         (),                                                                //   (terminated)
		.space_avail_data  ()                                                                 //   (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (141),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (2),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline (
		.clk               (pcie_hip_avmm_coreclkout_clk),                                   //       cr0.clk
		.reset             (pcie_hip_avmm_Txs_translator_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (cmd_mux_src_ready),                                              //     sink0.ready
		.in_valid          (cmd_mux_src_valid),                                              //          .valid
		.in_startofpacket  (cmd_mux_src_startofpacket),                                      //          .startofpacket
		.in_endofpacket    (cmd_mux_src_endofpacket),                                        //          .endofpacket
		.in_data           (cmd_mux_src_data),                                               //          .data
		.in_channel        (cmd_mux_src_channel),                                            //          .channel
		.out_ready         (agent_pipeline_source0_ready),                                   //   source0.ready
		.out_valid         (agent_pipeline_source0_valid),                                   //          .valid
		.out_startofpacket (agent_pipeline_source0_startofpacket),                           //          .startofpacket
		.out_endofpacket   (agent_pipeline_source0_endofpacket),                             //          .endofpacket
		.out_data          (agent_pipeline_source0_data),                                    //          .data
		.out_channel       (agent_pipeline_source0_channel),                                 //          .channel
		.in_empty          (1'b0),                                                           // (terminated)
		.out_empty         (),                                                               // (terminated)
		.out_error         (),                                                               // (terminated)
		.in_error          (1'b0)                                                            // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (141),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_001 (
		.clk               (pcie_hip_avmm_coreclkout_clk),                                   //       cr0.clk
		.reset             (pcie_hip_avmm_Txs_translator_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (pcie_hip_avmm_txs_agent_rp_ready),                               //     sink0.ready
		.in_valid          (pcie_hip_avmm_txs_agent_rp_valid),                               //          .valid
		.in_startofpacket  (pcie_hip_avmm_txs_agent_rp_startofpacket),                       //          .startofpacket
		.in_endofpacket    (pcie_hip_avmm_txs_agent_rp_endofpacket),                         //          .endofpacket
		.in_data           (pcie_hip_avmm_txs_agent_rp_data),                                //          .data
		.out_ready         (agent_pipeline_001_source0_ready),                               //   source0.ready
		.out_valid         (agent_pipeline_001_source0_valid),                               //          .valid
		.out_startofpacket (agent_pipeline_001_source0_startofpacket),                       //          .startofpacket
		.out_endofpacket   (agent_pipeline_001_source0_endofpacket),                         //          .endofpacket
		.out_data          (agent_pipeline_001_source0_data),                                //          .data
		.in_empty          (1'b0),                                                           // (terminated)
		.out_empty         (),                                                               // (terminated)
		.out_error         (),                                                               // (terminated)
		.in_error          (1'b0),                                                           // (terminated)
		.out_channel       (),                                                               // (terminated)
		.in_channel        (1'b0)                                                            // (terminated)
	);

	soc_system_mm_interconnect_1_avalon_st_adapter #(
		.inBitsPerSymbol (66),
		.inUsePackets    (0),
		.inDataWidth     (66),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (66),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter (
		.in_clk_0_clk   (pcie_hip_avmm_coreclkout_clk),                                   // in_clk_0.clk
		.in_rst_0_reset (pcie_hip_avmm_Txs_translator_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (pcie_hip_avmm_txs_agent_rdata_fifo_out_data),                    //     in_0.data
		.in_0_valid     (pcie_hip_avmm_txs_agent_rdata_fifo_out_valid),                   //         .valid
		.in_0_ready     (pcie_hip_avmm_txs_agent_rdata_fifo_out_ready),                   //         .ready
		.out_0_data     (avalon_st_adapter_out_0_data),                                   //    out_0.data
		.out_0_valid    (avalon_st_adapter_out_0_valid),                                  //         .valid
		.out_0_ready    (avalon_st_adapter_out_0_ready),                                  //         .ready
		.out_0_error    (avalon_st_adapter_out_0_error)                                   //         .error
	);

endmodule
