// subsys_vid.v

// Generated using ACDS version 18.1 625

`timescale 1 ps / 1 ps
module subsys_vid (
		input  wire [3:0]   control_address,         //   control.address
		input  wire [3:0]   control_byteenable,      //          .byteenable
		input  wire         control_write,           //          .write
		input  wire [31:0]  control_writedata,       //          .writedata
		input  wire         control_read,            //          .read
		output wire [31:0]  control_readdata,        //          .readdata
		output wire         control_readdatavalid,   //          .readdatavalid
		output wire         control_waitrequest,     //          .waitrequest
		output wire         interrupt_irq,           // interrupt.irq
		output wire [31:0]  master_rd_address,       // master_rd.address
		output wire [4:0]   master_rd_burstcount,    //          .burstcount
		input  wire         master_rd_waitrequest,   //          .waitrequest
		output wire         master_rd_read,          //          .read
		input  wire [255:0] master_rd_readdata,      //          .readdata
		input  wire         master_rd_readdatavalid, //          .readdatavalid
		input  wire         vid_out_vid_clk,         //   vid_out.vid_clk
		output wire [31:0]  vid_out_vid_data,        //          .vid_data
		output wire         vid_out_underflow,       //          .underflow
		output wire         vid_out_vid_datavalid,   //          .vid_datavalid
		output wire         vid_out_vid_v_sync,      //          .vid_v_sync
		output wire         vid_out_vid_h_sync,      //          .vid_h_sync
		output wire         vid_out_vid_f,           //          .vid_f
		output wire         vid_out_vid_h,           //          .vid_h
		output wire         vid_out_vid_v,           //          .vid_v
		input  wire         vip_clk_clk,             //   vip_clk.clk
		input  wire         vip_reset_reset_n        // vip_reset.reset_n
	);

	wire         vfr_dout_valid;                 // vfr:dout_valid -> cvo:din_valid
	wire  [31:0] vfr_dout_data;                  // vfr:dout_data -> cvo:din_data
	wire         vfr_dout_ready;                 // cvo:din_ready -> vfr:dout_ready
	wire         vfr_dout_startofpacket;         // vfr:dout_startofpacket -> cvo:din_startofpacket
	wire         vfr_dout_endofpacket;           // vfr:dout_endofpacket -> cvo:din_endofpacket
	wire         rst_controller_reset_out_reset; // rst_controller:reset_out -> [cvo:main_reset_reset, vfr:main_reset]

	subsys_vid_cvo #(
		.BPS                           (8),
		.NUMBER_OF_COLOUR_PLANES       (4),
		.COLOUR_PLANES_ARE_IN_PARALLEL (1),
		.INTERLACED                    (0),
		.H_ACTIVE_PIXELS               (1280),
		.V_ACTIVE_LINES                (720),
		.ACCEPT_COLOURS_IN_SEQ         (0),
		.FIFO_DEPTH                    (1280),
		.CLOCKS_ARE_SAME               (0),
		.USE_CONTROL                   (0),
		.NO_OF_MODES                   (1),
		.THRESHOLD                     (1279),
		.STD_WIDTH                     (1),
		.GENERATE_SYNC                 (0),
		.ACCEPT_SYNC                   (0),
		.COUNT_STEP_IS_PIP_VALUE       (0),
		.LOW_LATENCY                   (0),
		.USE_EMBEDDED_SYNCS            (0),
		.AP_LINE                       (0),
		.V_BLANK                       (0),
		.H_BLANK                       (0),
		.H_SYNC_LENGTH                 (46),
		.H_FRONT_PORCH                 (110),
		.H_BACK_PORCH                  (220),
		.V_SYNC_LENGTH                 (5),
		.V_FRONT_PORCH                 (5),
		.V_BACK_PORCH                  (20),
		.F_RISING_EDGE                 (0),
		.F_FALLING_EDGE                (0),
		.FIELD0_V_RISING_EDGE          (0),
		.FIELD0_V_BLANK                (0),
		.FIELD0_V_SYNC_LENGTH          (0),
		.FIELD0_V_FRONT_PORCH          (0),
		.FIELD0_V_BACK_PORCH           (0),
		.ANC_LINE                      (0),
		.FIELD0_ANC_LINE               (0),
		.PIXELS_IN_PARALLEL            (1),
		.SRC_WIDTH                     (8),
		.DST_WIDTH                     (8),
		.CONTEXT_WIDTH                 (8),
		.TASK_WIDTH                    (8)
	) cvo (
		.clocked_video_vid_clk       (vid_out_vid_clk),                // clocked_video.vid_clk
		.clocked_video_vid_data      (vid_out_vid_data),               //              .vid_data
		.clocked_video_underflow     (vid_out_underflow),              //              .underflow
		.clocked_video_vid_datavalid (vid_out_vid_datavalid),          //              .vid_datavalid
		.clocked_video_vid_v_sync    (vid_out_vid_v_sync),             //              .vid_v_sync
		.clocked_video_vid_h_sync    (vid_out_vid_h_sync),             //              .vid_h_sync
		.clocked_video_vid_f         (vid_out_vid_f),                  //              .vid_f
		.clocked_video_vid_h         (vid_out_vid_h),                  //              .vid_h
		.clocked_video_vid_v         (vid_out_vid_v),                  //              .vid_v
		.main_clock_clk              (vip_clk_clk),                    //    main_clock.clk
		.main_reset_reset            (rst_controller_reset_out_reset), //    main_reset.reset
		.din_data                    (vfr_dout_data),                  //           din.data
		.din_valid                   (vfr_dout_valid),                 //              .valid
		.din_startofpacket           (vfr_dout_startofpacket),         //              .startofpacket
		.din_endofpacket             (vfr_dout_endofpacket),           //              .endofpacket
		.din_ready                   (vfr_dout_ready)                  //              .ready
	);

	subsys_vid_vfr #(
		.BITS_PER_SYMBOL              (8),
		.NUMBER_OF_COLOR_PLANES       (4),
		.COLOR_PLANES_ARE_IN_PARALLEL (1),
		.PIXELS_IN_PARALLEL           (1),
		.READY_LATENCY                (1),
		.MAX_WIDTH                    (1280),
		.MAX_HEIGHT                   (720),
		.CLOCKS_ARE_SEPARATE          (0),
		.MEM_PORT_WIDTH               (256),
		.MEM_BASE_ADDR                (0),
		.BURST_ALIGNMENT              (1),
		.WRITE_FIFO_DEPTH             (32),
		.WRITE_BURST_TARGET           (16),
		.READ_FIFO_DEPTH              (32),
		.READ_BURST_TARGET            (16),
		.WRITER_RUNTIME_CONTROL       (0),
		.READER_RUNTIME_CONTROL       (1),
		.IS_FRAME_WRITER              (0),
		.IS_FRAME_READER              (1),
		.DROP_FRAMES                  (1),
		.REPEAT_FRAMES                (1),
		.DROP_REPEAT_USER             (0),
		.INTERLACED_SUPPORT           (0),
		.CONTROLLED_DROP_REPEAT       (0),
		.DROP_INVALID_FIELDS          (1),
		.MULTI_FRAME_DELAY            (1),
		.IS_SYNC_MASTER               (0),
		.IS_SYNC_SLAVE                (0),
		.LINE_BASED_BUFFERING         (0),
		.PRIORITIZE_FMAX              (0),
		.USER_PACKETS_MAX_STORAGE     (0),
		.MAX_SYMBOLS_PER_PACKET       (10),
		.NUM_BUFFERS                  (3)
	) vfr (
		.main_clock                  (vip_clk_clk),                    //        main_clock.clk
		.main_reset                  (rst_controller_reset_out_reset), //        main_reset.reset
		.dout_data                   (vfr_dout_data),                  //              dout.data
		.dout_valid                  (vfr_dout_valid),                 //                  .valid
		.dout_startofpacket          (vfr_dout_startofpacket),         //                  .startofpacket
		.dout_endofpacket            (vfr_dout_endofpacket),           //                  .endofpacket
		.dout_ready                  (vfr_dout_ready),                 //                  .ready
		.mem_master_rd_address       (master_rd_address),              //     mem_master_rd.address
		.mem_master_rd_burstcount    (master_rd_burstcount),           //                  .burstcount
		.mem_master_rd_waitrequest   (master_rd_waitrequest),          //                  .waitrequest
		.mem_master_rd_read          (master_rd_read),                 //                  .read
		.mem_master_rd_readdata      (master_rd_readdata),             //                  .readdata
		.mem_master_rd_readdatavalid (master_rd_readdatavalid),        //                  .readdatavalid
		.control_interrupt_irq       (interrupt_irq),                  // control_interrupt.irq
		.control_address             (control_address),                //           control.address
		.control_byteenable          (control_byteenable),             //                  .byteenable
		.control_write               (control_write),                  //                  .write
		.control_writedata           (control_writedata),              //                  .writedata
		.control_read                (control_read),                   //                  .read
		.control_readdata            (control_readdata),               //                  .readdata
		.control_readdatavalid       (control_readdatavalid),          //                  .readdatavalid
		.control_waitrequest         (control_waitrequest)             //                  .waitrequest
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (~vip_reset_reset_n),             // reset_in0.reset
		.clk            (vip_clk_clk),                    //       clk.clk
		.reset_out      (rst_controller_reset_out_reset), // reset_out.reset
		.reset_req      (),                               // (terminated)
		.reset_req_in0  (1'b0),                           // (terminated)
		.reset_in1      (1'b0),                           // (terminated)
		.reset_req_in1  (1'b0),                           // (terminated)
		.reset_in2      (1'b0),                           // (terminated)
		.reset_req_in2  (1'b0),                           // (terminated)
		.reset_in3      (1'b0),                           // (terminated)
		.reset_req_in3  (1'b0),                           // (terminated)
		.reset_in4      (1'b0),                           // (terminated)
		.reset_req_in4  (1'b0),                           // (terminated)
		.reset_in5      (1'b0),                           // (terminated)
		.reset_req_in5  (1'b0),                           // (terminated)
		.reset_in6      (1'b0),                           // (terminated)
		.reset_req_in6  (1'b0),                           // (terminated)
		.reset_in7      (1'b0),                           // (terminated)
		.reset_req_in7  (1'b0),                           // (terminated)
		.reset_in8      (1'b0),                           // (terminated)
		.reset_req_in8  (1'b0),                           // (terminated)
		.reset_in9      (1'b0),                           // (terminated)
		.reset_req_in9  (1'b0),                           // (terminated)
		.reset_in10     (1'b0),                           // (terminated)
		.reset_req_in10 (1'b0),                           // (terminated)
		.reset_in11     (1'b0),                           // (terminated)
		.reset_req_in11 (1'b0),                           // (terminated)
		.reset_in12     (1'b0),                           // (terminated)
		.reset_req_in12 (1'b0),                           // (terminated)
		.reset_in13     (1'b0),                           // (terminated)
		.reset_req_in13 (1'b0),                           // (terminated)
		.reset_in14     (1'b0),                           // (terminated)
		.reset_req_in14 (1'b0),                           // (terminated)
		.reset_in15     (1'b0),                           // (terminated)
		.reset_req_in15 (1'b0)                            // (terminated)
	);

endmodule
