// soc_system_mm_interconnect_7.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 18.1 646

`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_7 (
		input  wire         vid_clk_clk_clk,                                                 //                                               vid_clk_clk.clk
		input  wire         cam_0_cam_reset_reset_bridge_in_reset_reset,                     //                     cam_0_cam_reset_reset_bridge_in_reset.reset
		input  wire         cam_0_master_wr_translator_reset_reset_bridge_in_reset_reset,    //    cam_0_master_wr_translator_reset_reset_bridge_in_reset.reset
		input  wire         mm_clock_crossing_bridge_1_s0_reset_reset_bridge_in_reset_reset, // mm_clock_crossing_bridge_1_s0_reset_reset_bridge_in_reset.reset
		input  wire         vid_0_vip_reset_reset_bridge_in_reset_reset,                     //                     vid_0_vip_reset_reset_bridge_in_reset.reset
		input  wire [31:0]  cam_0_master_wr_address,                                         //                                           cam_0_master_wr.address
		output wire         cam_0_master_wr_waitrequest,                                     //                                                          .waitrequest
		input  wire [3:0]   cam_0_master_wr_burstcount,                                      //                                                          .burstcount
		input  wire [31:0]  cam_0_master_wr_byteenable,                                      //                                                          .byteenable
		input  wire         cam_0_master_wr_write,                                           //                                                          .write
		input  wire [255:0] cam_0_master_wr_writedata,                                       //                                                          .writedata
		input  wire [31:0]  vid_0_master_rd_address,                                         //                                           vid_0_master_rd.address
		output wire         vid_0_master_rd_waitrequest,                                     //                                                          .waitrequest
		input  wire [4:0]   vid_0_master_rd_burstcount,                                      //                                                          .burstcount
		input  wire         vid_0_master_rd_read,                                            //                                                          .read
		output wire [255:0] vid_0_master_rd_readdata,                                        //                                                          .readdata
		output wire         vid_0_master_rd_readdatavalid,                                   //                                                          .readdatavalid
		output wire [31:0]  mm_clock_crossing_bridge_1_s0_address,                           //                             mm_clock_crossing_bridge_1_s0.address
		output wire         mm_clock_crossing_bridge_1_s0_write,                             //                                                          .write
		output wire         mm_clock_crossing_bridge_1_s0_read,                              //                                                          .read
		input  wire [255:0] mm_clock_crossing_bridge_1_s0_readdata,                          //                                                          .readdata
		output wire [255:0] mm_clock_crossing_bridge_1_s0_writedata,                         //                                                          .writedata
		output wire [4:0]   mm_clock_crossing_bridge_1_s0_burstcount,                        //                                                          .burstcount
		output wire [31:0]  mm_clock_crossing_bridge_1_s0_byteenable,                        //                                                          .byteenable
		input  wire         mm_clock_crossing_bridge_1_s0_readdatavalid,                     //                                                          .readdatavalid
		input  wire         mm_clock_crossing_bridge_1_s0_waitrequest,                       //                                                          .waitrequest
		output wire         mm_clock_crossing_bridge_1_s0_debugaccess                        //                                                          .debugaccess
	);

	wire          vid_0_master_rd_translator_avalon_universal_master_0_waitrequest;   // vid_0_master_rd_agent:av_waitrequest -> vid_0_master_rd_translator:uav_waitrequest
	wire  [255:0] vid_0_master_rd_translator_avalon_universal_master_0_readdata;      // vid_0_master_rd_agent:av_readdata -> vid_0_master_rd_translator:uav_readdata
	wire          vid_0_master_rd_translator_avalon_universal_master_0_debugaccess;   // vid_0_master_rd_translator:uav_debugaccess -> vid_0_master_rd_agent:av_debugaccess
	wire   [31:0] vid_0_master_rd_translator_avalon_universal_master_0_address;       // vid_0_master_rd_translator:uav_address -> vid_0_master_rd_agent:av_address
	wire          vid_0_master_rd_translator_avalon_universal_master_0_read;          // vid_0_master_rd_translator:uav_read -> vid_0_master_rd_agent:av_read
	wire   [31:0] vid_0_master_rd_translator_avalon_universal_master_0_byteenable;    // vid_0_master_rd_translator:uav_byteenable -> vid_0_master_rd_agent:av_byteenable
	wire          vid_0_master_rd_translator_avalon_universal_master_0_readdatavalid; // vid_0_master_rd_agent:av_readdatavalid -> vid_0_master_rd_translator:uav_readdatavalid
	wire          vid_0_master_rd_translator_avalon_universal_master_0_lock;          // vid_0_master_rd_translator:uav_lock -> vid_0_master_rd_agent:av_lock
	wire          vid_0_master_rd_translator_avalon_universal_master_0_write;         // vid_0_master_rd_translator:uav_write -> vid_0_master_rd_agent:av_write
	wire  [255:0] vid_0_master_rd_translator_avalon_universal_master_0_writedata;     // vid_0_master_rd_translator:uav_writedata -> vid_0_master_rd_agent:av_writedata
	wire    [9:0] vid_0_master_rd_translator_avalon_universal_master_0_burstcount;    // vid_0_master_rd_translator:uav_burstcount -> vid_0_master_rd_agent:av_burstcount
	wire          rsp_mux_src_valid;                                                  // rsp_mux:src_valid -> vid_0_master_rd_agent:rp_valid
	wire  [360:0] rsp_mux_src_data;                                                   // rsp_mux:src_data -> vid_0_master_rd_agent:rp_data
	wire          rsp_mux_src_ready;                                                  // vid_0_master_rd_agent:rp_ready -> rsp_mux:src_ready
	wire    [1:0] rsp_mux_src_channel;                                                // rsp_mux:src_channel -> vid_0_master_rd_agent:rp_channel
	wire          rsp_mux_src_startofpacket;                                          // rsp_mux:src_startofpacket -> vid_0_master_rd_agent:rp_startofpacket
	wire          rsp_mux_src_endofpacket;                                            // rsp_mux:src_endofpacket -> vid_0_master_rd_agent:rp_endofpacket
	wire          cam_0_master_wr_translator_avalon_universal_master_0_waitrequest;   // cam_0_master_wr_agent:av_waitrequest -> cam_0_master_wr_translator:uav_waitrequest
	wire  [255:0] cam_0_master_wr_translator_avalon_universal_master_0_readdata;      // cam_0_master_wr_agent:av_readdata -> cam_0_master_wr_translator:uav_readdata
	wire          cam_0_master_wr_translator_avalon_universal_master_0_debugaccess;   // cam_0_master_wr_translator:uav_debugaccess -> cam_0_master_wr_agent:av_debugaccess
	wire   [31:0] cam_0_master_wr_translator_avalon_universal_master_0_address;       // cam_0_master_wr_translator:uav_address -> cam_0_master_wr_agent:av_address
	wire          cam_0_master_wr_translator_avalon_universal_master_0_read;          // cam_0_master_wr_translator:uav_read -> cam_0_master_wr_agent:av_read
	wire   [31:0] cam_0_master_wr_translator_avalon_universal_master_0_byteenable;    // cam_0_master_wr_translator:uav_byteenable -> cam_0_master_wr_agent:av_byteenable
	wire          cam_0_master_wr_translator_avalon_universal_master_0_readdatavalid; // cam_0_master_wr_agent:av_readdatavalid -> cam_0_master_wr_translator:uav_readdatavalid
	wire          cam_0_master_wr_translator_avalon_universal_master_0_lock;          // cam_0_master_wr_translator:uav_lock -> cam_0_master_wr_agent:av_lock
	wire          cam_0_master_wr_translator_avalon_universal_master_0_write;         // cam_0_master_wr_translator:uav_write -> cam_0_master_wr_agent:av_write
	wire  [255:0] cam_0_master_wr_translator_avalon_universal_master_0_writedata;     // cam_0_master_wr_translator:uav_writedata -> cam_0_master_wr_agent:av_writedata
	wire    [8:0] cam_0_master_wr_translator_avalon_universal_master_0_burstcount;    // cam_0_master_wr_translator:uav_burstcount -> cam_0_master_wr_agent:av_burstcount
	wire          rsp_mux_001_src_valid;                                              // rsp_mux_001:src_valid -> cam_0_master_wr_agent:rp_valid
	wire  [360:0] rsp_mux_001_src_data;                                               // rsp_mux_001:src_data -> cam_0_master_wr_agent:rp_data
	wire          rsp_mux_001_src_ready;                                              // cam_0_master_wr_agent:rp_ready -> rsp_mux_001:src_ready
	wire    [1:0] rsp_mux_001_src_channel;                                            // rsp_mux_001:src_channel -> cam_0_master_wr_agent:rp_channel
	wire          rsp_mux_001_src_startofpacket;                                      // rsp_mux_001:src_startofpacket -> cam_0_master_wr_agent:rp_startofpacket
	wire          rsp_mux_001_src_endofpacket;                                        // rsp_mux_001:src_endofpacket -> cam_0_master_wr_agent:rp_endofpacket
	wire  [255:0] mm_clock_crossing_bridge_1_s0_agent_m0_readdata;                    // mm_clock_crossing_bridge_1_s0_translator:uav_readdata -> mm_clock_crossing_bridge_1_s0_agent:m0_readdata
	wire          mm_clock_crossing_bridge_1_s0_agent_m0_waitrequest;                 // mm_clock_crossing_bridge_1_s0_translator:uav_waitrequest -> mm_clock_crossing_bridge_1_s0_agent:m0_waitrequest
	wire          mm_clock_crossing_bridge_1_s0_agent_m0_debugaccess;                 // mm_clock_crossing_bridge_1_s0_agent:m0_debugaccess -> mm_clock_crossing_bridge_1_s0_translator:uav_debugaccess
	wire   [31:0] mm_clock_crossing_bridge_1_s0_agent_m0_address;                     // mm_clock_crossing_bridge_1_s0_agent:m0_address -> mm_clock_crossing_bridge_1_s0_translator:uav_address
	wire   [31:0] mm_clock_crossing_bridge_1_s0_agent_m0_byteenable;                  // mm_clock_crossing_bridge_1_s0_agent:m0_byteenable -> mm_clock_crossing_bridge_1_s0_translator:uav_byteenable
	wire          mm_clock_crossing_bridge_1_s0_agent_m0_read;                        // mm_clock_crossing_bridge_1_s0_agent:m0_read -> mm_clock_crossing_bridge_1_s0_translator:uav_read
	wire          mm_clock_crossing_bridge_1_s0_agent_m0_readdatavalid;               // mm_clock_crossing_bridge_1_s0_translator:uav_readdatavalid -> mm_clock_crossing_bridge_1_s0_agent:m0_readdatavalid
	wire          mm_clock_crossing_bridge_1_s0_agent_m0_lock;                        // mm_clock_crossing_bridge_1_s0_agent:m0_lock -> mm_clock_crossing_bridge_1_s0_translator:uav_lock
	wire  [255:0] mm_clock_crossing_bridge_1_s0_agent_m0_writedata;                   // mm_clock_crossing_bridge_1_s0_agent:m0_writedata -> mm_clock_crossing_bridge_1_s0_translator:uav_writedata
	wire          mm_clock_crossing_bridge_1_s0_agent_m0_write;                       // mm_clock_crossing_bridge_1_s0_agent:m0_write -> mm_clock_crossing_bridge_1_s0_translator:uav_write
	wire    [9:0] mm_clock_crossing_bridge_1_s0_agent_m0_burstcount;                  // mm_clock_crossing_bridge_1_s0_agent:m0_burstcount -> mm_clock_crossing_bridge_1_s0_translator:uav_burstcount
	wire          mm_clock_crossing_bridge_1_s0_agent_rf_source_valid;                // mm_clock_crossing_bridge_1_s0_agent:rf_source_valid -> mm_clock_crossing_bridge_1_s0_agent_rsp_fifo:in_valid
	wire  [361:0] mm_clock_crossing_bridge_1_s0_agent_rf_source_data;                 // mm_clock_crossing_bridge_1_s0_agent:rf_source_data -> mm_clock_crossing_bridge_1_s0_agent_rsp_fifo:in_data
	wire          mm_clock_crossing_bridge_1_s0_agent_rf_source_ready;                // mm_clock_crossing_bridge_1_s0_agent_rsp_fifo:in_ready -> mm_clock_crossing_bridge_1_s0_agent:rf_source_ready
	wire          mm_clock_crossing_bridge_1_s0_agent_rf_source_startofpacket;        // mm_clock_crossing_bridge_1_s0_agent:rf_source_startofpacket -> mm_clock_crossing_bridge_1_s0_agent_rsp_fifo:in_startofpacket
	wire          mm_clock_crossing_bridge_1_s0_agent_rf_source_endofpacket;          // mm_clock_crossing_bridge_1_s0_agent:rf_source_endofpacket -> mm_clock_crossing_bridge_1_s0_agent_rsp_fifo:in_endofpacket
	wire          mm_clock_crossing_bridge_1_s0_agent_rsp_fifo_out_valid;             // mm_clock_crossing_bridge_1_s0_agent_rsp_fifo:out_valid -> mm_clock_crossing_bridge_1_s0_agent:rf_sink_valid
	wire  [361:0] mm_clock_crossing_bridge_1_s0_agent_rsp_fifo_out_data;              // mm_clock_crossing_bridge_1_s0_agent_rsp_fifo:out_data -> mm_clock_crossing_bridge_1_s0_agent:rf_sink_data
	wire          mm_clock_crossing_bridge_1_s0_agent_rsp_fifo_out_ready;             // mm_clock_crossing_bridge_1_s0_agent:rf_sink_ready -> mm_clock_crossing_bridge_1_s0_agent_rsp_fifo:out_ready
	wire          mm_clock_crossing_bridge_1_s0_agent_rsp_fifo_out_startofpacket;     // mm_clock_crossing_bridge_1_s0_agent_rsp_fifo:out_startofpacket -> mm_clock_crossing_bridge_1_s0_agent:rf_sink_startofpacket
	wire          mm_clock_crossing_bridge_1_s0_agent_rsp_fifo_out_endofpacket;       // mm_clock_crossing_bridge_1_s0_agent_rsp_fifo:out_endofpacket -> mm_clock_crossing_bridge_1_s0_agent:rf_sink_endofpacket
	wire          cmd_mux_src_valid;                                                  // cmd_mux:src_valid -> mm_clock_crossing_bridge_1_s0_agent:cp_valid
	wire  [360:0] cmd_mux_src_data;                                                   // cmd_mux:src_data -> mm_clock_crossing_bridge_1_s0_agent:cp_data
	wire          cmd_mux_src_ready;                                                  // mm_clock_crossing_bridge_1_s0_agent:cp_ready -> cmd_mux:src_ready
	wire    [1:0] cmd_mux_src_channel;                                                // cmd_mux:src_channel -> mm_clock_crossing_bridge_1_s0_agent:cp_channel
	wire          cmd_mux_src_startofpacket;                                          // cmd_mux:src_startofpacket -> mm_clock_crossing_bridge_1_s0_agent:cp_startofpacket
	wire          cmd_mux_src_endofpacket;                                            // cmd_mux:src_endofpacket -> mm_clock_crossing_bridge_1_s0_agent:cp_endofpacket
	wire          vid_0_master_rd_agent_cp_valid;                                     // vid_0_master_rd_agent:cp_valid -> router:sink_valid
	wire  [360:0] vid_0_master_rd_agent_cp_data;                                      // vid_0_master_rd_agent:cp_data -> router:sink_data
	wire          vid_0_master_rd_agent_cp_ready;                                     // router:sink_ready -> vid_0_master_rd_agent:cp_ready
	wire          vid_0_master_rd_agent_cp_startofpacket;                             // vid_0_master_rd_agent:cp_startofpacket -> router:sink_startofpacket
	wire          vid_0_master_rd_agent_cp_endofpacket;                               // vid_0_master_rd_agent:cp_endofpacket -> router:sink_endofpacket
	wire          router_src_valid;                                                   // router:src_valid -> cmd_demux:sink_valid
	wire  [360:0] router_src_data;                                                    // router:src_data -> cmd_demux:sink_data
	wire          router_src_ready;                                                   // cmd_demux:sink_ready -> router:src_ready
	wire    [1:0] router_src_channel;                                                 // router:src_channel -> cmd_demux:sink_channel
	wire          router_src_startofpacket;                                           // router:src_startofpacket -> cmd_demux:sink_startofpacket
	wire          router_src_endofpacket;                                             // router:src_endofpacket -> cmd_demux:sink_endofpacket
	wire          cam_0_master_wr_agent_cp_valid;                                     // cam_0_master_wr_agent:cp_valid -> router_001:sink_valid
	wire  [360:0] cam_0_master_wr_agent_cp_data;                                      // cam_0_master_wr_agent:cp_data -> router_001:sink_data
	wire          cam_0_master_wr_agent_cp_ready;                                     // router_001:sink_ready -> cam_0_master_wr_agent:cp_ready
	wire          cam_0_master_wr_agent_cp_startofpacket;                             // cam_0_master_wr_agent:cp_startofpacket -> router_001:sink_startofpacket
	wire          cam_0_master_wr_agent_cp_endofpacket;                               // cam_0_master_wr_agent:cp_endofpacket -> router_001:sink_endofpacket
	wire          router_001_src_valid;                                               // router_001:src_valid -> cmd_demux_001:sink_valid
	wire  [360:0] router_001_src_data;                                                // router_001:src_data -> cmd_demux_001:sink_data
	wire          router_001_src_ready;                                               // cmd_demux_001:sink_ready -> router_001:src_ready
	wire    [1:0] router_001_src_channel;                                             // router_001:src_channel -> cmd_demux_001:sink_channel
	wire          router_001_src_startofpacket;                                       // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
	wire          router_001_src_endofpacket;                                         // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
	wire          mm_clock_crossing_bridge_1_s0_agent_rp_valid;                       // mm_clock_crossing_bridge_1_s0_agent:rp_valid -> router_002:sink_valid
	wire  [360:0] mm_clock_crossing_bridge_1_s0_agent_rp_data;                        // mm_clock_crossing_bridge_1_s0_agent:rp_data -> router_002:sink_data
	wire          mm_clock_crossing_bridge_1_s0_agent_rp_ready;                       // router_002:sink_ready -> mm_clock_crossing_bridge_1_s0_agent:rp_ready
	wire          mm_clock_crossing_bridge_1_s0_agent_rp_startofpacket;               // mm_clock_crossing_bridge_1_s0_agent:rp_startofpacket -> router_002:sink_startofpacket
	wire          mm_clock_crossing_bridge_1_s0_agent_rp_endofpacket;                 // mm_clock_crossing_bridge_1_s0_agent:rp_endofpacket -> router_002:sink_endofpacket
	wire          router_002_src_valid;                                               // router_002:src_valid -> rsp_demux:sink_valid
	wire  [360:0] router_002_src_data;                                                // router_002:src_data -> rsp_demux:sink_data
	wire          router_002_src_ready;                                               // rsp_demux:sink_ready -> router_002:src_ready
	wire    [1:0] router_002_src_channel;                                             // router_002:src_channel -> rsp_demux:sink_channel
	wire          router_002_src_startofpacket;                                       // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_002_src_endofpacket;                                         // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          cmd_demux_src0_valid;                                               // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire  [360:0] cmd_demux_src0_data;                                                // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire          cmd_demux_src0_ready;                                               // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire    [1:0] cmd_demux_src0_channel;                                             // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire          cmd_demux_src0_startofpacket;                                       // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire          cmd_demux_src0_endofpacket;                                         // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_001_src0_valid;                                           // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
	wire  [360:0] cmd_demux_001_src0_data;                                            // cmd_demux_001:src0_data -> cmd_mux:sink1_data
	wire          cmd_demux_001_src0_ready;                                           // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
	wire    [1:0] cmd_demux_001_src0_channel;                                         // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
	wire          cmd_demux_001_src0_startofpacket;                                   // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
	wire          cmd_demux_001_src0_endofpacket;                                     // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
	wire          rsp_demux_src0_valid;                                               // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire  [360:0] rsp_demux_src0_data;                                                // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire          rsp_demux_src0_ready;                                               // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire    [1:0] rsp_demux_src0_channel;                                             // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire          rsp_demux_src0_startofpacket;                                       // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire          rsp_demux_src0_endofpacket;                                         // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_src1_valid;                                               // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
	wire  [360:0] rsp_demux_src1_data;                                                // rsp_demux:src1_data -> rsp_mux_001:sink0_data
	wire          rsp_demux_src1_ready;                                               // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
	wire    [1:0] rsp_demux_src1_channel;                                             // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
	wire          rsp_demux_src1_startofpacket;                                       // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
	wire          rsp_demux_src1_endofpacket;                                         // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
	wire          mm_clock_crossing_bridge_1_s0_agent_rdata_fifo_src_valid;           // mm_clock_crossing_bridge_1_s0_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
	wire  [257:0] mm_clock_crossing_bridge_1_s0_agent_rdata_fifo_src_data;            // mm_clock_crossing_bridge_1_s0_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
	wire          mm_clock_crossing_bridge_1_s0_agent_rdata_fifo_src_ready;           // avalon_st_adapter:in_0_ready -> mm_clock_crossing_bridge_1_s0_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_out_0_valid;                                      // avalon_st_adapter:out_0_valid -> mm_clock_crossing_bridge_1_s0_agent:rdata_fifo_sink_valid
	wire  [257:0] avalon_st_adapter_out_0_data;                                       // avalon_st_adapter:out_0_data -> mm_clock_crossing_bridge_1_s0_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_out_0_ready;                                      // mm_clock_crossing_bridge_1_s0_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
	wire    [0:0] avalon_st_adapter_out_0_error;                                      // avalon_st_adapter:out_0_error -> mm_clock_crossing_bridge_1_s0_agent:rdata_fifo_sink_error

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (256),
		.AV_BURSTCOUNT_W             (5),
		.AV_BYTEENABLE_W             (32),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (10),
		.USE_READ                    (1),
		.USE_WRITE                   (0),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (32),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) vid_0_master_rd_translator (
		.clk                    (vid_clk_clk_clk),                                                                                                                                                                                                                                                       //                       clk.clk
		.reset                  (mm_clock_crossing_bridge_1_s0_reset_reset_bridge_in_reset_reset),                                                                                                                                                                                                       //                     reset.reset
		.uav_address            (vid_0_master_rd_translator_avalon_universal_master_0_address),                                                                                                                                                                                                          // avalon_universal_master_0.address
		.uav_burstcount         (vid_0_master_rd_translator_avalon_universal_master_0_burstcount),                                                                                                                                                                                                       //                          .burstcount
		.uav_read               (vid_0_master_rd_translator_avalon_universal_master_0_read),                                                                                                                                                                                                             //                          .read
		.uav_write              (vid_0_master_rd_translator_avalon_universal_master_0_write),                                                                                                                                                                                                            //                          .write
		.uav_waitrequest        (vid_0_master_rd_translator_avalon_universal_master_0_waitrequest),                                                                                                                                                                                                      //                          .waitrequest
		.uav_readdatavalid      (vid_0_master_rd_translator_avalon_universal_master_0_readdatavalid),                                                                                                                                                                                                    //                          .readdatavalid
		.uav_byteenable         (vid_0_master_rd_translator_avalon_universal_master_0_byteenable),                                                                                                                                                                                                       //                          .byteenable
		.uav_readdata           (vid_0_master_rd_translator_avalon_universal_master_0_readdata),                                                                                                                                                                                                         //                          .readdata
		.uav_writedata          (vid_0_master_rd_translator_avalon_universal_master_0_writedata),                                                                                                                                                                                                        //                          .writedata
		.uav_lock               (vid_0_master_rd_translator_avalon_universal_master_0_lock),                                                                                                                                                                                                             //                          .lock
		.uav_debugaccess        (vid_0_master_rd_translator_avalon_universal_master_0_debugaccess),                                                                                                                                                                                                      //                          .debugaccess
		.av_address             (vid_0_master_rd_address),                                                                                                                                                                                                                                               //      avalon_anti_master_0.address
		.av_waitrequest         (vid_0_master_rd_waitrequest),                                                                                                                                                                                                                                           //                          .waitrequest
		.av_burstcount          (vid_0_master_rd_burstcount),                                                                                                                                                                                                                                            //                          .burstcount
		.av_read                (vid_0_master_rd_read),                                                                                                                                                                                                                                                  //                          .read
		.av_readdata            (vid_0_master_rd_readdata),                                                                                                                                                                                                                                              //                          .readdata
		.av_readdatavalid       (vid_0_master_rd_readdatavalid),                                                                                                                                                                                                                                         //                          .readdatavalid
		.av_byteenable          (32'b11111111111111111111111111111111),                                                                                                                                                                                                                                  //               (terminated)
		.av_beginbursttransfer  (1'b0),                                                                                                                                                                                                                                                                  //               (terminated)
		.av_begintransfer       (1'b0),                                                                                                                                                                                                                                                                  //               (terminated)
		.av_chipselect          (1'b0),                                                                                                                                                                                                                                                                  //               (terminated)
		.av_write               (1'b0),                                                                                                                                                                                                                                                                  //               (terminated)
		.av_writedata           (256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), //               (terminated)
		.av_lock                (1'b0),                                                                                                                                                                                                                                                                  //               (terminated)
		.av_debugaccess         (1'b0),                                                                                                                                                                                                                                                                  //               (terminated)
		.uav_clken              (),                                                                                                                                                                                                                                                                      //               (terminated)
		.av_clken               (1'b1),                                                                                                                                                                                                                                                                  //               (terminated)
		.uav_response           (2'b00),                                                                                                                                                                                                                                                                 //               (terminated)
		.av_response            (),                                                                                                                                                                                                                                                                      //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                                                                                                                                                                                                                  //               (terminated)
		.av_writeresponsevalid  ()                                                                                                                                                                                                                                                                       //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (256),
		.AV_BURSTCOUNT_W             (4),
		.AV_BYTEENABLE_W             (32),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (9),
		.USE_READ                    (0),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (0),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (32),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) cam_0_master_wr_translator (
		.clk                    (vid_clk_clk_clk),                                                    //                       clk.clk
		.reset                  (cam_0_master_wr_translator_reset_reset_bridge_in_reset_reset),       //                     reset.reset
		.uav_address            (cam_0_master_wr_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (cam_0_master_wr_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (cam_0_master_wr_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (cam_0_master_wr_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (cam_0_master_wr_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (cam_0_master_wr_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (cam_0_master_wr_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (cam_0_master_wr_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (cam_0_master_wr_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (cam_0_master_wr_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (cam_0_master_wr_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (cam_0_master_wr_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (cam_0_master_wr_waitrequest),                                        //                          .waitrequest
		.av_burstcount          (cam_0_master_wr_burstcount),                                         //                          .burstcount
		.av_byteenable          (cam_0_master_wr_byteenable),                                         //                          .byteenable
		.av_write               (cam_0_master_wr_write),                                              //                          .write
		.av_writedata           (cam_0_master_wr_writedata),                                          //                          .writedata
		.av_beginbursttransfer  (1'b0),                                                               //               (terminated)
		.av_begintransfer       (1'b0),                                                               //               (terminated)
		.av_chipselect          (1'b0),                                                               //               (terminated)
		.av_read                (1'b0),                                                               //               (terminated)
		.av_readdata            (),                                                                   //               (terminated)
		.av_readdatavalid       (),                                                                   //               (terminated)
		.av_lock                (1'b0),                                                               //               (terminated)
		.av_debugaccess         (1'b0),                                                               //               (terminated)
		.uav_clken              (),                                                                   //               (terminated)
		.av_clken               (1'b1),                                                               //               (terminated)
		.uav_response           (2'b00),                                                              //               (terminated)
		.av_response            (),                                                                   //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                               //               (terminated)
		.av_writeresponsevalid  ()                                                                    //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (32),
		.AV_DATA_W                      (256),
		.UAV_DATA_W                     (256),
		.AV_BURSTCOUNT_W                (5),
		.AV_BYTEENABLE_W                (32),
		.UAV_BYTEENABLE_W               (32),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (10),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (32),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) mm_clock_crossing_bridge_1_s0_translator (
		.clk                    (vid_clk_clk_clk),                                                 //                      clk.clk
		.reset                  (mm_clock_crossing_bridge_1_s0_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (mm_clock_crossing_bridge_1_s0_agent_m0_address),                  // avalon_universal_slave_0.address
		.uav_burstcount         (mm_clock_crossing_bridge_1_s0_agent_m0_burstcount),               //                         .burstcount
		.uav_read               (mm_clock_crossing_bridge_1_s0_agent_m0_read),                     //                         .read
		.uav_write              (mm_clock_crossing_bridge_1_s0_agent_m0_write),                    //                         .write
		.uav_waitrequest        (mm_clock_crossing_bridge_1_s0_agent_m0_waitrequest),              //                         .waitrequest
		.uav_readdatavalid      (mm_clock_crossing_bridge_1_s0_agent_m0_readdatavalid),            //                         .readdatavalid
		.uav_byteenable         (mm_clock_crossing_bridge_1_s0_agent_m0_byteenable),               //                         .byteenable
		.uav_readdata           (mm_clock_crossing_bridge_1_s0_agent_m0_readdata),                 //                         .readdata
		.uav_writedata          (mm_clock_crossing_bridge_1_s0_agent_m0_writedata),                //                         .writedata
		.uav_lock               (mm_clock_crossing_bridge_1_s0_agent_m0_lock),                     //                         .lock
		.uav_debugaccess        (mm_clock_crossing_bridge_1_s0_agent_m0_debugaccess),              //                         .debugaccess
		.av_address             (mm_clock_crossing_bridge_1_s0_address),                           //      avalon_anti_slave_0.address
		.av_write               (mm_clock_crossing_bridge_1_s0_write),                             //                         .write
		.av_read                (mm_clock_crossing_bridge_1_s0_read),                              //                         .read
		.av_readdata            (mm_clock_crossing_bridge_1_s0_readdata),                          //                         .readdata
		.av_writedata           (mm_clock_crossing_bridge_1_s0_writedata),                         //                         .writedata
		.av_burstcount          (mm_clock_crossing_bridge_1_s0_burstcount),                        //                         .burstcount
		.av_byteenable          (mm_clock_crossing_bridge_1_s0_byteenable),                        //                         .byteenable
		.av_readdatavalid       (mm_clock_crossing_bridge_1_s0_readdatavalid),                     //                         .readdatavalid
		.av_waitrequest         (mm_clock_crossing_bridge_1_s0_waitrequest),                       //                         .waitrequest
		.av_debugaccess         (mm_clock_crossing_bridge_1_s0_debugaccess),                       //                         .debugaccess
		.av_begintransfer       (),                                                                //              (terminated)
		.av_beginbursttransfer  (),                                                                //              (terminated)
		.av_writebyteenable     (),                                                                //              (terminated)
		.av_lock                (),                                                                //              (terminated)
		.av_chipselect          (),                                                                //              (terminated)
		.av_clken               (),                                                                //              (terminated)
		.uav_clken              (1'b0),                                                            //              (terminated)
		.av_outputenable        (),                                                                //              (terminated)
		.uav_response           (),                                                                //              (terminated)
		.av_response            (2'b00),                                                           //              (terminated)
		.uav_writeresponsevalid (),                                                                //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                             //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (360),
		.PKT_ORI_BURST_SIZE_L      (358),
		.PKT_RESPONSE_STATUS_H     (357),
		.PKT_RESPONSE_STATUS_L     (356),
		.PKT_QOS_H                 (345),
		.PKT_QOS_L                 (345),
		.PKT_DATA_SIDEBAND_H       (343),
		.PKT_DATA_SIDEBAND_L       (343),
		.PKT_ADDR_SIDEBAND_H       (342),
		.PKT_ADDR_SIDEBAND_L       (342),
		.PKT_BURST_TYPE_H          (341),
		.PKT_BURST_TYPE_L          (340),
		.PKT_CACHE_H               (355),
		.PKT_CACHE_L               (352),
		.PKT_THREAD_ID_H           (348),
		.PKT_THREAD_ID_L           (348),
		.PKT_BURST_SIZE_H          (339),
		.PKT_BURST_SIZE_L          (337),
		.PKT_TRANS_EXCLUSIVE       (325),
		.PKT_TRANS_LOCK            (324),
		.PKT_BEGIN_BURST           (344),
		.PKT_PROTECTION_H          (351),
		.PKT_PROTECTION_L          (349),
		.PKT_BURSTWRAP_H           (336),
		.PKT_BURSTWRAP_L           (336),
		.PKT_BYTE_CNT_H            (335),
		.PKT_BYTE_CNT_L            (326),
		.PKT_ADDR_H                (319),
		.PKT_ADDR_L                (288),
		.PKT_TRANS_COMPRESSED_READ (320),
		.PKT_TRANS_POSTED          (321),
		.PKT_TRANS_WRITE           (322),
		.PKT_TRANS_READ            (323),
		.PKT_DATA_H                (255),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (287),
		.PKT_BYTEEN_L              (256),
		.PKT_SRC_ID_H              (346),
		.PKT_SRC_ID_L              (346),
		.PKT_DEST_ID_H             (347),
		.PKT_DEST_ID_L             (347),
		.ST_DATA_W                 (361),
		.ST_CHANNEL_W              (2),
		.AV_BURSTCOUNT_W           (10),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (1),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) vid_0_master_rd_agent (
		.clk                   (vid_clk_clk_clk),                                                    //       clk.clk
		.reset                 (mm_clock_crossing_bridge_1_s0_reset_reset_bridge_in_reset_reset),    // clk_reset.reset
		.av_address            (vid_0_master_rd_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (vid_0_master_rd_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (vid_0_master_rd_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (vid_0_master_rd_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (vid_0_master_rd_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (vid_0_master_rd_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (vid_0_master_rd_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (vid_0_master_rd_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (vid_0_master_rd_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (vid_0_master_rd_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (vid_0_master_rd_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (vid_0_master_rd_agent_cp_valid),                                     //        cp.valid
		.cp_data               (vid_0_master_rd_agent_cp_data),                                      //          .data
		.cp_startofpacket      (vid_0_master_rd_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (vid_0_master_rd_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (vid_0_master_rd_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_src_valid),                                                  //        rp.valid
		.rp_data               (rsp_mux_src_data),                                                   //          .data
		.rp_channel            (rsp_mux_src_channel),                                                //          .channel
		.rp_startofpacket      (rsp_mux_src_startofpacket),                                          //          .startofpacket
		.rp_endofpacket        (rsp_mux_src_endofpacket),                                            //          .endofpacket
		.rp_ready              (rsp_mux_src_ready),                                                  //          .ready
		.av_response           (),                                                                   // (terminated)
		.av_writeresponsevalid ()                                                                    // (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (360),
		.PKT_ORI_BURST_SIZE_L      (358),
		.PKT_RESPONSE_STATUS_H     (357),
		.PKT_RESPONSE_STATUS_L     (356),
		.PKT_QOS_H                 (345),
		.PKT_QOS_L                 (345),
		.PKT_DATA_SIDEBAND_H       (343),
		.PKT_DATA_SIDEBAND_L       (343),
		.PKT_ADDR_SIDEBAND_H       (342),
		.PKT_ADDR_SIDEBAND_L       (342),
		.PKT_BURST_TYPE_H          (341),
		.PKT_BURST_TYPE_L          (340),
		.PKT_CACHE_H               (355),
		.PKT_CACHE_L               (352),
		.PKT_THREAD_ID_H           (348),
		.PKT_THREAD_ID_L           (348),
		.PKT_BURST_SIZE_H          (339),
		.PKT_BURST_SIZE_L          (337),
		.PKT_TRANS_EXCLUSIVE       (325),
		.PKT_TRANS_LOCK            (324),
		.PKT_BEGIN_BURST           (344),
		.PKT_PROTECTION_H          (351),
		.PKT_PROTECTION_L          (349),
		.PKT_BURSTWRAP_H           (336),
		.PKT_BURSTWRAP_L           (336),
		.PKT_BYTE_CNT_H            (335),
		.PKT_BYTE_CNT_L            (326),
		.PKT_ADDR_H                (319),
		.PKT_ADDR_L                (288),
		.PKT_TRANS_COMPRESSED_READ (320),
		.PKT_TRANS_POSTED          (321),
		.PKT_TRANS_WRITE           (322),
		.PKT_TRANS_READ            (323),
		.PKT_DATA_H                (255),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (287),
		.PKT_BYTEEN_L              (256),
		.PKT_SRC_ID_H              (346),
		.PKT_SRC_ID_L              (346),
		.PKT_DEST_ID_H             (347),
		.PKT_DEST_ID_L             (347),
		.ST_DATA_W                 (361),
		.ST_CHANNEL_W              (2),
		.AV_BURSTCOUNT_W           (9),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) cam_0_master_wr_agent (
		.clk                   (vid_clk_clk_clk),                                                    //       clk.clk
		.reset                 (cam_0_master_wr_translator_reset_reset_bridge_in_reset_reset),       // clk_reset.reset
		.av_address            (cam_0_master_wr_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (cam_0_master_wr_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (cam_0_master_wr_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (cam_0_master_wr_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (cam_0_master_wr_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (cam_0_master_wr_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (cam_0_master_wr_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (cam_0_master_wr_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (cam_0_master_wr_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (cam_0_master_wr_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (cam_0_master_wr_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (cam_0_master_wr_agent_cp_valid),                                     //        cp.valid
		.cp_data               (cam_0_master_wr_agent_cp_data),                                      //          .data
		.cp_startofpacket      (cam_0_master_wr_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (cam_0_master_wr_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (cam_0_master_wr_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_001_src_valid),                                              //        rp.valid
		.rp_data               (rsp_mux_001_src_data),                                               //          .data
		.rp_channel            (rsp_mux_001_src_channel),                                            //          .channel
		.rp_startofpacket      (rsp_mux_001_src_startofpacket),                                      //          .startofpacket
		.rp_endofpacket        (rsp_mux_001_src_endofpacket),                                        //          .endofpacket
		.rp_ready              (rsp_mux_001_src_ready),                                              //          .ready
		.av_response           (),                                                                   // (terminated)
		.av_writeresponsevalid ()                                                                    // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (360),
		.PKT_ORI_BURST_SIZE_L      (358),
		.PKT_RESPONSE_STATUS_H     (357),
		.PKT_RESPONSE_STATUS_L     (356),
		.PKT_BURST_SIZE_H          (339),
		.PKT_BURST_SIZE_L          (337),
		.PKT_TRANS_LOCK            (324),
		.PKT_BEGIN_BURST           (344),
		.PKT_PROTECTION_H          (351),
		.PKT_PROTECTION_L          (349),
		.PKT_BURSTWRAP_H           (336),
		.PKT_BURSTWRAP_L           (336),
		.PKT_BYTE_CNT_H            (335),
		.PKT_BYTE_CNT_L            (326),
		.PKT_ADDR_H                (319),
		.PKT_ADDR_L                (288),
		.PKT_TRANS_COMPRESSED_READ (320),
		.PKT_TRANS_POSTED          (321),
		.PKT_TRANS_WRITE           (322),
		.PKT_TRANS_READ            (323),
		.PKT_DATA_H                (255),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (287),
		.PKT_BYTEEN_L              (256),
		.PKT_SRC_ID_H              (346),
		.PKT_SRC_ID_L              (346),
		.PKT_DEST_ID_H             (347),
		.PKT_DEST_ID_L             (347),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (2),
		.ST_DATA_W                 (361),
		.AVS_BURSTCOUNT_W          (10),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) mm_clock_crossing_bridge_1_s0_agent (
		.clk                     (vid_clk_clk_clk),                                                 //             clk.clk
		.reset                   (mm_clock_crossing_bridge_1_s0_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (mm_clock_crossing_bridge_1_s0_agent_m0_address),                  //              m0.address
		.m0_burstcount           (mm_clock_crossing_bridge_1_s0_agent_m0_burstcount),               //                .burstcount
		.m0_byteenable           (mm_clock_crossing_bridge_1_s0_agent_m0_byteenable),               //                .byteenable
		.m0_debugaccess          (mm_clock_crossing_bridge_1_s0_agent_m0_debugaccess),              //                .debugaccess
		.m0_lock                 (mm_clock_crossing_bridge_1_s0_agent_m0_lock),                     //                .lock
		.m0_readdata             (mm_clock_crossing_bridge_1_s0_agent_m0_readdata),                 //                .readdata
		.m0_readdatavalid        (mm_clock_crossing_bridge_1_s0_agent_m0_readdatavalid),            //                .readdatavalid
		.m0_read                 (mm_clock_crossing_bridge_1_s0_agent_m0_read),                     //                .read
		.m0_waitrequest          (mm_clock_crossing_bridge_1_s0_agent_m0_waitrequest),              //                .waitrequest
		.m0_writedata            (mm_clock_crossing_bridge_1_s0_agent_m0_writedata),                //                .writedata
		.m0_write                (mm_clock_crossing_bridge_1_s0_agent_m0_write),                    //                .write
		.rp_endofpacket          (mm_clock_crossing_bridge_1_s0_agent_rp_endofpacket),              //              rp.endofpacket
		.rp_ready                (mm_clock_crossing_bridge_1_s0_agent_rp_ready),                    //                .ready
		.rp_valid                (mm_clock_crossing_bridge_1_s0_agent_rp_valid),                    //                .valid
		.rp_data                 (mm_clock_crossing_bridge_1_s0_agent_rp_data),                     //                .data
		.rp_startofpacket        (mm_clock_crossing_bridge_1_s0_agent_rp_startofpacket),            //                .startofpacket
		.cp_ready                (cmd_mux_src_ready),                                               //              cp.ready
		.cp_valid                (cmd_mux_src_valid),                                               //                .valid
		.cp_data                 (cmd_mux_src_data),                                                //                .data
		.cp_startofpacket        (cmd_mux_src_startofpacket),                                       //                .startofpacket
		.cp_endofpacket          (cmd_mux_src_endofpacket),                                         //                .endofpacket
		.cp_channel              (cmd_mux_src_channel),                                             //                .channel
		.rf_sink_ready           (mm_clock_crossing_bridge_1_s0_agent_rsp_fifo_out_ready),          //         rf_sink.ready
		.rf_sink_valid           (mm_clock_crossing_bridge_1_s0_agent_rsp_fifo_out_valid),          //                .valid
		.rf_sink_startofpacket   (mm_clock_crossing_bridge_1_s0_agent_rsp_fifo_out_startofpacket),  //                .startofpacket
		.rf_sink_endofpacket     (mm_clock_crossing_bridge_1_s0_agent_rsp_fifo_out_endofpacket),    //                .endofpacket
		.rf_sink_data            (mm_clock_crossing_bridge_1_s0_agent_rsp_fifo_out_data),           //                .data
		.rf_source_ready         (mm_clock_crossing_bridge_1_s0_agent_rf_source_ready),             //       rf_source.ready
		.rf_source_valid         (mm_clock_crossing_bridge_1_s0_agent_rf_source_valid),             //                .valid
		.rf_source_startofpacket (mm_clock_crossing_bridge_1_s0_agent_rf_source_startofpacket),     //                .startofpacket
		.rf_source_endofpacket   (mm_clock_crossing_bridge_1_s0_agent_rf_source_endofpacket),       //                .endofpacket
		.rf_source_data          (mm_clock_crossing_bridge_1_s0_agent_rf_source_data),              //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                                   // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                                   //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                                    //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                                   //                .error
		.rdata_fifo_src_ready    (mm_clock_crossing_bridge_1_s0_agent_rdata_fifo_src_ready),        //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (mm_clock_crossing_bridge_1_s0_agent_rdata_fifo_src_valid),        //                .valid
		.rdata_fifo_src_data     (mm_clock_crossing_bridge_1_s0_agent_rdata_fifo_src_data),         //                .data
		.m0_response             (2'b00),                                                           //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                             //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (362),
		.FIFO_DEPTH          (37),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) mm_clock_crossing_bridge_1_s0_agent_rsp_fifo (
		.clk               (vid_clk_clk_clk),                                                 //       clk.clk
		.reset             (mm_clock_crossing_bridge_1_s0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (mm_clock_crossing_bridge_1_s0_agent_rf_source_data),              //        in.data
		.in_valid          (mm_clock_crossing_bridge_1_s0_agent_rf_source_valid),             //          .valid
		.in_ready          (mm_clock_crossing_bridge_1_s0_agent_rf_source_ready),             //          .ready
		.in_startofpacket  (mm_clock_crossing_bridge_1_s0_agent_rf_source_startofpacket),     //          .startofpacket
		.in_endofpacket    (mm_clock_crossing_bridge_1_s0_agent_rf_source_endofpacket),       //          .endofpacket
		.out_data          (mm_clock_crossing_bridge_1_s0_agent_rsp_fifo_out_data),           //       out.data
		.out_valid         (mm_clock_crossing_bridge_1_s0_agent_rsp_fifo_out_valid),          //          .valid
		.out_ready         (mm_clock_crossing_bridge_1_s0_agent_rsp_fifo_out_ready),          //          .ready
		.out_startofpacket (mm_clock_crossing_bridge_1_s0_agent_rsp_fifo_out_startofpacket),  //          .startofpacket
		.out_endofpacket   (mm_clock_crossing_bridge_1_s0_agent_rsp_fifo_out_endofpacket),    //          .endofpacket
		.csr_address       (2'b00),                                                           // (terminated)
		.csr_read          (1'b0),                                                            // (terminated)
		.csr_write         (1'b0),                                                            // (terminated)
		.csr_readdata      (),                                                                // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                            // (terminated)
		.almost_full_data  (),                                                                // (terminated)
		.almost_empty_data (),                                                                // (terminated)
		.in_empty          (1'b0),                                                            // (terminated)
		.out_empty         (),                                                                // (terminated)
		.in_error          (1'b0),                                                            // (terminated)
		.out_error         (),                                                                // (terminated)
		.in_channel        (1'b0),                                                            // (terminated)
		.out_channel       ()                                                                 // (terminated)
	);

	soc_system_mm_interconnect_7_router router (
		.sink_ready         (vid_0_master_rd_agent_cp_ready),                                  //      sink.ready
		.sink_valid         (vid_0_master_rd_agent_cp_valid),                                  //          .valid
		.sink_data          (vid_0_master_rd_agent_cp_data),                                   //          .data
		.sink_startofpacket (vid_0_master_rd_agent_cp_startofpacket),                          //          .startofpacket
		.sink_endofpacket   (vid_0_master_rd_agent_cp_endofpacket),                            //          .endofpacket
		.clk                (vid_clk_clk_clk),                                                 //       clk.clk
		.reset              (mm_clock_crossing_bridge_1_s0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_src_ready),                                                //       src.ready
		.src_valid          (router_src_valid),                                                //          .valid
		.src_data           (router_src_data),                                                 //          .data
		.src_channel        (router_src_channel),                                              //          .channel
		.src_startofpacket  (router_src_startofpacket),                                        //          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                           //          .endofpacket
	);

	soc_system_mm_interconnect_7_router router_001 (
		.sink_ready         (cam_0_master_wr_agent_cp_ready),                               //      sink.ready
		.sink_valid         (cam_0_master_wr_agent_cp_valid),                               //          .valid
		.sink_data          (cam_0_master_wr_agent_cp_data),                                //          .data
		.sink_startofpacket (cam_0_master_wr_agent_cp_startofpacket),                       //          .startofpacket
		.sink_endofpacket   (cam_0_master_wr_agent_cp_endofpacket),                         //          .endofpacket
		.clk                (vid_clk_clk_clk),                                              //       clk.clk
		.reset              (cam_0_master_wr_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_001_src_ready),                                         //       src.ready
		.src_valid          (router_001_src_valid),                                         //          .valid
		.src_data           (router_001_src_data),                                          //          .data
		.src_channel        (router_001_src_channel),                                       //          .channel
		.src_startofpacket  (router_001_src_startofpacket),                                 //          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                                    //          .endofpacket
	);

	soc_system_mm_interconnect_7_router_002 router_002 (
		.sink_ready         (mm_clock_crossing_bridge_1_s0_agent_rp_ready),                    //      sink.ready
		.sink_valid         (mm_clock_crossing_bridge_1_s0_agent_rp_valid),                    //          .valid
		.sink_data          (mm_clock_crossing_bridge_1_s0_agent_rp_data),                     //          .data
		.sink_startofpacket (mm_clock_crossing_bridge_1_s0_agent_rp_startofpacket),            //          .startofpacket
		.sink_endofpacket   (mm_clock_crossing_bridge_1_s0_agent_rp_endofpacket),              //          .endofpacket
		.clk                (vid_clk_clk_clk),                                                 //       clk.clk
		.reset              (mm_clock_crossing_bridge_1_s0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_002_src_ready),                                            //       src.ready
		.src_valid          (router_002_src_valid),                                            //          .valid
		.src_data           (router_002_src_data),                                             //          .data
		.src_channel        (router_002_src_channel),                                          //          .channel
		.src_startofpacket  (router_002_src_startofpacket),                                    //          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                                       //          .endofpacket
	);

	soc_system_mm_interconnect_7_cmd_demux cmd_demux (
		.clk                (vid_clk_clk_clk),                                                 //       clk.clk
		.reset              (mm_clock_crossing_bridge_1_s0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_src_ready),                                                //      sink.ready
		.sink_channel       (router_src_channel),                                              //          .channel
		.sink_data          (router_src_data),                                                 //          .data
		.sink_startofpacket (router_src_startofpacket),                                        //          .startofpacket
		.sink_endofpacket   (router_src_endofpacket),                                          //          .endofpacket
		.sink_valid         (router_src_valid),                                                //          .valid
		.src0_ready         (cmd_demux_src0_ready),                                            //      src0.ready
		.src0_valid         (cmd_demux_src0_valid),                                            //          .valid
		.src0_data          (cmd_demux_src0_data),                                             //          .data
		.src0_channel       (cmd_demux_src0_channel),                                          //          .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                                    //          .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket)                                       //          .endofpacket
	);

	soc_system_mm_interconnect_7_cmd_demux cmd_demux_001 (
		.clk                (vid_clk_clk_clk),                                              //       clk.clk
		.reset              (cam_0_master_wr_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_001_src_ready),                                         //      sink.ready
		.sink_channel       (router_001_src_channel),                                       //          .channel
		.sink_data          (router_001_src_data),                                          //          .data
		.sink_startofpacket (router_001_src_startofpacket),                                 //          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),                                   //          .endofpacket
		.sink_valid         (router_001_src_valid),                                         //          .valid
		.src0_ready         (cmd_demux_001_src0_ready),                                     //      src0.ready
		.src0_valid         (cmd_demux_001_src0_valid),                                     //          .valid
		.src0_data          (cmd_demux_001_src0_data),                                      //          .data
		.src0_channel       (cmd_demux_001_src0_channel),                                   //          .channel
		.src0_startofpacket (cmd_demux_001_src0_startofpacket),                             //          .startofpacket
		.src0_endofpacket   (cmd_demux_001_src0_endofpacket)                                //          .endofpacket
	);

	soc_system_mm_interconnect_7_cmd_mux cmd_mux (
		.clk                 (vid_clk_clk_clk),                                                 //       clk.clk
		.reset               (mm_clock_crossing_bridge_1_s0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                                               //       src.ready
		.src_valid           (cmd_mux_src_valid),                                               //          .valid
		.src_data            (cmd_mux_src_data),                                                //          .data
		.src_channel         (cmd_mux_src_channel),                                             //          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                                       //          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                                         //          .endofpacket
		.sink0_ready         (cmd_demux_src0_ready),                                            //     sink0.ready
		.sink0_valid         (cmd_demux_src0_valid),                                            //          .valid
		.sink0_channel       (cmd_demux_src0_channel),                                          //          .channel
		.sink0_data          (cmd_demux_src0_data),                                             //          .data
		.sink0_startofpacket (cmd_demux_src0_startofpacket),                                    //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src0_endofpacket),                                      //          .endofpacket
		.sink1_ready         (cmd_demux_001_src0_ready),                                        //     sink1.ready
		.sink1_valid         (cmd_demux_001_src0_valid),                                        //          .valid
		.sink1_channel       (cmd_demux_001_src0_channel),                                      //          .channel
		.sink1_data          (cmd_demux_001_src0_data),                                         //          .data
		.sink1_startofpacket (cmd_demux_001_src0_startofpacket),                                //          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src0_endofpacket)                                   //          .endofpacket
	);

	soc_system_mm_interconnect_7_rsp_demux rsp_demux (
		.clk                (vid_clk_clk_clk),                                                 //       clk.clk
		.reset              (mm_clock_crossing_bridge_1_s0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_002_src_ready),                                            //      sink.ready
		.sink_channel       (router_002_src_channel),                                          //          .channel
		.sink_data          (router_002_src_data),                                             //          .data
		.sink_startofpacket (router_002_src_startofpacket),                                    //          .startofpacket
		.sink_endofpacket   (router_002_src_endofpacket),                                      //          .endofpacket
		.sink_valid         (router_002_src_valid),                                            //          .valid
		.src0_ready         (rsp_demux_src0_ready),                                            //      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                                            //          .valid
		.src0_data          (rsp_demux_src0_data),                                             //          .data
		.src0_channel       (rsp_demux_src0_channel),                                          //          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                                    //          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket),                                      //          .endofpacket
		.src1_ready         (rsp_demux_src1_ready),                                            //      src1.ready
		.src1_valid         (rsp_demux_src1_valid),                                            //          .valid
		.src1_data          (rsp_demux_src1_data),                                             //          .data
		.src1_channel       (rsp_demux_src1_channel),                                          //          .channel
		.src1_startofpacket (rsp_demux_src1_startofpacket),                                    //          .startofpacket
		.src1_endofpacket   (rsp_demux_src1_endofpacket)                                       //          .endofpacket
	);

	soc_system_mm_interconnect_7_rsp_mux rsp_mux (
		.clk                 (vid_clk_clk_clk),                                                 //       clk.clk
		.reset               (mm_clock_crossing_bridge_1_s0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                                               //       src.ready
		.src_valid           (rsp_mux_src_valid),                                               //          .valid
		.src_data            (rsp_mux_src_data),                                                //          .data
		.src_channel         (rsp_mux_src_channel),                                             //          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                                       //          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                                         //          .endofpacket
		.sink0_ready         (rsp_demux_src0_ready),                                            //     sink0.ready
		.sink0_valid         (rsp_demux_src0_valid),                                            //          .valid
		.sink0_channel       (rsp_demux_src0_channel),                                          //          .channel
		.sink0_data          (rsp_demux_src0_data),                                             //          .data
		.sink0_startofpacket (rsp_demux_src0_startofpacket),                                    //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src0_endofpacket)                                       //          .endofpacket
	);

	soc_system_mm_interconnect_7_rsp_mux rsp_mux_001 (
		.clk                 (vid_clk_clk_clk),                                              //       clk.clk
		.reset               (cam_0_master_wr_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_001_src_ready),                                        //       src.ready
		.src_valid           (rsp_mux_001_src_valid),                                        //          .valid
		.src_data            (rsp_mux_001_src_data),                                         //          .data
		.src_channel         (rsp_mux_001_src_channel),                                      //          .channel
		.src_startofpacket   (rsp_mux_001_src_startofpacket),                                //          .startofpacket
		.src_endofpacket     (rsp_mux_001_src_endofpacket),                                  //          .endofpacket
		.sink0_ready         (rsp_demux_src1_ready),                                         //     sink0.ready
		.sink0_valid         (rsp_demux_src1_valid),                                         //          .valid
		.sink0_channel       (rsp_demux_src1_channel),                                       //          .channel
		.sink0_data          (rsp_demux_src1_data),                                          //          .data
		.sink0_startofpacket (rsp_demux_src1_startofpacket),                                 //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src1_endofpacket)                                    //          .endofpacket
	);

	soc_system_mm_interconnect_0_avalon_st_adapter #(
		.inBitsPerSymbol (258),
		.inUsePackets    (0),
		.inDataWidth     (258),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (258),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter (
		.in_clk_0_clk   (vid_clk_clk_clk),                                                 // in_clk_0.clk
		.in_rst_0_reset (mm_clock_crossing_bridge_1_s0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (mm_clock_crossing_bridge_1_s0_agent_rdata_fifo_src_data),         //     in_0.data
		.in_0_valid     (mm_clock_crossing_bridge_1_s0_agent_rdata_fifo_src_valid),        //         .valid
		.in_0_ready     (mm_clock_crossing_bridge_1_s0_agent_rdata_fifo_src_ready),        //         .ready
		.out_0_data     (avalon_st_adapter_out_0_data),                                    //    out_0.data
		.out_0_valid    (avalon_st_adapter_out_0_valid),                                   //         .valid
		.out_0_ready    (avalon_st_adapter_out_0_ready),                                   //         .ready
		.out_0_error    (avalon_st_adapter_out_0_error)                                    //         .error
	);

endmodule
