datasheet for subsys_cam

subsys_cam |

2020.06.26.14:48:18 | Datasheet

Overview

clk_0 | subsys_cam

All Components
cam_pwdn altera_avalon_pio 18.1
mm_bridge_0 altera_avalon_mm_bridge 18.1
scl alt_vip_cl_scl 18.1
vfb alt_vip_cl_vfb 18.1
Memory Map

| vfb
mem_master_wr
cam_pwdn |
s1 |
scl |
control |
vfb |
control |

## cam_pwdn

altera_avalon_pio v18.1

mm_bridge_0 | m0 | cam_pwdn
s1
clk_0 | clk
clk
clk_reset
reset

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
clockRate | 74250000
derived_has_tri | false
derived_has_out | true
derived_has_in | false
derived_do_test_bench_wiring | false
derived_capture | false
derived_edge_type | NONE
derived_irq_type | NONE
derived_has_irq | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 1
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 74250000
HAS_IN | 0
HAS_OUT | 1
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

## clk_0

clock_source v18.1

## Parameters

clockFrequency | 74250000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## crs

alt_vip_cl_crs v18.1

scl | dout | crs
din
clk_0 | clk
main_clock
clk_reset
main_reset
|  | dout | csc
|  | din

## Parameters

SHOW_HIDDEN_FEATURES | 1
BITS_PER_SYMBOL | 8
NUMBER_OF_COLOR_PLANES | 2
COLOR_PLANES_ARE_IN_PARALLEL | 1
PIXELS_IN_PARALLEL | 1
PIP_IN | 1
PIP_OUT | 1
MAX_WIDTH | 1280
MAX_HEIGHT | 720
HORIZ_ALGORITHM | BILINEAR
HORIZ_CO_SITING | LEFT
HORIZ_ENABLE_LUMA_ADAPT | 1
VERT_ALGORITHM | BILINEAR
VERT_CO_SITING | TOP
VERT_ENABLE_LUMA_ADAPT | 0
VARIABLE_SIDE | NEITHER
ENABLE_444_IN | 0
ENABLE_422_IN | 1
ENABLE_420_IN | 0
ENABLE_444_OUT | 1
ENABLE_422_OUT | 0
ENABLE_420_OUT | 0
USER_PACKET_SUPPORT | NONE_ALLOWED
USER_PACKET_FIFO_DEPTH | 0
PIPELINE_READY | 0
LIMITED_READBACK | 1
AUTO_DEVICE_FAMILY | CYCLONEV
AUTO_DEVICE | 5CSXFC6C6U23I7
AUTO_DEVICE_SPEEDGRADE | 7_H6
deviceFamily | Cyclone V
generateLegacySim | false

## Software Assignments

(none)

## csc

alt_vip_cl_csc v18.1

crs | dout | csc
din
clk_0 | clk
main_clock
clk_reset
main_reset
|  | dout | vfb
|  | din

## Parameters

INPUT_BITS_PER_SYMBOL | 8
OUTPUT_BITS_PER_SYMBOL | 8
NUMBER_OF_COLOR_PLANES | 3
COLOR_PLANES_ARE_IN_PARALLEL | 1
PIXELS_IN_PARALLEL | 1
REQ_FCOEFF_A0 | 2.115
REQ_FCOEFF_A1 | -0.213
REQ_FCOEFF_A2 | 0.0
REQ_FCOEFF_B0 | 0.0
REQ_FCOEFF_B1 | -0.534
REQ_FCOEFF_B2 | 1.793
REQ_FCOEFF_C0 | 1.164
REQ_FCOEFF_C1 | 1.164
REQ_FCOEFF_C2 | 1.164
REQ_FCOEFF_S0 | -289.344
REQ_FCOEFF_S1 | 76.992
REQ_FCOEFF_S2 | -248.128
INPUT_DATA_TYPE_SIGNED | 0
INPUT_DATA_TYPE_GUARD_BAND | 0
INPUT_DATA_TYPE_MIN | 0
INPUT_DATA_TYPE_MAX | 255
OUTPUT_DATA_TYPE_SIGNED | 0
OUTPUT_DATA_TYPE_GUARD_BAND | 0
OUTPUT_DATA_TYPE_MIN | 0
OUTPUT_DATA_TYPE_MAX | 255
COEFFICIENT_SIGNED | 1
COEFFICIENT_INT_BITS | 2
SUMMAND_SIGNED | 1
SUMMAND_INT_BITS | 9
COEF_SUM_FRACTION_BITS | 8
MOVE_BINARY_POINT_RIGHT | 0
REMOVE_FRACTION_METHOD | 1
SIGN_TO_UNSIGN_METHOD | 0
PIPELINE_DATA_OUTPUT | 0
USER_PACKET_SUPPORT | NONE_ALLOWED
CONVERSION_MODE | LSB
RUNTIME_CONTROL | 0
LIMITED_READBACK | 0
FAMILY | CYCLONEV
COEFFICIENT_A0 | 0
COEFFICIENT_A1 | 0
COEFFICIENT_A2 | 0
COEFFICIENT_B0 | 0
COEFFICIENT_B1 | 0
COEFFICIENT_B2 | 0
COEFFICIENT_C0 | 0
COEFFICIENT_C1 | 0
COEFFICIENT_C2 | 0
COEFFICIENT_S0 | 0
COEFFICIENT_S1 | 0
COEFFICIENT_S2 | 0
min_output_s1 | 0.0
max_output_s1 | 0.0
min_output_s2 | 0.0
max_output_s2 | 0.0
min_output_s3 | 0
max_output_s3 | 0
min_output_s4 | 0
max_output_s4 | 0
AUTO_DEVICE | 5CSXFC6C6U23I7
AUTO_DEVICE_SPEEDGRADE | 7_H6
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## cvi

alt_vip_cl_cvi v18.1

clk_0 | clk | cvi
main_clock
clk_reset
main_reset
|  | dout_0 | scl
|  | din

## Parameters

BPS | 8
NUMBER_OF_COLOUR_PLANES | 2
COLOUR_PLANES_ARE_IN_PARALLEL | 1
PIXELS_IN_PARALLEL | 1
SYNC_TO | 2
NO_OF_CHANNELS | 1
MATCH_CTRLDATA_PKT_CLIP_BASIC | 0
MATCH_CTRLDATA_PKT_PAD_ADV | 0
OVERFLOW_HANDLING | 0
USE_EMBEDDED_SYNCS | 0
USE_HDMI_DEPRICATION | 0
ACCEPT_COLOURS_IN_SEQ | 1
GENERATE_VID_F | 0
USE_STD | 0
STD_WIDTH | 1
GENERATE_ANC | 0
ANC_DEPTH | 1
EXTRACT_TOTAL_RESOLUTION | 1
INTERLACED | 0
H_ACTIVE_PIXELS_F0 | 640
V_ACTIVE_LINES_F0 | 480
V_ACTIVE_LINES_F1 | 32
FIFO_DEPTH | 1024
CLOCKS_ARE_SAME | 0
USE_CONTROL | 0
AUTO_DEVICE_FAMILY | CYCLONEV
AUTO_DEVICE | 5CSXFC6C6U23I7
AUTO_DEVICE_SPEEDGRADE | 7_H6
deviceFamily | Cyclone V
generateLegacySim | false

## Software Assignments

(none)

## mm_bridge_0

altera_avalon_mm_bridge v18.1

clk_0 | clk | mm_bridge_0
clk
clk_reset
reset
|  | m0 | vfb
|  | control
|  | m0 | scl
|  | control
|  | m0 | cam_pwdn
|  | s1

## Parameters

DATA_WIDTH | 32
SYMBOL_WIDTH | 8
ADDRESS_WIDTH | 10
SYSINFO_ADDR_WIDTH | 10
USE_AUTO_ADDRESS_WIDTH | 1
AUTO_ADDRESS_WIDTH | 10
HDL_ADDR_WIDTH | 10
ADDRESS_UNITS | SYMBOLS
BURSTCOUNT_WIDTH | 1
MAX_BURST_SIZE | 1
MAX_PENDING_RESPONSES | 4
LINEWRAPBURSTS | 0
PIPELINE_COMMAND | 1
PIPELINE_RESPONSE | 1
USE_RESPONSE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## scl

alt_vip_cl_scl v18.1

mm_bridge_0 | m0 | scl
control
cvi | dout_0
din
clk_0 | clk
main_clock
clk_reset
main_reset
|  | dout | crs
|  | din

## Parameters

SYMBOLS_IN_SEQ | 1
SYMBOLS_IN_PAR | 2
BITS_PER_SYMBOL | 8
PIXELS_IN_PARALLEL | 1
EXTRA_PIPELINING | 0
IS_422 | 1
NO_BLANKING | 0
MAX_IN_WIDTH | 640
MAX_IN_HEIGHT | 480
MAX_OUT_WIDTH | 1280
MAX_OUT_HEIGHT | 720
RUNTIME_CONTROL | 1
ALGORITHM_NAME | POLYPHASE
DEFAULT_EDGE_THRESH | 7
ARE_IDENTICAL | 1
V_TAPS | 8
V_PHASES | 16
H_TAPS | 8
H_PHASES | 16
V_SIGNED | 1
V_INTEGER_BITS | 1
V_FRACTION_BITS | 7
H_SIGNED | 1
H_INTEGER_BITS | 1
H_FRACTION_BITS | 7
PRESERVE_BITS | 0
LOAD_AT_RUNTIME | 0
V_BANKS | 1
V_FUNCTION | LANCZOS_2
V_COEFF_FILE | <enter file name (including full path)>
H_BANKS | 1
H_FUNCTION | LANCZOS_2
H_COEFF_FILE | <enter file name (including full path)>
USER_PACKET_SUPPORT | NONE_ALLOWED
USER_PACKET_FIFO_DEPTH | 0
LIMITED_READBACK | 1
IS_420 | 0
ALWAYS_DOWNSCALE | 0
DEFAULT_UPPER_BLUR | 0
DEFAULT_LOWER_BLUR | 0
ENABLE_FIR | 0
V_SYMMETRIC | 0
H_SYMMETRIC | 0
FAMILY | CYCLONEV
AUTO_DEVICE | 5CSXFC6C6U23I7
AUTO_DEVICE_SPEEDGRADE | 7_H6
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## vfb

alt_vip_cl_vfb v18.1

mm_bridge_0 | m0 | vfb
control
csc | dout
din
clk_0 | clk
main_clock
clk_reset
main_reset

## Parameters

BITS_PER_SYMBOL | 8
NUMBER_OF_COLOR_PLANES | 3
COLOR_PLANES_ARE_IN_PARALLEL | 1
PIXELS_IN_PARALLEL | 1
READY_LATENCY | 1
MAX_WIDTH | 1280
MAX_HEIGHT | 720
CLOCKS_ARE_SEPARATE | 0
MEM_PORT_WIDTH | 256
MEM_BASE_ADDR | 2130706432
USE_BUFFER_OFFSET | 0
MEM_BUFFER_OFFSET | 16777216
BURST_ALIGNMENT | 1
WRITE_FIFO_DEPTH | 16
WRITE_BURST_TARGET | 8
READ_FIFO_DEPTH | 16
READ_BURST_TARGET | 8
WRITER_RUNTIME_CONTROL | 1
READER_RUNTIME_CONTROL | 0
IS_FRAME_WRITER | 1
IS_FRAME_READER | 0
DROP_FRAMES | 1
REPEAT_FRAMES | 1
DROP_REPEAT_USER | 0
INTERLACED_SUPPORT | 0
CONTROLLED_DROP_REPEAT | 0
DROP_INVALID_FIELDS | 0
MULTI_FRAME_DELAY | 1
IS_SYNC_MASTER | 0
IS_SYNC_SLAVE | 0
LINE_BASED_BUFFERING | 0
PRIORITIZE_FMAX | 0
USER_PACKETS_MAX_STORAGE | 0
MAX_SYMBOLS_PER_PACKET | 10
TEST_INIT | 0
ANC_BUFFER_LENGTH | 256
ACTUAL_MAX_SYM_ANC_PACKET | 12
FRAME_BUFFER_LENGTH | 2764800
NUM_BUFFERS | 3
FAMILY | CYCLONEV
AUTO_DEVICE | 5CSXFC6C6U23I7
AUTO_DEVICE_SPEEDGRADE | 7_H6
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

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