// soc_system_pcie_0_mm_interconnect_0.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 18.1 646

`timescale 1 ps / 1 ps
module soc_system_pcie_0_mm_interconnect_0 (
		input  wire        custom_reset_synchronizer_0_clock_out_clk,                            //                          custom_reset_synchronizer_0_clock_out.clk
		input  wire        pcie_hip_avmm_coreclkout_clk,                                         //                                       pcie_hip_avmm_coreclkout.clk
		input  wire        msgdma_0_reset_n_reset_bridge_in_reset_reset,                         //                         msgdma_0_reset_n_reset_bridge_in_reset.reset
		input  wire        pcie_hip_avmm_RP_Master_translator_reset_reset_bridge_in_reset_reset, // pcie_hip_avmm_RP_Master_translator_reset_reset_bridge_in_reset.reset
		input  wire [31:0] msgdma_0_mm_read_address,                                             //                                               msgdma_0_mm_read.address
		output wire        msgdma_0_mm_read_waitrequest,                                         //                                                               .waitrequest
		input  wire [6:0]  msgdma_0_mm_read_burstcount,                                          //                                                               .burstcount
		input  wire [7:0]  msgdma_0_mm_read_byteenable,                                          //                                                               .byteenable
		input  wire        msgdma_0_mm_read_read,                                                //                                                               .read
		output wire [63:0] msgdma_0_mm_read_readdata,                                            //                                                               .readdata
		output wire        msgdma_0_mm_read_readdatavalid,                                       //                                                               .readdatavalid
		input  wire [31:0] msgdma_0_mm_write_address,                                            //                                              msgdma_0_mm_write.address
		output wire        msgdma_0_mm_write_waitrequest,                                        //                                                               .waitrequest
		input  wire [6:0]  msgdma_0_mm_write_burstcount,                                         //                                                               .burstcount
		input  wire [7:0]  msgdma_0_mm_write_byteenable,                                         //                                                               .byteenable
		input  wire        msgdma_0_mm_write_write,                                              //                                                               .write
		input  wire [63:0] msgdma_0_mm_write_writedata,                                          //                                                               .writedata
		input  wire [31:0] pcie_hip_avmm_RP_Master_address,                                      //                                        pcie_hip_avmm_RP_Master.address
		output wire        pcie_hip_avmm_RP_Master_waitrequest,                                  //                                                               .waitrequest
		input  wire [6:0]  pcie_hip_avmm_RP_Master_burstcount,                                   //                                                               .burstcount
		input  wire [7:0]  pcie_hip_avmm_RP_Master_byteenable,                                   //                                                               .byteenable
		input  wire        pcie_hip_avmm_RP_Master_read,                                         //                                                               .read
		output wire [63:0] pcie_hip_avmm_RP_Master_readdata,                                     //                                                               .readdata
		output wire        pcie_hip_avmm_RP_Master_readdatavalid,                                //                                                               .readdatavalid
		input  wire        pcie_hip_avmm_RP_Master_write,                                        //                                                               .write
		input  wire [63:0] pcie_hip_avmm_RP_Master_writedata,                                    //                                                               .writedata
		output wire [15:0] pb_2_ocm_s0_address,                                                  //                                                    pb_2_ocm_s0.address
		output wire        pb_2_ocm_s0_write,                                                    //                                                               .write
		output wire        pb_2_ocm_s0_read,                                                     //                                                               .read
		input  wire [63:0] pb_2_ocm_s0_readdata,                                                 //                                                               .readdata
		output wire [63:0] pb_2_ocm_s0_writedata,                                                //                                                               .writedata
		output wire [6:0]  pb_2_ocm_s0_burstcount,                                               //                                                               .burstcount
		output wire [7:0]  pb_2_ocm_s0_byteenable,                                               //                                                               .byteenable
		input  wire        pb_2_ocm_s0_readdatavalid,                                            //                                                               .readdatavalid
		input  wire        pb_2_ocm_s0_waitrequest,                                              //                                                               .waitrequest
		output wire        pb_2_ocm_s0_debugaccess,                                              //                                                               .debugaccess
		output wire [29:0] pb_f2sdram_s0_address,                                                //                                                  pb_f2sdram_s0.address
		output wire        pb_f2sdram_s0_write,                                                  //                                                               .write
		output wire        pb_f2sdram_s0_read,                                                   //                                                               .read
		input  wire [63:0] pb_f2sdram_s0_readdata,                                               //                                                               .readdata
		output wire [63:0] pb_f2sdram_s0_writedata,                                              //                                                               .writedata
		output wire [6:0]  pb_f2sdram_s0_burstcount,                                             //                                                               .burstcount
		output wire [7:0]  pb_f2sdram_s0_byteenable,                                             //                                                               .byteenable
		input  wire        pb_f2sdram_s0_readdatavalid,                                          //                                                               .readdatavalid
		input  wire        pb_f2sdram_s0_waitrequest,                                            //                                                               .waitrequest
		output wire        pb_f2sdram_s0_debugaccess,                                            //                                                               .debugaccess
		output wire [27:0] pb_msgdma_2_txs_s0_address,                                           //                                             pb_msgdma_2_txs_s0.address
		output wire        pb_msgdma_2_txs_s0_write,                                             //                                                               .write
		output wire        pb_msgdma_2_txs_s0_read,                                              //                                                               .read
		input  wire [63:0] pb_msgdma_2_txs_s0_readdata,                                          //                                                               .readdata
		output wire [63:0] pb_msgdma_2_txs_s0_writedata,                                         //                                                               .writedata
		output wire [6:0]  pb_msgdma_2_txs_s0_burstcount,                                        //                                                               .burstcount
		output wire [7:0]  pb_msgdma_2_txs_s0_byteenable,                                        //                                                               .byteenable
		input  wire        pb_msgdma_2_txs_s0_readdatavalid,                                     //                                                               .readdatavalid
		input  wire        pb_msgdma_2_txs_s0_waitrequest,                                       //                                                               .waitrequest
		output wire        pb_msgdma_2_txs_s0_debugaccess,                                       //                                                               .debugaccess
		output wire [14:0] pb_rxm_2_msi_s0_address,                                              //                                                pb_rxm_2_msi_s0.address
		output wire        pb_rxm_2_msi_s0_write,                                                //                                                               .write
		output wire        pb_rxm_2_msi_s0_read,                                                 //                                                               .read
		input  wire [31:0] pb_rxm_2_msi_s0_readdata,                                             //                                                               .readdata
		output wire [31:0] pb_rxm_2_msi_s0_writedata,                                            //                                                               .writedata
		output wire [0:0]  pb_rxm_2_msi_s0_burstcount,                                           //                                                               .burstcount
		output wire [3:0]  pb_rxm_2_msi_s0_byteenable,                                           //                                                               .byteenable
		input  wire        pb_rxm_2_msi_s0_readdatavalid,                                        //                                                               .readdatavalid
		input  wire        pb_rxm_2_msi_s0_waitrequest,                                          //                                                               .waitrequest
		output wire        pb_rxm_2_msi_s0_debugaccess                                           //                                                               .debugaccess
	);

	wire          pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_waitrequest;   // pcie_hip_avmm_RP_Master_agent:av_waitrequest -> pcie_hip_avmm_RP_Master_translator:uav_waitrequest
	wire   [63:0] pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_readdata;      // pcie_hip_avmm_RP_Master_agent:av_readdata -> pcie_hip_avmm_RP_Master_translator:uav_readdata
	wire          pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_debugaccess;   // pcie_hip_avmm_RP_Master_translator:uav_debugaccess -> pcie_hip_avmm_RP_Master_agent:av_debugaccess
	wire   [31:0] pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_address;       // pcie_hip_avmm_RP_Master_translator:uav_address -> pcie_hip_avmm_RP_Master_agent:av_address
	wire          pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_read;          // pcie_hip_avmm_RP_Master_translator:uav_read -> pcie_hip_avmm_RP_Master_agent:av_read
	wire    [7:0] pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_byteenable;    // pcie_hip_avmm_RP_Master_translator:uav_byteenable -> pcie_hip_avmm_RP_Master_agent:av_byteenable
	wire          pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_readdatavalid; // pcie_hip_avmm_RP_Master_agent:av_readdatavalid -> pcie_hip_avmm_RP_Master_translator:uav_readdatavalid
	wire          pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_lock;          // pcie_hip_avmm_RP_Master_translator:uav_lock -> pcie_hip_avmm_RP_Master_agent:av_lock
	wire          pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_write;         // pcie_hip_avmm_RP_Master_translator:uav_write -> pcie_hip_avmm_RP_Master_agent:av_write
	wire   [63:0] pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_writedata;     // pcie_hip_avmm_RP_Master_translator:uav_writedata -> pcie_hip_avmm_RP_Master_agent:av_writedata
	wire    [9:0] pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_burstcount;    // pcie_hip_avmm_RP_Master_translator:uav_burstcount -> pcie_hip_avmm_RP_Master_agent:av_burstcount
	wire          msgdma_0_mm_read_translator_avalon_universal_master_0_waitrequest;          // msgdma_0_mm_read_agent:av_waitrequest -> msgdma_0_mm_read_translator:uav_waitrequest
	wire   [63:0] msgdma_0_mm_read_translator_avalon_universal_master_0_readdata;             // msgdma_0_mm_read_agent:av_readdata -> msgdma_0_mm_read_translator:uav_readdata
	wire          msgdma_0_mm_read_translator_avalon_universal_master_0_debugaccess;          // msgdma_0_mm_read_translator:uav_debugaccess -> msgdma_0_mm_read_agent:av_debugaccess
	wire   [31:0] msgdma_0_mm_read_translator_avalon_universal_master_0_address;              // msgdma_0_mm_read_translator:uav_address -> msgdma_0_mm_read_agent:av_address
	wire          msgdma_0_mm_read_translator_avalon_universal_master_0_read;                 // msgdma_0_mm_read_translator:uav_read -> msgdma_0_mm_read_agent:av_read
	wire    [7:0] msgdma_0_mm_read_translator_avalon_universal_master_0_byteenable;           // msgdma_0_mm_read_translator:uav_byteenable -> msgdma_0_mm_read_agent:av_byteenable
	wire          msgdma_0_mm_read_translator_avalon_universal_master_0_readdatavalid;        // msgdma_0_mm_read_agent:av_readdatavalid -> msgdma_0_mm_read_translator:uav_readdatavalid
	wire          msgdma_0_mm_read_translator_avalon_universal_master_0_lock;                 // msgdma_0_mm_read_translator:uav_lock -> msgdma_0_mm_read_agent:av_lock
	wire          msgdma_0_mm_read_translator_avalon_universal_master_0_write;                // msgdma_0_mm_read_translator:uav_write -> msgdma_0_mm_read_agent:av_write
	wire   [63:0] msgdma_0_mm_read_translator_avalon_universal_master_0_writedata;            // msgdma_0_mm_read_translator:uav_writedata -> msgdma_0_mm_read_agent:av_writedata
	wire    [9:0] msgdma_0_mm_read_translator_avalon_universal_master_0_burstcount;           // msgdma_0_mm_read_translator:uav_burstcount -> msgdma_0_mm_read_agent:av_burstcount
	wire          msgdma_0_mm_write_translator_avalon_universal_master_0_waitrequest;         // msgdma_0_mm_write_agent:av_waitrequest -> msgdma_0_mm_write_translator:uav_waitrequest
	wire   [63:0] msgdma_0_mm_write_translator_avalon_universal_master_0_readdata;            // msgdma_0_mm_write_agent:av_readdata -> msgdma_0_mm_write_translator:uav_readdata
	wire          msgdma_0_mm_write_translator_avalon_universal_master_0_debugaccess;         // msgdma_0_mm_write_translator:uav_debugaccess -> msgdma_0_mm_write_agent:av_debugaccess
	wire   [31:0] msgdma_0_mm_write_translator_avalon_universal_master_0_address;             // msgdma_0_mm_write_translator:uav_address -> msgdma_0_mm_write_agent:av_address
	wire          msgdma_0_mm_write_translator_avalon_universal_master_0_read;                // msgdma_0_mm_write_translator:uav_read -> msgdma_0_mm_write_agent:av_read
	wire    [7:0] msgdma_0_mm_write_translator_avalon_universal_master_0_byteenable;          // msgdma_0_mm_write_translator:uav_byteenable -> msgdma_0_mm_write_agent:av_byteenable
	wire          msgdma_0_mm_write_translator_avalon_universal_master_0_readdatavalid;       // msgdma_0_mm_write_agent:av_readdatavalid -> msgdma_0_mm_write_translator:uav_readdatavalid
	wire          msgdma_0_mm_write_translator_avalon_universal_master_0_lock;                // msgdma_0_mm_write_translator:uav_lock -> msgdma_0_mm_write_agent:av_lock
	wire          msgdma_0_mm_write_translator_avalon_universal_master_0_write;               // msgdma_0_mm_write_translator:uav_write -> msgdma_0_mm_write_agent:av_write
	wire   [63:0] msgdma_0_mm_write_translator_avalon_universal_master_0_writedata;           // msgdma_0_mm_write_translator:uav_writedata -> msgdma_0_mm_write_agent:av_writedata
	wire    [9:0] msgdma_0_mm_write_translator_avalon_universal_master_0_burstcount;          // msgdma_0_mm_write_translator:uav_burstcount -> msgdma_0_mm_write_agent:av_burstcount
	wire          rsp_mux_002_src_valid;                                                      // rsp_mux_002:src_valid -> msgdma_0_mm_write_agent:rp_valid
	wire  [146:0] rsp_mux_002_src_data;                                                       // rsp_mux_002:src_data -> msgdma_0_mm_write_agent:rp_data
	wire          rsp_mux_002_src_ready;                                                      // msgdma_0_mm_write_agent:rp_ready -> rsp_mux_002:src_ready
	wire    [3:0] rsp_mux_002_src_channel;                                                    // rsp_mux_002:src_channel -> msgdma_0_mm_write_agent:rp_channel
	wire          rsp_mux_002_src_startofpacket;                                              // rsp_mux_002:src_startofpacket -> msgdma_0_mm_write_agent:rp_startofpacket
	wire          rsp_mux_002_src_endofpacket;                                                // rsp_mux_002:src_endofpacket -> msgdma_0_mm_write_agent:rp_endofpacket
	wire   [31:0] pb_rxm_2_msi_s0_agent_m0_readdata;                                          // pb_rxm_2_msi_s0_translator:uav_readdata -> pb_rxm_2_msi_s0_agent:m0_readdata
	wire          pb_rxm_2_msi_s0_agent_m0_waitrequest;                                       // pb_rxm_2_msi_s0_translator:uav_waitrequest -> pb_rxm_2_msi_s0_agent:m0_waitrequest
	wire          pb_rxm_2_msi_s0_agent_m0_debugaccess;                                       // pb_rxm_2_msi_s0_agent:m0_debugaccess -> pb_rxm_2_msi_s0_translator:uav_debugaccess
	wire   [31:0] pb_rxm_2_msi_s0_agent_m0_address;                                           // pb_rxm_2_msi_s0_agent:m0_address -> pb_rxm_2_msi_s0_translator:uav_address
	wire    [3:0] pb_rxm_2_msi_s0_agent_m0_byteenable;                                        // pb_rxm_2_msi_s0_agent:m0_byteenable -> pb_rxm_2_msi_s0_translator:uav_byteenable
	wire          pb_rxm_2_msi_s0_agent_m0_read;                                              // pb_rxm_2_msi_s0_agent:m0_read -> pb_rxm_2_msi_s0_translator:uav_read
	wire          pb_rxm_2_msi_s0_agent_m0_readdatavalid;                                     // pb_rxm_2_msi_s0_translator:uav_readdatavalid -> pb_rxm_2_msi_s0_agent:m0_readdatavalid
	wire          pb_rxm_2_msi_s0_agent_m0_lock;                                              // pb_rxm_2_msi_s0_agent:m0_lock -> pb_rxm_2_msi_s0_translator:uav_lock
	wire   [31:0] pb_rxm_2_msi_s0_agent_m0_writedata;                                         // pb_rxm_2_msi_s0_agent:m0_writedata -> pb_rxm_2_msi_s0_translator:uav_writedata
	wire          pb_rxm_2_msi_s0_agent_m0_write;                                             // pb_rxm_2_msi_s0_agent:m0_write -> pb_rxm_2_msi_s0_translator:uav_write
	wire    [2:0] pb_rxm_2_msi_s0_agent_m0_burstcount;                                        // pb_rxm_2_msi_s0_agent:m0_burstcount -> pb_rxm_2_msi_s0_translator:uav_burstcount
	wire          pb_rxm_2_msi_s0_agent_rf_source_valid;                                      // pb_rxm_2_msi_s0_agent:rf_source_valid -> pb_rxm_2_msi_s0_agent_rsp_fifo:in_valid
	wire  [111:0] pb_rxm_2_msi_s0_agent_rf_source_data;                                       // pb_rxm_2_msi_s0_agent:rf_source_data -> pb_rxm_2_msi_s0_agent_rsp_fifo:in_data
	wire          pb_rxm_2_msi_s0_agent_rf_source_ready;                                      // pb_rxm_2_msi_s0_agent_rsp_fifo:in_ready -> pb_rxm_2_msi_s0_agent:rf_source_ready
	wire          pb_rxm_2_msi_s0_agent_rf_source_startofpacket;                              // pb_rxm_2_msi_s0_agent:rf_source_startofpacket -> pb_rxm_2_msi_s0_agent_rsp_fifo:in_startofpacket
	wire          pb_rxm_2_msi_s0_agent_rf_source_endofpacket;                                // pb_rxm_2_msi_s0_agent:rf_source_endofpacket -> pb_rxm_2_msi_s0_agent_rsp_fifo:in_endofpacket
	wire          pb_rxm_2_msi_s0_agent_rsp_fifo_out_valid;                                   // pb_rxm_2_msi_s0_agent_rsp_fifo:out_valid -> pb_rxm_2_msi_s0_agent:rf_sink_valid
	wire  [111:0] pb_rxm_2_msi_s0_agent_rsp_fifo_out_data;                                    // pb_rxm_2_msi_s0_agent_rsp_fifo:out_data -> pb_rxm_2_msi_s0_agent:rf_sink_data
	wire          pb_rxm_2_msi_s0_agent_rsp_fifo_out_ready;                                   // pb_rxm_2_msi_s0_agent:rf_sink_ready -> pb_rxm_2_msi_s0_agent_rsp_fifo:out_ready
	wire          pb_rxm_2_msi_s0_agent_rsp_fifo_out_startofpacket;                           // pb_rxm_2_msi_s0_agent_rsp_fifo:out_startofpacket -> pb_rxm_2_msi_s0_agent:rf_sink_startofpacket
	wire          pb_rxm_2_msi_s0_agent_rsp_fifo_out_endofpacket;                             // pb_rxm_2_msi_s0_agent_rsp_fifo:out_endofpacket -> pb_rxm_2_msi_s0_agent:rf_sink_endofpacket
	wire          pb_rxm_2_msi_s0_agent_rdata_fifo_src_valid;                                 // pb_rxm_2_msi_s0_agent:rdata_fifo_src_valid -> pb_rxm_2_msi_s0_agent_rdata_fifo:in_valid
	wire   [33:0] pb_rxm_2_msi_s0_agent_rdata_fifo_src_data;                                  // pb_rxm_2_msi_s0_agent:rdata_fifo_src_data -> pb_rxm_2_msi_s0_agent_rdata_fifo:in_data
	wire          pb_rxm_2_msi_s0_agent_rdata_fifo_src_ready;                                 // pb_rxm_2_msi_s0_agent_rdata_fifo:in_ready -> pb_rxm_2_msi_s0_agent:rdata_fifo_src_ready
	wire   [63:0] pb_2_ocm_s0_agent_m0_readdata;                                              // pb_2_ocm_s0_translator:uav_readdata -> pb_2_ocm_s0_agent:m0_readdata
	wire          pb_2_ocm_s0_agent_m0_waitrequest;                                           // pb_2_ocm_s0_translator:uav_waitrequest -> pb_2_ocm_s0_agent:m0_waitrequest
	wire          pb_2_ocm_s0_agent_m0_debugaccess;                                           // pb_2_ocm_s0_agent:m0_debugaccess -> pb_2_ocm_s0_translator:uav_debugaccess
	wire   [31:0] pb_2_ocm_s0_agent_m0_address;                                               // pb_2_ocm_s0_agent:m0_address -> pb_2_ocm_s0_translator:uav_address
	wire    [7:0] pb_2_ocm_s0_agent_m0_byteenable;                                            // pb_2_ocm_s0_agent:m0_byteenable -> pb_2_ocm_s0_translator:uav_byteenable
	wire          pb_2_ocm_s0_agent_m0_read;                                                  // pb_2_ocm_s0_agent:m0_read -> pb_2_ocm_s0_translator:uav_read
	wire          pb_2_ocm_s0_agent_m0_readdatavalid;                                         // pb_2_ocm_s0_translator:uav_readdatavalid -> pb_2_ocm_s0_agent:m0_readdatavalid
	wire          pb_2_ocm_s0_agent_m0_lock;                                                  // pb_2_ocm_s0_agent:m0_lock -> pb_2_ocm_s0_translator:uav_lock
	wire   [63:0] pb_2_ocm_s0_agent_m0_writedata;                                             // pb_2_ocm_s0_agent:m0_writedata -> pb_2_ocm_s0_translator:uav_writedata
	wire          pb_2_ocm_s0_agent_m0_write;                                                 // pb_2_ocm_s0_agent:m0_write -> pb_2_ocm_s0_translator:uav_write
	wire    [9:0] pb_2_ocm_s0_agent_m0_burstcount;                                            // pb_2_ocm_s0_agent:m0_burstcount -> pb_2_ocm_s0_translator:uav_burstcount
	wire          pb_2_ocm_s0_agent_rf_source_valid;                                          // pb_2_ocm_s0_agent:rf_source_valid -> pb_2_ocm_s0_agent_rsp_fifo:in_valid
	wire  [147:0] pb_2_ocm_s0_agent_rf_source_data;                                           // pb_2_ocm_s0_agent:rf_source_data -> pb_2_ocm_s0_agent_rsp_fifo:in_data
	wire          pb_2_ocm_s0_agent_rf_source_ready;                                          // pb_2_ocm_s0_agent_rsp_fifo:in_ready -> pb_2_ocm_s0_agent:rf_source_ready
	wire          pb_2_ocm_s0_agent_rf_source_startofpacket;                                  // pb_2_ocm_s0_agent:rf_source_startofpacket -> pb_2_ocm_s0_agent_rsp_fifo:in_startofpacket
	wire          pb_2_ocm_s0_agent_rf_source_endofpacket;                                    // pb_2_ocm_s0_agent:rf_source_endofpacket -> pb_2_ocm_s0_agent_rsp_fifo:in_endofpacket
	wire          pb_2_ocm_s0_agent_rsp_fifo_out_valid;                                       // pb_2_ocm_s0_agent_rsp_fifo:out_valid -> pb_2_ocm_s0_agent:rf_sink_valid
	wire  [147:0] pb_2_ocm_s0_agent_rsp_fifo_out_data;                                        // pb_2_ocm_s0_agent_rsp_fifo:out_data -> pb_2_ocm_s0_agent:rf_sink_data
	wire          pb_2_ocm_s0_agent_rsp_fifo_out_ready;                                       // pb_2_ocm_s0_agent:rf_sink_ready -> pb_2_ocm_s0_agent_rsp_fifo:out_ready
	wire          pb_2_ocm_s0_agent_rsp_fifo_out_startofpacket;                               // pb_2_ocm_s0_agent_rsp_fifo:out_startofpacket -> pb_2_ocm_s0_agent:rf_sink_startofpacket
	wire          pb_2_ocm_s0_agent_rsp_fifo_out_endofpacket;                                 // pb_2_ocm_s0_agent_rsp_fifo:out_endofpacket -> pb_2_ocm_s0_agent:rf_sink_endofpacket
	wire          pb_2_ocm_s0_agent_rdata_fifo_src_valid;                                     // pb_2_ocm_s0_agent:rdata_fifo_src_valid -> pb_2_ocm_s0_agent_rdata_fifo:in_valid
	wire   [65:0] pb_2_ocm_s0_agent_rdata_fifo_src_data;                                      // pb_2_ocm_s0_agent:rdata_fifo_src_data -> pb_2_ocm_s0_agent_rdata_fifo:in_data
	wire          pb_2_ocm_s0_agent_rdata_fifo_src_ready;                                     // pb_2_ocm_s0_agent_rdata_fifo:in_ready -> pb_2_ocm_s0_agent:rdata_fifo_src_ready
	wire   [63:0] pb_f2sdram_s0_agent_m0_readdata;                                            // pb_f2sdram_s0_translator:uav_readdata -> pb_f2sdram_s0_agent:m0_readdata
	wire          pb_f2sdram_s0_agent_m0_waitrequest;                                         // pb_f2sdram_s0_translator:uav_waitrequest -> pb_f2sdram_s0_agent:m0_waitrequest
	wire          pb_f2sdram_s0_agent_m0_debugaccess;                                         // pb_f2sdram_s0_agent:m0_debugaccess -> pb_f2sdram_s0_translator:uav_debugaccess
	wire   [31:0] pb_f2sdram_s0_agent_m0_address;                                             // pb_f2sdram_s0_agent:m0_address -> pb_f2sdram_s0_translator:uav_address
	wire    [7:0] pb_f2sdram_s0_agent_m0_byteenable;                                          // pb_f2sdram_s0_agent:m0_byteenable -> pb_f2sdram_s0_translator:uav_byteenable
	wire          pb_f2sdram_s0_agent_m0_read;                                                // pb_f2sdram_s0_agent:m0_read -> pb_f2sdram_s0_translator:uav_read
	wire          pb_f2sdram_s0_agent_m0_readdatavalid;                                       // pb_f2sdram_s0_translator:uav_readdatavalid -> pb_f2sdram_s0_agent:m0_readdatavalid
	wire          pb_f2sdram_s0_agent_m0_lock;                                                // pb_f2sdram_s0_agent:m0_lock -> pb_f2sdram_s0_translator:uav_lock
	wire   [63:0] pb_f2sdram_s0_agent_m0_writedata;                                           // pb_f2sdram_s0_agent:m0_writedata -> pb_f2sdram_s0_translator:uav_writedata
	wire          pb_f2sdram_s0_agent_m0_write;                                               // pb_f2sdram_s0_agent:m0_write -> pb_f2sdram_s0_translator:uav_write
	wire    [9:0] pb_f2sdram_s0_agent_m0_burstcount;                                          // pb_f2sdram_s0_agent:m0_burstcount -> pb_f2sdram_s0_translator:uav_burstcount
	wire          pb_f2sdram_s0_agent_rf_source_valid;                                        // pb_f2sdram_s0_agent:rf_source_valid -> pb_f2sdram_s0_agent_rsp_fifo:in_valid
	wire  [147:0] pb_f2sdram_s0_agent_rf_source_data;                                         // pb_f2sdram_s0_agent:rf_source_data -> pb_f2sdram_s0_agent_rsp_fifo:in_data
	wire          pb_f2sdram_s0_agent_rf_source_ready;                                        // pb_f2sdram_s0_agent_rsp_fifo:in_ready -> pb_f2sdram_s0_agent:rf_source_ready
	wire          pb_f2sdram_s0_agent_rf_source_startofpacket;                                // pb_f2sdram_s0_agent:rf_source_startofpacket -> pb_f2sdram_s0_agent_rsp_fifo:in_startofpacket
	wire          pb_f2sdram_s0_agent_rf_source_endofpacket;                                  // pb_f2sdram_s0_agent:rf_source_endofpacket -> pb_f2sdram_s0_agent_rsp_fifo:in_endofpacket
	wire          pb_f2sdram_s0_agent_rsp_fifo_out_valid;                                     // pb_f2sdram_s0_agent_rsp_fifo:out_valid -> pb_f2sdram_s0_agent:rf_sink_valid
	wire  [147:0] pb_f2sdram_s0_agent_rsp_fifo_out_data;                                      // pb_f2sdram_s0_agent_rsp_fifo:out_data -> pb_f2sdram_s0_agent:rf_sink_data
	wire          pb_f2sdram_s0_agent_rsp_fifo_out_ready;                                     // pb_f2sdram_s0_agent:rf_sink_ready -> pb_f2sdram_s0_agent_rsp_fifo:out_ready
	wire          pb_f2sdram_s0_agent_rsp_fifo_out_startofpacket;                             // pb_f2sdram_s0_agent_rsp_fifo:out_startofpacket -> pb_f2sdram_s0_agent:rf_sink_startofpacket
	wire          pb_f2sdram_s0_agent_rsp_fifo_out_endofpacket;                               // pb_f2sdram_s0_agent_rsp_fifo:out_endofpacket -> pb_f2sdram_s0_agent:rf_sink_endofpacket
	wire          pb_f2sdram_s0_agent_rdata_fifo_src_valid;                                   // pb_f2sdram_s0_agent:rdata_fifo_src_valid -> pb_f2sdram_s0_agent_rdata_fifo:in_valid
	wire   [65:0] pb_f2sdram_s0_agent_rdata_fifo_src_data;                                    // pb_f2sdram_s0_agent:rdata_fifo_src_data -> pb_f2sdram_s0_agent_rdata_fifo:in_data
	wire          pb_f2sdram_s0_agent_rdata_fifo_src_ready;                                   // pb_f2sdram_s0_agent_rdata_fifo:in_ready -> pb_f2sdram_s0_agent:rdata_fifo_src_ready
	wire   [63:0] pb_msgdma_2_txs_s0_agent_m0_readdata;                                       // pb_msgdma_2_txs_s0_translator:uav_readdata -> pb_msgdma_2_txs_s0_agent:m0_readdata
	wire          pb_msgdma_2_txs_s0_agent_m0_waitrequest;                                    // pb_msgdma_2_txs_s0_translator:uav_waitrequest -> pb_msgdma_2_txs_s0_agent:m0_waitrequest
	wire          pb_msgdma_2_txs_s0_agent_m0_debugaccess;                                    // pb_msgdma_2_txs_s0_agent:m0_debugaccess -> pb_msgdma_2_txs_s0_translator:uav_debugaccess
	wire   [31:0] pb_msgdma_2_txs_s0_agent_m0_address;                                        // pb_msgdma_2_txs_s0_agent:m0_address -> pb_msgdma_2_txs_s0_translator:uav_address
	wire    [7:0] pb_msgdma_2_txs_s0_agent_m0_byteenable;                                     // pb_msgdma_2_txs_s0_agent:m0_byteenable -> pb_msgdma_2_txs_s0_translator:uav_byteenable
	wire          pb_msgdma_2_txs_s0_agent_m0_read;                                           // pb_msgdma_2_txs_s0_agent:m0_read -> pb_msgdma_2_txs_s0_translator:uav_read
	wire          pb_msgdma_2_txs_s0_agent_m0_readdatavalid;                                  // pb_msgdma_2_txs_s0_translator:uav_readdatavalid -> pb_msgdma_2_txs_s0_agent:m0_readdatavalid
	wire          pb_msgdma_2_txs_s0_agent_m0_lock;                                           // pb_msgdma_2_txs_s0_agent:m0_lock -> pb_msgdma_2_txs_s0_translator:uav_lock
	wire   [63:0] pb_msgdma_2_txs_s0_agent_m0_writedata;                                      // pb_msgdma_2_txs_s0_agent:m0_writedata -> pb_msgdma_2_txs_s0_translator:uav_writedata
	wire          pb_msgdma_2_txs_s0_agent_m0_write;                                          // pb_msgdma_2_txs_s0_agent:m0_write -> pb_msgdma_2_txs_s0_translator:uav_write
	wire    [9:0] pb_msgdma_2_txs_s0_agent_m0_burstcount;                                     // pb_msgdma_2_txs_s0_agent:m0_burstcount -> pb_msgdma_2_txs_s0_translator:uav_burstcount
	wire          pb_msgdma_2_txs_s0_agent_rf_source_valid;                                   // pb_msgdma_2_txs_s0_agent:rf_source_valid -> pb_msgdma_2_txs_s0_agent_rsp_fifo:in_valid
	wire  [147:0] pb_msgdma_2_txs_s0_agent_rf_source_data;                                    // pb_msgdma_2_txs_s0_agent:rf_source_data -> pb_msgdma_2_txs_s0_agent_rsp_fifo:in_data
	wire          pb_msgdma_2_txs_s0_agent_rf_source_ready;                                   // pb_msgdma_2_txs_s0_agent_rsp_fifo:in_ready -> pb_msgdma_2_txs_s0_agent:rf_source_ready
	wire          pb_msgdma_2_txs_s0_agent_rf_source_startofpacket;                           // pb_msgdma_2_txs_s0_agent:rf_source_startofpacket -> pb_msgdma_2_txs_s0_agent_rsp_fifo:in_startofpacket
	wire          pb_msgdma_2_txs_s0_agent_rf_source_endofpacket;                             // pb_msgdma_2_txs_s0_agent:rf_source_endofpacket -> pb_msgdma_2_txs_s0_agent_rsp_fifo:in_endofpacket
	wire          pb_msgdma_2_txs_s0_agent_rsp_fifo_out_valid;                                // pb_msgdma_2_txs_s0_agent_rsp_fifo:out_valid -> pb_msgdma_2_txs_s0_agent:rf_sink_valid
	wire  [147:0] pb_msgdma_2_txs_s0_agent_rsp_fifo_out_data;                                 // pb_msgdma_2_txs_s0_agent_rsp_fifo:out_data -> pb_msgdma_2_txs_s0_agent:rf_sink_data
	wire          pb_msgdma_2_txs_s0_agent_rsp_fifo_out_ready;                                // pb_msgdma_2_txs_s0_agent:rf_sink_ready -> pb_msgdma_2_txs_s0_agent_rsp_fifo:out_ready
	wire          pb_msgdma_2_txs_s0_agent_rsp_fifo_out_startofpacket;                        // pb_msgdma_2_txs_s0_agent_rsp_fifo:out_startofpacket -> pb_msgdma_2_txs_s0_agent:rf_sink_startofpacket
	wire          pb_msgdma_2_txs_s0_agent_rsp_fifo_out_endofpacket;                          // pb_msgdma_2_txs_s0_agent_rsp_fifo:out_endofpacket -> pb_msgdma_2_txs_s0_agent:rf_sink_endofpacket
	wire          pb_msgdma_2_txs_s0_agent_rdata_fifo_src_valid;                              // pb_msgdma_2_txs_s0_agent:rdata_fifo_src_valid -> pb_msgdma_2_txs_s0_agent_rdata_fifo:in_valid
	wire   [65:0] pb_msgdma_2_txs_s0_agent_rdata_fifo_src_data;                               // pb_msgdma_2_txs_s0_agent:rdata_fifo_src_data -> pb_msgdma_2_txs_s0_agent_rdata_fifo:in_data
	wire          pb_msgdma_2_txs_s0_agent_rdata_fifo_src_ready;                              // pb_msgdma_2_txs_s0_agent_rdata_fifo:in_ready -> pb_msgdma_2_txs_s0_agent:rdata_fifo_src_ready
	wire          router_002_src_valid;                                                       // router_002:src_valid -> cmd_demux_002:sink_valid
	wire  [146:0] router_002_src_data;                                                        // router_002:src_data -> cmd_demux_002:sink_data
	wire          router_002_src_ready;                                                       // cmd_demux_002:sink_ready -> router_002:src_ready
	wire    [3:0] router_002_src_channel;                                                     // router_002:src_channel -> cmd_demux_002:sink_channel
	wire          router_002_src_startofpacket;                                               // router_002:src_startofpacket -> cmd_demux_002:sink_startofpacket
	wire          router_002_src_endofpacket;                                                 // router_002:src_endofpacket -> cmd_demux_002:sink_endofpacket
	wire          router_004_src_valid;                                                       // router_004:src_valid -> rsp_demux_001:sink_valid
	wire  [146:0] router_004_src_data;                                                        // router_004:src_data -> rsp_demux_001:sink_data
	wire          router_004_src_ready;                                                       // rsp_demux_001:sink_ready -> router_004:src_ready
	wire    [3:0] router_004_src_channel;                                                     // router_004:src_channel -> rsp_demux_001:sink_channel
	wire          router_004_src_startofpacket;                                               // router_004:src_startofpacket -> rsp_demux_001:sink_startofpacket
	wire          router_004_src_endofpacket;                                                 // router_004:src_endofpacket -> rsp_demux_001:sink_endofpacket
	wire          router_005_src_valid;                                                       // router_005:src_valid -> rsp_demux_002:sink_valid
	wire  [146:0] router_005_src_data;                                                        // router_005:src_data -> rsp_demux_002:sink_data
	wire          router_005_src_ready;                                                       // rsp_demux_002:sink_ready -> router_005:src_ready
	wire    [3:0] router_005_src_channel;                                                     // router_005:src_channel -> rsp_demux_002:sink_channel
	wire          router_005_src_startofpacket;                                               // router_005:src_startofpacket -> rsp_demux_002:sink_startofpacket
	wire          router_005_src_endofpacket;                                                 // router_005:src_endofpacket -> rsp_demux_002:sink_endofpacket
	wire          router_006_src_valid;                                                       // router_006:src_valid -> rsp_demux_003:sink_valid
	wire  [146:0] router_006_src_data;                                                        // router_006:src_data -> rsp_demux_003:sink_data
	wire          router_006_src_ready;                                                       // rsp_demux_003:sink_ready -> router_006:src_ready
	wire    [3:0] router_006_src_channel;                                                     // router_006:src_channel -> rsp_demux_003:sink_channel
	wire          router_006_src_startofpacket;                                               // router_006:src_startofpacket -> rsp_demux_003:sink_startofpacket
	wire          router_006_src_endofpacket;                                                 // router_006:src_endofpacket -> rsp_demux_003:sink_endofpacket
	wire          router_src_valid;                                                           // router:src_valid -> pcie_hip_avmm_RP_Master_limiter:cmd_sink_valid
	wire  [146:0] router_src_data;                                                            // router:src_data -> pcie_hip_avmm_RP_Master_limiter:cmd_sink_data
	wire          router_src_ready;                                                           // pcie_hip_avmm_RP_Master_limiter:cmd_sink_ready -> router:src_ready
	wire    [3:0] router_src_channel;                                                         // router:src_channel -> pcie_hip_avmm_RP_Master_limiter:cmd_sink_channel
	wire          router_src_startofpacket;                                                   // router:src_startofpacket -> pcie_hip_avmm_RP_Master_limiter:cmd_sink_startofpacket
	wire          router_src_endofpacket;                                                     // router:src_endofpacket -> pcie_hip_avmm_RP_Master_limiter:cmd_sink_endofpacket
	wire          pcie_hip_avmm_rp_master_limiter_rsp_src_valid;                              // pcie_hip_avmm_RP_Master_limiter:rsp_src_valid -> pcie_hip_avmm_RP_Master_agent:rp_valid
	wire  [146:0] pcie_hip_avmm_rp_master_limiter_rsp_src_data;                               // pcie_hip_avmm_RP_Master_limiter:rsp_src_data -> pcie_hip_avmm_RP_Master_agent:rp_data
	wire          pcie_hip_avmm_rp_master_limiter_rsp_src_ready;                              // pcie_hip_avmm_RP_Master_agent:rp_ready -> pcie_hip_avmm_RP_Master_limiter:rsp_src_ready
	wire    [3:0] pcie_hip_avmm_rp_master_limiter_rsp_src_channel;                            // pcie_hip_avmm_RP_Master_limiter:rsp_src_channel -> pcie_hip_avmm_RP_Master_agent:rp_channel
	wire          pcie_hip_avmm_rp_master_limiter_rsp_src_startofpacket;                      // pcie_hip_avmm_RP_Master_limiter:rsp_src_startofpacket -> pcie_hip_avmm_RP_Master_agent:rp_startofpacket
	wire          pcie_hip_avmm_rp_master_limiter_rsp_src_endofpacket;                        // pcie_hip_avmm_RP_Master_limiter:rsp_src_endofpacket -> pcie_hip_avmm_RP_Master_agent:rp_endofpacket
	wire          router_001_src_valid;                                                       // router_001:src_valid -> msgdma_0_mm_read_limiter:cmd_sink_valid
	wire  [146:0] router_001_src_data;                                                        // router_001:src_data -> msgdma_0_mm_read_limiter:cmd_sink_data
	wire          router_001_src_ready;                                                       // msgdma_0_mm_read_limiter:cmd_sink_ready -> router_001:src_ready
	wire    [3:0] router_001_src_channel;                                                     // router_001:src_channel -> msgdma_0_mm_read_limiter:cmd_sink_channel
	wire          router_001_src_startofpacket;                                               // router_001:src_startofpacket -> msgdma_0_mm_read_limiter:cmd_sink_startofpacket
	wire          router_001_src_endofpacket;                                                 // router_001:src_endofpacket -> msgdma_0_mm_read_limiter:cmd_sink_endofpacket
	wire          msgdma_0_mm_read_limiter_rsp_src_valid;                                     // msgdma_0_mm_read_limiter:rsp_src_valid -> msgdma_0_mm_read_agent:rp_valid
	wire  [146:0] msgdma_0_mm_read_limiter_rsp_src_data;                                      // msgdma_0_mm_read_limiter:rsp_src_data -> msgdma_0_mm_read_agent:rp_data
	wire          msgdma_0_mm_read_limiter_rsp_src_ready;                                     // msgdma_0_mm_read_agent:rp_ready -> msgdma_0_mm_read_limiter:rsp_src_ready
	wire    [3:0] msgdma_0_mm_read_limiter_rsp_src_channel;                                   // msgdma_0_mm_read_limiter:rsp_src_channel -> msgdma_0_mm_read_agent:rp_channel
	wire          msgdma_0_mm_read_limiter_rsp_src_startofpacket;                             // msgdma_0_mm_read_limiter:rsp_src_startofpacket -> msgdma_0_mm_read_agent:rp_startofpacket
	wire          msgdma_0_mm_read_limiter_rsp_src_endofpacket;                               // msgdma_0_mm_read_limiter:rsp_src_endofpacket -> msgdma_0_mm_read_agent:rp_endofpacket
	wire          cmd_demux_001_src0_valid;                                                   // cmd_demux_001:src0_valid -> cmd_mux_001:sink1_valid
	wire  [146:0] cmd_demux_001_src0_data;                                                    // cmd_demux_001:src0_data -> cmd_mux_001:sink1_data
	wire          cmd_demux_001_src0_ready;                                                   // cmd_mux_001:sink1_ready -> cmd_demux_001:src0_ready
	wire    [3:0] cmd_demux_001_src0_channel;                                                 // cmd_demux_001:src0_channel -> cmd_mux_001:sink1_channel
	wire          cmd_demux_001_src0_startofpacket;                                           // cmd_demux_001:src0_startofpacket -> cmd_mux_001:sink1_startofpacket
	wire          cmd_demux_001_src0_endofpacket;                                             // cmd_demux_001:src0_endofpacket -> cmd_mux_001:sink1_endofpacket
	wire          cmd_demux_001_src1_valid;                                                   // cmd_demux_001:src1_valid -> cmd_mux_002:sink1_valid
	wire  [146:0] cmd_demux_001_src1_data;                                                    // cmd_demux_001:src1_data -> cmd_mux_002:sink1_data
	wire          cmd_demux_001_src1_ready;                                                   // cmd_mux_002:sink1_ready -> cmd_demux_001:src1_ready
	wire    [3:0] cmd_demux_001_src1_channel;                                                 // cmd_demux_001:src1_channel -> cmd_mux_002:sink1_channel
	wire          cmd_demux_001_src1_startofpacket;                                           // cmd_demux_001:src1_startofpacket -> cmd_mux_002:sink1_startofpacket
	wire          cmd_demux_001_src1_endofpacket;                                             // cmd_demux_001:src1_endofpacket -> cmd_mux_002:sink1_endofpacket
	wire          cmd_demux_001_src2_valid;                                                   // cmd_demux_001:src2_valid -> cmd_mux_003:sink0_valid
	wire  [146:0] cmd_demux_001_src2_data;                                                    // cmd_demux_001:src2_data -> cmd_mux_003:sink0_data
	wire          cmd_demux_001_src2_ready;                                                   // cmd_mux_003:sink0_ready -> cmd_demux_001:src2_ready
	wire    [3:0] cmd_demux_001_src2_channel;                                                 // cmd_demux_001:src2_channel -> cmd_mux_003:sink0_channel
	wire          cmd_demux_001_src2_startofpacket;                                           // cmd_demux_001:src2_startofpacket -> cmd_mux_003:sink0_startofpacket
	wire          cmd_demux_001_src2_endofpacket;                                             // cmd_demux_001:src2_endofpacket -> cmd_mux_003:sink0_endofpacket
	wire          cmd_demux_002_src1_valid;                                                   // cmd_demux_002:src1_valid -> cmd_mux_002:sink2_valid
	wire  [146:0] cmd_demux_002_src1_data;                                                    // cmd_demux_002:src1_data -> cmd_mux_002:sink2_data
	wire          cmd_demux_002_src1_ready;                                                   // cmd_mux_002:sink2_ready -> cmd_demux_002:src1_ready
	wire    [3:0] cmd_demux_002_src1_channel;                                                 // cmd_demux_002:src1_channel -> cmd_mux_002:sink2_channel
	wire          cmd_demux_002_src1_startofpacket;                                           // cmd_demux_002:src1_startofpacket -> cmd_mux_002:sink2_startofpacket
	wire          cmd_demux_002_src1_endofpacket;                                             // cmd_demux_002:src1_endofpacket -> cmd_mux_002:sink2_endofpacket
	wire          cmd_demux_002_src2_valid;                                                   // cmd_demux_002:src2_valid -> cmd_mux_003:sink1_valid
	wire  [146:0] cmd_demux_002_src2_data;                                                    // cmd_demux_002:src2_data -> cmd_mux_003:sink1_data
	wire          cmd_demux_002_src2_ready;                                                   // cmd_mux_003:sink1_ready -> cmd_demux_002:src2_ready
	wire    [3:0] cmd_demux_002_src2_channel;                                                 // cmd_demux_002:src2_channel -> cmd_mux_003:sink1_channel
	wire          cmd_demux_002_src2_startofpacket;                                           // cmd_demux_002:src2_startofpacket -> cmd_mux_003:sink1_startofpacket
	wire          cmd_demux_002_src2_endofpacket;                                             // cmd_demux_002:src2_endofpacket -> cmd_mux_003:sink1_endofpacket
	wire          rsp_demux_001_src1_valid;                                                   // rsp_demux_001:src1_valid -> rsp_mux_001:sink0_valid
	wire  [146:0] rsp_demux_001_src1_data;                                                    // rsp_demux_001:src1_data -> rsp_mux_001:sink0_data
	wire          rsp_demux_001_src1_ready;                                                   // rsp_mux_001:sink0_ready -> rsp_demux_001:src1_ready
	wire    [3:0] rsp_demux_001_src1_channel;                                                 // rsp_demux_001:src1_channel -> rsp_mux_001:sink0_channel
	wire          rsp_demux_001_src1_startofpacket;                                           // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
	wire          rsp_demux_001_src1_endofpacket;                                             // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
	wire          rsp_demux_001_src2_valid;                                                   // rsp_demux_001:src2_valid -> rsp_mux_002:sink0_valid
	wire  [146:0] rsp_demux_001_src2_data;                                                    // rsp_demux_001:src2_data -> rsp_mux_002:sink0_data
	wire          rsp_demux_001_src2_ready;                                                   // rsp_mux_002:sink0_ready -> rsp_demux_001:src2_ready
	wire    [3:0] rsp_demux_001_src2_channel;                                                 // rsp_demux_001:src2_channel -> rsp_mux_002:sink0_channel
	wire          rsp_demux_001_src2_startofpacket;                                           // rsp_demux_001:src2_startofpacket -> rsp_mux_002:sink0_startofpacket
	wire          rsp_demux_001_src2_endofpacket;                                             // rsp_demux_001:src2_endofpacket -> rsp_mux_002:sink0_endofpacket
	wire          rsp_demux_002_src1_valid;                                                   // rsp_demux_002:src1_valid -> rsp_mux_001:sink1_valid
	wire  [146:0] rsp_demux_002_src1_data;                                                    // rsp_demux_002:src1_data -> rsp_mux_001:sink1_data
	wire          rsp_demux_002_src1_ready;                                                   // rsp_mux_001:sink1_ready -> rsp_demux_002:src1_ready
	wire    [3:0] rsp_demux_002_src1_channel;                                                 // rsp_demux_002:src1_channel -> rsp_mux_001:sink1_channel
	wire          rsp_demux_002_src1_startofpacket;                                           // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
	wire          rsp_demux_002_src1_endofpacket;                                             // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
	wire          rsp_demux_002_src2_valid;                                                   // rsp_demux_002:src2_valid -> rsp_mux_002:sink1_valid
	wire  [146:0] rsp_demux_002_src2_data;                                                    // rsp_demux_002:src2_data -> rsp_mux_002:sink1_data
	wire          rsp_demux_002_src2_ready;                                                   // rsp_mux_002:sink1_ready -> rsp_demux_002:src2_ready
	wire    [3:0] rsp_demux_002_src2_channel;                                                 // rsp_demux_002:src2_channel -> rsp_mux_002:sink1_channel
	wire          rsp_demux_002_src2_startofpacket;                                           // rsp_demux_002:src2_startofpacket -> rsp_mux_002:sink1_startofpacket
	wire          rsp_demux_002_src2_endofpacket;                                             // rsp_demux_002:src2_endofpacket -> rsp_mux_002:sink1_endofpacket
	wire          rsp_demux_003_src0_valid;                                                   // rsp_demux_003:src0_valid -> rsp_mux_001:sink2_valid
	wire  [146:0] rsp_demux_003_src0_data;                                                    // rsp_demux_003:src0_data -> rsp_mux_001:sink2_data
	wire          rsp_demux_003_src0_ready;                                                   // rsp_mux_001:sink2_ready -> rsp_demux_003:src0_ready
	wire    [3:0] rsp_demux_003_src0_channel;                                                 // rsp_demux_003:src0_channel -> rsp_mux_001:sink2_channel
	wire          rsp_demux_003_src0_startofpacket;                                           // rsp_demux_003:src0_startofpacket -> rsp_mux_001:sink2_startofpacket
	wire          rsp_demux_003_src0_endofpacket;                                             // rsp_demux_003:src0_endofpacket -> rsp_mux_001:sink2_endofpacket
	wire          rsp_demux_003_src1_valid;                                                   // rsp_demux_003:src1_valid -> rsp_mux_002:sink2_valid
	wire  [146:0] rsp_demux_003_src1_data;                                                    // rsp_demux_003:src1_data -> rsp_mux_002:sink2_data
	wire          rsp_demux_003_src1_ready;                                                   // rsp_mux_002:sink2_ready -> rsp_demux_003:src1_ready
	wire    [3:0] rsp_demux_003_src1_channel;                                                 // rsp_demux_003:src1_channel -> rsp_mux_002:sink2_channel
	wire          rsp_demux_003_src1_startofpacket;                                           // rsp_demux_003:src1_startofpacket -> rsp_mux_002:sink2_startofpacket
	wire          rsp_demux_003_src1_endofpacket;                                             // rsp_demux_003:src1_endofpacket -> rsp_mux_002:sink2_endofpacket
	wire          router_003_src_valid;                                                       // router_003:src_valid -> pb_rxm_2_msi_s0_rsp_width_adapter:in_valid
	wire  [110:0] router_003_src_data;                                                        // router_003:src_data -> pb_rxm_2_msi_s0_rsp_width_adapter:in_data
	wire          router_003_src_ready;                                                       // pb_rxm_2_msi_s0_rsp_width_adapter:in_ready -> router_003:src_ready
	wire    [3:0] router_003_src_channel;                                                     // router_003:src_channel -> pb_rxm_2_msi_s0_rsp_width_adapter:in_channel
	wire          router_003_src_startofpacket;                                               // router_003:src_startofpacket -> pb_rxm_2_msi_s0_rsp_width_adapter:in_startofpacket
	wire          router_003_src_endofpacket;                                                 // router_003:src_endofpacket -> pb_rxm_2_msi_s0_rsp_width_adapter:in_endofpacket
	wire          pb_rxm_2_msi_s0_rsp_width_adapter_src_valid;                                // pb_rxm_2_msi_s0_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
	wire  [146:0] pb_rxm_2_msi_s0_rsp_width_adapter_src_data;                                 // pb_rxm_2_msi_s0_rsp_width_adapter:out_data -> rsp_demux:sink_data
	wire          pb_rxm_2_msi_s0_rsp_width_adapter_src_ready;                                // rsp_demux:sink_ready -> pb_rxm_2_msi_s0_rsp_width_adapter:out_ready
	wire    [3:0] pb_rxm_2_msi_s0_rsp_width_adapter_src_channel;                              // pb_rxm_2_msi_s0_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
	wire          pb_rxm_2_msi_s0_rsp_width_adapter_src_startofpacket;                        // pb_rxm_2_msi_s0_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
	wire          pb_rxm_2_msi_s0_rsp_width_adapter_src_endofpacket;                          // pb_rxm_2_msi_s0_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
	wire          cmd_mux_src_valid;                                                          // cmd_mux:src_valid -> pb_rxm_2_msi_s0_cmd_width_adapter:in_valid
	wire  [146:0] cmd_mux_src_data;                                                           // cmd_mux:src_data -> pb_rxm_2_msi_s0_cmd_width_adapter:in_data
	wire          cmd_mux_src_ready;                                                          // pb_rxm_2_msi_s0_cmd_width_adapter:in_ready -> cmd_mux:src_ready
	wire    [3:0] cmd_mux_src_channel;                                                        // cmd_mux:src_channel -> pb_rxm_2_msi_s0_cmd_width_adapter:in_channel
	wire          cmd_mux_src_startofpacket;                                                  // cmd_mux:src_startofpacket -> pb_rxm_2_msi_s0_cmd_width_adapter:in_startofpacket
	wire          cmd_mux_src_endofpacket;                                                    // cmd_mux:src_endofpacket -> pb_rxm_2_msi_s0_cmd_width_adapter:in_endofpacket
	wire          pb_rxm_2_msi_s0_cmd_width_adapter_src_valid;                                // pb_rxm_2_msi_s0_cmd_width_adapter:out_valid -> pb_rxm_2_msi_s0_burst_adapter:sink0_valid
	wire  [110:0] pb_rxm_2_msi_s0_cmd_width_adapter_src_data;                                 // pb_rxm_2_msi_s0_cmd_width_adapter:out_data -> pb_rxm_2_msi_s0_burst_adapter:sink0_data
	wire          pb_rxm_2_msi_s0_cmd_width_adapter_src_ready;                                // pb_rxm_2_msi_s0_burst_adapter:sink0_ready -> pb_rxm_2_msi_s0_cmd_width_adapter:out_ready
	wire    [3:0] pb_rxm_2_msi_s0_cmd_width_adapter_src_channel;                              // pb_rxm_2_msi_s0_cmd_width_adapter:out_channel -> pb_rxm_2_msi_s0_burst_adapter:sink0_channel
	wire          pb_rxm_2_msi_s0_cmd_width_adapter_src_startofpacket;                        // pb_rxm_2_msi_s0_cmd_width_adapter:out_startofpacket -> pb_rxm_2_msi_s0_burst_adapter:sink0_startofpacket
	wire          pb_rxm_2_msi_s0_cmd_width_adapter_src_endofpacket;                          // pb_rxm_2_msi_s0_cmd_width_adapter:out_endofpacket -> pb_rxm_2_msi_s0_burst_adapter:sink0_endofpacket
	wire          cmd_demux_src0_valid;                                                       // cmd_demux:src0_valid -> async_fifo:in_valid
	wire  [146:0] cmd_demux_src0_data;                                                        // cmd_demux:src0_data -> async_fifo:in_data
	wire          cmd_demux_src0_ready;                                                       // async_fifo:in_ready -> cmd_demux:src0_ready
	wire    [3:0] cmd_demux_src0_channel;                                                     // cmd_demux:src0_channel -> async_fifo:in_channel
	wire          cmd_demux_src0_startofpacket;                                               // cmd_demux:src0_startofpacket -> async_fifo:in_startofpacket
	wire          cmd_demux_src0_endofpacket;                                                 // cmd_demux:src0_endofpacket -> async_fifo:in_endofpacket
	wire          async_fifo_out_valid;                                                       // async_fifo:out_valid -> cmd_mux:sink0_valid
	wire  [146:0] async_fifo_out_data;                                                        // async_fifo:out_data -> cmd_mux:sink0_data
	wire          async_fifo_out_ready;                                                       // cmd_mux:sink0_ready -> async_fifo:out_ready
	wire    [3:0] async_fifo_out_channel;                                                     // async_fifo:out_channel -> cmd_mux:sink0_channel
	wire          async_fifo_out_startofpacket;                                               // async_fifo:out_startofpacket -> cmd_mux:sink0_startofpacket
	wire          async_fifo_out_endofpacket;                                                 // async_fifo:out_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_src1_valid;                                                       // cmd_demux:src1_valid -> async_fifo_001:in_valid
	wire  [146:0] cmd_demux_src1_data;                                                        // cmd_demux:src1_data -> async_fifo_001:in_data
	wire          cmd_demux_src1_ready;                                                       // async_fifo_001:in_ready -> cmd_demux:src1_ready
	wire    [3:0] cmd_demux_src1_channel;                                                     // cmd_demux:src1_channel -> async_fifo_001:in_channel
	wire          cmd_demux_src1_startofpacket;                                               // cmd_demux:src1_startofpacket -> async_fifo_001:in_startofpacket
	wire          cmd_demux_src1_endofpacket;                                                 // cmd_demux:src1_endofpacket -> async_fifo_001:in_endofpacket
	wire          async_fifo_001_out_valid;                                                   // async_fifo_001:out_valid -> cmd_mux_001:sink0_valid
	wire  [146:0] async_fifo_001_out_data;                                                    // async_fifo_001:out_data -> cmd_mux_001:sink0_data
	wire          async_fifo_001_out_ready;                                                   // cmd_mux_001:sink0_ready -> async_fifo_001:out_ready
	wire    [3:0] async_fifo_001_out_channel;                                                 // async_fifo_001:out_channel -> cmd_mux_001:sink0_channel
	wire          async_fifo_001_out_startofpacket;                                           // async_fifo_001:out_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire          async_fifo_001_out_endofpacket;                                             // async_fifo_001:out_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire          cmd_demux_src2_valid;                                                       // cmd_demux:src2_valid -> async_fifo_002:in_valid
	wire  [146:0] cmd_demux_src2_data;                                                        // cmd_demux:src2_data -> async_fifo_002:in_data
	wire          cmd_demux_src2_ready;                                                       // async_fifo_002:in_ready -> cmd_demux:src2_ready
	wire    [3:0] cmd_demux_src2_channel;                                                     // cmd_demux:src2_channel -> async_fifo_002:in_channel
	wire          cmd_demux_src2_startofpacket;                                               // cmd_demux:src2_startofpacket -> async_fifo_002:in_startofpacket
	wire          cmd_demux_src2_endofpacket;                                                 // cmd_demux:src2_endofpacket -> async_fifo_002:in_endofpacket
	wire          async_fifo_002_out_valid;                                                   // async_fifo_002:out_valid -> cmd_mux_002:sink0_valid
	wire  [146:0] async_fifo_002_out_data;                                                    // async_fifo_002:out_data -> cmd_mux_002:sink0_data
	wire          async_fifo_002_out_ready;                                                   // cmd_mux_002:sink0_ready -> async_fifo_002:out_ready
	wire    [3:0] async_fifo_002_out_channel;                                                 // async_fifo_002:out_channel -> cmd_mux_002:sink0_channel
	wire          async_fifo_002_out_startofpacket;                                           // async_fifo_002:out_startofpacket -> cmd_mux_002:sink0_startofpacket
	wire          async_fifo_002_out_endofpacket;                                             // async_fifo_002:out_endofpacket -> cmd_mux_002:sink0_endofpacket
	wire          rsp_demux_src0_valid;                                                       // rsp_demux:src0_valid -> async_fifo_003:in_valid
	wire  [146:0] rsp_demux_src0_data;                                                        // rsp_demux:src0_data -> async_fifo_003:in_data
	wire          rsp_demux_src0_ready;                                                       // async_fifo_003:in_ready -> rsp_demux:src0_ready
	wire    [3:0] rsp_demux_src0_channel;                                                     // rsp_demux:src0_channel -> async_fifo_003:in_channel
	wire          rsp_demux_src0_startofpacket;                                               // rsp_demux:src0_startofpacket -> async_fifo_003:in_startofpacket
	wire          rsp_demux_src0_endofpacket;                                                 // rsp_demux:src0_endofpacket -> async_fifo_003:in_endofpacket
	wire          async_fifo_003_out_valid;                                                   // async_fifo_003:out_valid -> rsp_mux:sink0_valid
	wire  [146:0] async_fifo_003_out_data;                                                    // async_fifo_003:out_data -> rsp_mux:sink0_data
	wire          async_fifo_003_out_ready;                                                   // rsp_mux:sink0_ready -> async_fifo_003:out_ready
	wire    [3:0] async_fifo_003_out_channel;                                                 // async_fifo_003:out_channel -> rsp_mux:sink0_channel
	wire          async_fifo_003_out_startofpacket;                                           // async_fifo_003:out_startofpacket -> rsp_mux:sink0_startofpacket
	wire          async_fifo_003_out_endofpacket;                                             // async_fifo_003:out_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_001_src0_valid;                                                   // rsp_demux_001:src0_valid -> async_fifo_004:in_valid
	wire  [146:0] rsp_demux_001_src0_data;                                                    // rsp_demux_001:src0_data -> async_fifo_004:in_data
	wire          rsp_demux_001_src0_ready;                                                   // async_fifo_004:in_ready -> rsp_demux_001:src0_ready
	wire    [3:0] rsp_demux_001_src0_channel;                                                 // rsp_demux_001:src0_channel -> async_fifo_004:in_channel
	wire          rsp_demux_001_src0_startofpacket;                                           // rsp_demux_001:src0_startofpacket -> async_fifo_004:in_startofpacket
	wire          rsp_demux_001_src0_endofpacket;                                             // rsp_demux_001:src0_endofpacket -> async_fifo_004:in_endofpacket
	wire          async_fifo_004_out_valid;                                                   // async_fifo_004:out_valid -> rsp_mux:sink1_valid
	wire  [146:0] async_fifo_004_out_data;                                                    // async_fifo_004:out_data -> rsp_mux:sink1_data
	wire          async_fifo_004_out_ready;                                                   // rsp_mux:sink1_ready -> async_fifo_004:out_ready
	wire    [3:0] async_fifo_004_out_channel;                                                 // async_fifo_004:out_channel -> rsp_mux:sink1_channel
	wire          async_fifo_004_out_startofpacket;                                           // async_fifo_004:out_startofpacket -> rsp_mux:sink1_startofpacket
	wire          async_fifo_004_out_endofpacket;                                             // async_fifo_004:out_endofpacket -> rsp_mux:sink1_endofpacket
	wire          rsp_demux_002_src0_valid;                                                   // rsp_demux_002:src0_valid -> async_fifo_005:in_valid
	wire  [146:0] rsp_demux_002_src0_data;                                                    // rsp_demux_002:src0_data -> async_fifo_005:in_data
	wire          rsp_demux_002_src0_ready;                                                   // async_fifo_005:in_ready -> rsp_demux_002:src0_ready
	wire    [3:0] rsp_demux_002_src0_channel;                                                 // rsp_demux_002:src0_channel -> async_fifo_005:in_channel
	wire          rsp_demux_002_src0_startofpacket;                                           // rsp_demux_002:src0_startofpacket -> async_fifo_005:in_startofpacket
	wire          rsp_demux_002_src0_endofpacket;                                             // rsp_demux_002:src0_endofpacket -> async_fifo_005:in_endofpacket
	wire          async_fifo_005_out_valid;                                                   // async_fifo_005:out_valid -> rsp_mux:sink2_valid
	wire  [146:0] async_fifo_005_out_data;                                                    // async_fifo_005:out_data -> rsp_mux:sink2_data
	wire          async_fifo_005_out_ready;                                                   // rsp_mux:sink2_ready -> async_fifo_005:out_ready
	wire    [3:0] async_fifo_005_out_channel;                                                 // async_fifo_005:out_channel -> rsp_mux:sink2_channel
	wire          async_fifo_005_out_startofpacket;                                           // async_fifo_005:out_startofpacket -> rsp_mux:sink2_startofpacket
	wire          async_fifo_005_out_endofpacket;                                             // async_fifo_005:out_endofpacket -> rsp_mux:sink2_endofpacket
	wire          rsp_mux_src_valid;                                                          // rsp_mux:src_valid -> limiter_pipeline:in_valid
	wire  [146:0] rsp_mux_src_data;                                                           // rsp_mux:src_data -> limiter_pipeline:in_data
	wire          rsp_mux_src_ready;                                                          // limiter_pipeline:in_ready -> rsp_mux:src_ready
	wire    [3:0] rsp_mux_src_channel;                                                        // rsp_mux:src_channel -> limiter_pipeline:in_channel
	wire          rsp_mux_src_startofpacket;                                                  // rsp_mux:src_startofpacket -> limiter_pipeline:in_startofpacket
	wire          rsp_mux_src_endofpacket;                                                    // rsp_mux:src_endofpacket -> limiter_pipeline:in_endofpacket
	wire          limiter_pipeline_source0_valid;                                             // limiter_pipeline:out_valid -> pcie_hip_avmm_RP_Master_limiter:rsp_sink_valid
	wire  [146:0] limiter_pipeline_source0_data;                                              // limiter_pipeline:out_data -> pcie_hip_avmm_RP_Master_limiter:rsp_sink_data
	wire          limiter_pipeline_source0_ready;                                             // pcie_hip_avmm_RP_Master_limiter:rsp_sink_ready -> limiter_pipeline:out_ready
	wire    [3:0] limiter_pipeline_source0_channel;                                           // limiter_pipeline:out_channel -> pcie_hip_avmm_RP_Master_limiter:rsp_sink_channel
	wire          limiter_pipeline_source0_startofpacket;                                     // limiter_pipeline:out_startofpacket -> pcie_hip_avmm_RP_Master_limiter:rsp_sink_startofpacket
	wire          limiter_pipeline_source0_endofpacket;                                       // limiter_pipeline:out_endofpacket -> pcie_hip_avmm_RP_Master_limiter:rsp_sink_endofpacket
	wire          rsp_mux_001_src_valid;                                                      // rsp_mux_001:src_valid -> limiter_pipeline_001:in_valid
	wire  [146:0] rsp_mux_001_src_data;                                                       // rsp_mux_001:src_data -> limiter_pipeline_001:in_data
	wire          rsp_mux_001_src_ready;                                                      // limiter_pipeline_001:in_ready -> rsp_mux_001:src_ready
	wire    [3:0] rsp_mux_001_src_channel;                                                    // rsp_mux_001:src_channel -> limiter_pipeline_001:in_channel
	wire          rsp_mux_001_src_startofpacket;                                              // rsp_mux_001:src_startofpacket -> limiter_pipeline_001:in_startofpacket
	wire          rsp_mux_001_src_endofpacket;                                                // rsp_mux_001:src_endofpacket -> limiter_pipeline_001:in_endofpacket
	wire          limiter_pipeline_001_source0_valid;                                         // limiter_pipeline_001:out_valid -> msgdma_0_mm_read_limiter:rsp_sink_valid
	wire  [146:0] limiter_pipeline_001_source0_data;                                          // limiter_pipeline_001:out_data -> msgdma_0_mm_read_limiter:rsp_sink_data
	wire          limiter_pipeline_001_source0_ready;                                         // msgdma_0_mm_read_limiter:rsp_sink_ready -> limiter_pipeline_001:out_ready
	wire    [3:0] limiter_pipeline_001_source0_channel;                                       // limiter_pipeline_001:out_channel -> msgdma_0_mm_read_limiter:rsp_sink_channel
	wire          limiter_pipeline_001_source0_startofpacket;                                 // limiter_pipeline_001:out_startofpacket -> msgdma_0_mm_read_limiter:rsp_sink_startofpacket
	wire          limiter_pipeline_001_source0_endofpacket;                                   // limiter_pipeline_001:out_endofpacket -> msgdma_0_mm_read_limiter:rsp_sink_endofpacket
	wire          pb_rxm_2_msi_s0_burst_adapter_source0_valid;                                // pb_rxm_2_msi_s0_burst_adapter:source0_valid -> agent_pipeline:in_valid
	wire  [110:0] pb_rxm_2_msi_s0_burst_adapter_source0_data;                                 // pb_rxm_2_msi_s0_burst_adapter:source0_data -> agent_pipeline:in_data
	wire          pb_rxm_2_msi_s0_burst_adapter_source0_ready;                                // agent_pipeline:in_ready -> pb_rxm_2_msi_s0_burst_adapter:source0_ready
	wire    [3:0] pb_rxm_2_msi_s0_burst_adapter_source0_channel;                              // pb_rxm_2_msi_s0_burst_adapter:source0_channel -> agent_pipeline:in_channel
	wire          pb_rxm_2_msi_s0_burst_adapter_source0_startofpacket;                        // pb_rxm_2_msi_s0_burst_adapter:source0_startofpacket -> agent_pipeline:in_startofpacket
	wire          pb_rxm_2_msi_s0_burst_adapter_source0_endofpacket;                          // pb_rxm_2_msi_s0_burst_adapter:source0_endofpacket -> agent_pipeline:in_endofpacket
	wire          agent_pipeline_source0_valid;                                               // agent_pipeline:out_valid -> pb_rxm_2_msi_s0_agent:cp_valid
	wire  [110:0] agent_pipeline_source0_data;                                                // agent_pipeline:out_data -> pb_rxm_2_msi_s0_agent:cp_data
	wire          agent_pipeline_source0_ready;                                               // pb_rxm_2_msi_s0_agent:cp_ready -> agent_pipeline:out_ready
	wire    [3:0] agent_pipeline_source0_channel;                                             // agent_pipeline:out_channel -> pb_rxm_2_msi_s0_agent:cp_channel
	wire          agent_pipeline_source0_startofpacket;                                       // agent_pipeline:out_startofpacket -> pb_rxm_2_msi_s0_agent:cp_startofpacket
	wire          agent_pipeline_source0_endofpacket;                                         // agent_pipeline:out_endofpacket -> pb_rxm_2_msi_s0_agent:cp_endofpacket
	wire          pb_rxm_2_msi_s0_agent_rp_valid;                                             // pb_rxm_2_msi_s0_agent:rp_valid -> agent_pipeline_001:in_valid
	wire  [110:0] pb_rxm_2_msi_s0_agent_rp_data;                                              // pb_rxm_2_msi_s0_agent:rp_data -> agent_pipeline_001:in_data
	wire          pb_rxm_2_msi_s0_agent_rp_ready;                                             // agent_pipeline_001:in_ready -> pb_rxm_2_msi_s0_agent:rp_ready
	wire          pb_rxm_2_msi_s0_agent_rp_startofpacket;                                     // pb_rxm_2_msi_s0_agent:rp_startofpacket -> agent_pipeline_001:in_startofpacket
	wire          pb_rxm_2_msi_s0_agent_rp_endofpacket;                                       // pb_rxm_2_msi_s0_agent:rp_endofpacket -> agent_pipeline_001:in_endofpacket
	wire          agent_pipeline_001_source0_valid;                                           // agent_pipeline_001:out_valid -> router_003:sink_valid
	wire  [110:0] agent_pipeline_001_source0_data;                                            // agent_pipeline_001:out_data -> router_003:sink_data
	wire          agent_pipeline_001_source0_ready;                                           // router_003:sink_ready -> agent_pipeline_001:out_ready
	wire          agent_pipeline_001_source0_startofpacket;                                   // agent_pipeline_001:out_startofpacket -> router_003:sink_startofpacket
	wire          agent_pipeline_001_source0_endofpacket;                                     // agent_pipeline_001:out_endofpacket -> router_003:sink_endofpacket
	wire          cmd_mux_001_src_valid;                                                      // cmd_mux_001:src_valid -> agent_pipeline_002:in_valid
	wire  [146:0] cmd_mux_001_src_data;                                                       // cmd_mux_001:src_data -> agent_pipeline_002:in_data
	wire          cmd_mux_001_src_ready;                                                      // agent_pipeline_002:in_ready -> cmd_mux_001:src_ready
	wire    [3:0] cmd_mux_001_src_channel;                                                    // cmd_mux_001:src_channel -> agent_pipeline_002:in_channel
	wire          cmd_mux_001_src_startofpacket;                                              // cmd_mux_001:src_startofpacket -> agent_pipeline_002:in_startofpacket
	wire          cmd_mux_001_src_endofpacket;                                                // cmd_mux_001:src_endofpacket -> agent_pipeline_002:in_endofpacket
	wire          agent_pipeline_002_source0_valid;                                           // agent_pipeline_002:out_valid -> pb_2_ocm_s0_agent:cp_valid
	wire  [146:0] agent_pipeline_002_source0_data;                                            // agent_pipeline_002:out_data -> pb_2_ocm_s0_agent:cp_data
	wire          agent_pipeline_002_source0_ready;                                           // pb_2_ocm_s0_agent:cp_ready -> agent_pipeline_002:out_ready
	wire    [3:0] agent_pipeline_002_source0_channel;                                         // agent_pipeline_002:out_channel -> pb_2_ocm_s0_agent:cp_channel
	wire          agent_pipeline_002_source0_startofpacket;                                   // agent_pipeline_002:out_startofpacket -> pb_2_ocm_s0_agent:cp_startofpacket
	wire          agent_pipeline_002_source0_endofpacket;                                     // agent_pipeline_002:out_endofpacket -> pb_2_ocm_s0_agent:cp_endofpacket
	wire          pb_2_ocm_s0_agent_rp_valid;                                                 // pb_2_ocm_s0_agent:rp_valid -> agent_pipeline_003:in_valid
	wire  [146:0] pb_2_ocm_s0_agent_rp_data;                                                  // pb_2_ocm_s0_agent:rp_data -> agent_pipeline_003:in_data
	wire          pb_2_ocm_s0_agent_rp_ready;                                                 // agent_pipeline_003:in_ready -> pb_2_ocm_s0_agent:rp_ready
	wire          pb_2_ocm_s0_agent_rp_startofpacket;                                         // pb_2_ocm_s0_agent:rp_startofpacket -> agent_pipeline_003:in_startofpacket
	wire          pb_2_ocm_s0_agent_rp_endofpacket;                                           // pb_2_ocm_s0_agent:rp_endofpacket -> agent_pipeline_003:in_endofpacket
	wire          agent_pipeline_003_source0_valid;                                           // agent_pipeline_003:out_valid -> router_004:sink_valid
	wire  [146:0] agent_pipeline_003_source0_data;                                            // agent_pipeline_003:out_data -> router_004:sink_data
	wire          agent_pipeline_003_source0_ready;                                           // router_004:sink_ready -> agent_pipeline_003:out_ready
	wire          agent_pipeline_003_source0_startofpacket;                                   // agent_pipeline_003:out_startofpacket -> router_004:sink_startofpacket
	wire          agent_pipeline_003_source0_endofpacket;                                     // agent_pipeline_003:out_endofpacket -> router_004:sink_endofpacket
	wire          pb_f2sdram_s0_agent_rp_valid;                                               // pb_f2sdram_s0_agent:rp_valid -> agent_pipeline_004:in_valid
	wire  [146:0] pb_f2sdram_s0_agent_rp_data;                                                // pb_f2sdram_s0_agent:rp_data -> agent_pipeline_004:in_data
	wire          pb_f2sdram_s0_agent_rp_ready;                                               // agent_pipeline_004:in_ready -> pb_f2sdram_s0_agent:rp_ready
	wire          pb_f2sdram_s0_agent_rp_startofpacket;                                       // pb_f2sdram_s0_agent:rp_startofpacket -> agent_pipeline_004:in_startofpacket
	wire          pb_f2sdram_s0_agent_rp_endofpacket;                                         // pb_f2sdram_s0_agent:rp_endofpacket -> agent_pipeline_004:in_endofpacket
	wire          agent_pipeline_004_source0_valid;                                           // agent_pipeline_004:out_valid -> router_005:sink_valid
	wire  [146:0] agent_pipeline_004_source0_data;                                            // agent_pipeline_004:out_data -> router_005:sink_data
	wire          agent_pipeline_004_source0_ready;                                           // router_005:sink_ready -> agent_pipeline_004:out_ready
	wire          agent_pipeline_004_source0_startofpacket;                                   // agent_pipeline_004:out_startofpacket -> router_005:sink_startofpacket
	wire          agent_pipeline_004_source0_endofpacket;                                     // agent_pipeline_004:out_endofpacket -> router_005:sink_endofpacket
	wire          cmd_mux_003_src_valid;                                                      // cmd_mux_003:src_valid -> agent_pipeline_005:in_valid
	wire  [146:0] cmd_mux_003_src_data;                                                       // cmd_mux_003:src_data -> agent_pipeline_005:in_data
	wire          cmd_mux_003_src_ready;                                                      // agent_pipeline_005:in_ready -> cmd_mux_003:src_ready
	wire    [3:0] cmd_mux_003_src_channel;                                                    // cmd_mux_003:src_channel -> agent_pipeline_005:in_channel
	wire          cmd_mux_003_src_startofpacket;                                              // cmd_mux_003:src_startofpacket -> agent_pipeline_005:in_startofpacket
	wire          cmd_mux_003_src_endofpacket;                                                // cmd_mux_003:src_endofpacket -> agent_pipeline_005:in_endofpacket
	wire          agent_pipeline_005_source0_valid;                                           // agent_pipeline_005:out_valid -> pb_msgdma_2_txs_s0_agent:cp_valid
	wire  [146:0] agent_pipeline_005_source0_data;                                            // agent_pipeline_005:out_data -> pb_msgdma_2_txs_s0_agent:cp_data
	wire          agent_pipeline_005_source0_ready;                                           // pb_msgdma_2_txs_s0_agent:cp_ready -> agent_pipeline_005:out_ready
	wire    [3:0] agent_pipeline_005_source0_channel;                                         // agent_pipeline_005:out_channel -> pb_msgdma_2_txs_s0_agent:cp_channel
	wire          agent_pipeline_005_source0_startofpacket;                                   // agent_pipeline_005:out_startofpacket -> pb_msgdma_2_txs_s0_agent:cp_startofpacket
	wire          agent_pipeline_005_source0_endofpacket;                                     // agent_pipeline_005:out_endofpacket -> pb_msgdma_2_txs_s0_agent:cp_endofpacket
	wire          pb_msgdma_2_txs_s0_agent_rp_valid;                                          // pb_msgdma_2_txs_s0_agent:rp_valid -> agent_pipeline_006:in_valid
	wire  [146:0] pb_msgdma_2_txs_s0_agent_rp_data;                                           // pb_msgdma_2_txs_s0_agent:rp_data -> agent_pipeline_006:in_data
	wire          pb_msgdma_2_txs_s0_agent_rp_ready;                                          // agent_pipeline_006:in_ready -> pb_msgdma_2_txs_s0_agent:rp_ready
	wire          pb_msgdma_2_txs_s0_agent_rp_startofpacket;                                  // pb_msgdma_2_txs_s0_agent:rp_startofpacket -> agent_pipeline_006:in_startofpacket
	wire          pb_msgdma_2_txs_s0_agent_rp_endofpacket;                                    // pb_msgdma_2_txs_s0_agent:rp_endofpacket -> agent_pipeline_006:in_endofpacket
	wire          agent_pipeline_006_source0_valid;                                           // agent_pipeline_006:out_valid -> router_006:sink_valid
	wire  [146:0] agent_pipeline_006_source0_data;                                            // agent_pipeline_006:out_data -> router_006:sink_data
	wire          agent_pipeline_006_source0_ready;                                           // router_006:sink_ready -> agent_pipeline_006:out_ready
	wire          agent_pipeline_006_source0_startofpacket;                                   // agent_pipeline_006:out_startofpacket -> router_006:sink_startofpacket
	wire          agent_pipeline_006_source0_endofpacket;                                     // agent_pipeline_006:out_endofpacket -> router_006:sink_endofpacket
	wire          cmd_demux_002_src0_valid;                                                   // cmd_demux_002:src0_valid -> pipeline_stage:in_valid
	wire  [146:0] cmd_demux_002_src0_data;                                                    // cmd_demux_002:src0_data -> pipeline_stage:in_data
	wire          cmd_demux_002_src0_ready;                                                   // pipeline_stage:in_ready -> cmd_demux_002:src0_ready
	wire    [3:0] cmd_demux_002_src0_channel;                                                 // cmd_demux_002:src0_channel -> pipeline_stage:in_channel
	wire          cmd_demux_002_src0_startofpacket;                                           // cmd_demux_002:src0_startofpacket -> pipeline_stage:in_startofpacket
	wire          cmd_demux_002_src0_endofpacket;                                             // cmd_demux_002:src0_endofpacket -> pipeline_stage:in_endofpacket
	wire          pipeline_stage_source0_valid;                                               // pipeline_stage:out_valid -> cmd_mux_001:sink2_valid
	wire  [146:0] pipeline_stage_source0_data;                                                // pipeline_stage:out_data -> cmd_mux_001:sink2_data
	wire          pipeline_stage_source0_ready;                                               // cmd_mux_001:sink2_ready -> pipeline_stage:out_ready
	wire    [3:0] pipeline_stage_source0_channel;                                             // pipeline_stage:out_channel -> cmd_mux_001:sink2_channel
	wire          pipeline_stage_source0_startofpacket;                                       // pipeline_stage:out_startofpacket -> cmd_mux_001:sink2_startofpacket
	wire          pipeline_stage_source0_endofpacket;                                         // pipeline_stage:out_endofpacket -> cmd_mux_001:sink2_endofpacket
	wire          cmd_mux_002_src_valid;                                                      // cmd_mux_002:src_valid -> pipeline_stage_001:in_valid
	wire  [146:0] cmd_mux_002_src_data;                                                       // cmd_mux_002:src_data -> pipeline_stage_001:in_data
	wire          cmd_mux_002_src_ready;                                                      // pipeline_stage_001:in_ready -> cmd_mux_002:src_ready
	wire    [3:0] cmd_mux_002_src_channel;                                                    // cmd_mux_002:src_channel -> pipeline_stage_001:in_channel
	wire          cmd_mux_002_src_startofpacket;                                              // cmd_mux_002:src_startofpacket -> pipeline_stage_001:in_startofpacket
	wire          cmd_mux_002_src_endofpacket;                                                // cmd_mux_002:src_endofpacket -> pipeline_stage_001:in_endofpacket
	wire          pipeline_stage_001_source0_valid;                                           // pipeline_stage_001:out_valid -> pb_f2sdram_s0_agent:cp_valid
	wire  [146:0] pipeline_stage_001_source0_data;                                            // pipeline_stage_001:out_data -> pb_f2sdram_s0_agent:cp_data
	wire          pipeline_stage_001_source0_ready;                                           // pb_f2sdram_s0_agent:cp_ready -> pipeline_stage_001:out_ready
	wire    [3:0] pipeline_stage_001_source0_channel;                                         // pipeline_stage_001:out_channel -> pb_f2sdram_s0_agent:cp_channel
	wire          pipeline_stage_001_source0_startofpacket;                                   // pipeline_stage_001:out_startofpacket -> pb_f2sdram_s0_agent:cp_startofpacket
	wire          pipeline_stage_001_source0_endofpacket;                                     // pipeline_stage_001:out_endofpacket -> pb_f2sdram_s0_agent:cp_endofpacket
	wire          msgdma_0_mm_read_agent_cp_valid;                                            // msgdma_0_mm_read_agent:cp_valid -> pipeline_stage_002:in_valid
	wire  [146:0] msgdma_0_mm_read_agent_cp_data;                                             // msgdma_0_mm_read_agent:cp_data -> pipeline_stage_002:in_data
	wire          msgdma_0_mm_read_agent_cp_ready;                                            // pipeline_stage_002:in_ready -> msgdma_0_mm_read_agent:cp_ready
	wire          msgdma_0_mm_read_agent_cp_startofpacket;                                    // msgdma_0_mm_read_agent:cp_startofpacket -> pipeline_stage_002:in_startofpacket
	wire          msgdma_0_mm_read_agent_cp_endofpacket;                                      // msgdma_0_mm_read_agent:cp_endofpacket -> pipeline_stage_002:in_endofpacket
	wire          pipeline_stage_002_source0_valid;                                           // pipeline_stage_002:out_valid -> router_001:sink_valid
	wire  [146:0] pipeline_stage_002_source0_data;                                            // pipeline_stage_002:out_data -> router_001:sink_data
	wire          pipeline_stage_002_source0_ready;                                           // router_001:sink_ready -> pipeline_stage_002:out_ready
	wire          pipeline_stage_002_source0_startofpacket;                                   // pipeline_stage_002:out_startofpacket -> router_001:sink_startofpacket
	wire          pipeline_stage_002_source0_endofpacket;                                     // pipeline_stage_002:out_endofpacket -> router_001:sink_endofpacket
	wire    [0:0] msgdma_0_mm_read_limiter_cmd_src_valid;                                     // msgdma_0_mm_read_limiter:cmd_src_valid -> pipeline_stage_003:in_valid
	wire  [146:0] msgdma_0_mm_read_limiter_cmd_src_data;                                      // msgdma_0_mm_read_limiter:cmd_src_data -> pipeline_stage_003:in_data
	wire          msgdma_0_mm_read_limiter_cmd_src_ready;                                     // pipeline_stage_003:in_ready -> msgdma_0_mm_read_limiter:cmd_src_ready
	wire    [3:0] msgdma_0_mm_read_limiter_cmd_src_channel;                                   // msgdma_0_mm_read_limiter:cmd_src_channel -> pipeline_stage_003:in_channel
	wire          msgdma_0_mm_read_limiter_cmd_src_startofpacket;                             // msgdma_0_mm_read_limiter:cmd_src_startofpacket -> pipeline_stage_003:in_startofpacket
	wire          msgdma_0_mm_read_limiter_cmd_src_endofpacket;                               // msgdma_0_mm_read_limiter:cmd_src_endofpacket -> pipeline_stage_003:in_endofpacket
	wire          pipeline_stage_003_source0_valid;                                           // pipeline_stage_003:out_valid -> cmd_demux_001:sink_valid
	wire  [146:0] pipeline_stage_003_source0_data;                                            // pipeline_stage_003:out_data -> cmd_demux_001:sink_data
	wire          pipeline_stage_003_source0_ready;                                           // cmd_demux_001:sink_ready -> pipeline_stage_003:out_ready
	wire    [3:0] pipeline_stage_003_source0_channel;                                         // pipeline_stage_003:out_channel -> cmd_demux_001:sink_channel
	wire          pipeline_stage_003_source0_startofpacket;                                   // pipeline_stage_003:out_startofpacket -> cmd_demux_001:sink_startofpacket
	wire          pipeline_stage_003_source0_endofpacket;                                     // pipeline_stage_003:out_endofpacket -> cmd_demux_001:sink_endofpacket
	wire          msgdma_0_mm_write_agent_cp_valid;                                           // msgdma_0_mm_write_agent:cp_valid -> pipeline_stage_004:in_valid
	wire  [146:0] msgdma_0_mm_write_agent_cp_data;                                            // msgdma_0_mm_write_agent:cp_data -> pipeline_stage_004:in_data
	wire          msgdma_0_mm_write_agent_cp_ready;                                           // pipeline_stage_004:in_ready -> msgdma_0_mm_write_agent:cp_ready
	wire          msgdma_0_mm_write_agent_cp_startofpacket;                                   // msgdma_0_mm_write_agent:cp_startofpacket -> pipeline_stage_004:in_startofpacket
	wire          msgdma_0_mm_write_agent_cp_endofpacket;                                     // msgdma_0_mm_write_agent:cp_endofpacket -> pipeline_stage_004:in_endofpacket
	wire          pipeline_stage_004_source0_valid;                                           // pipeline_stage_004:out_valid -> router_002:sink_valid
	wire  [146:0] pipeline_stage_004_source0_data;                                            // pipeline_stage_004:out_data -> router_002:sink_data
	wire          pipeline_stage_004_source0_ready;                                           // router_002:sink_ready -> pipeline_stage_004:out_ready
	wire          pipeline_stage_004_source0_startofpacket;                                   // pipeline_stage_004:out_startofpacket -> router_002:sink_startofpacket
	wire          pipeline_stage_004_source0_endofpacket;                                     // pipeline_stage_004:out_endofpacket -> router_002:sink_endofpacket
	wire          pcie_hip_avmm_rp_master_agent_cp_valid;                                     // pcie_hip_avmm_RP_Master_agent:cp_valid -> pipeline_stage_005:in_valid
	wire  [146:0] pcie_hip_avmm_rp_master_agent_cp_data;                                      // pcie_hip_avmm_RP_Master_agent:cp_data -> pipeline_stage_005:in_data
	wire          pcie_hip_avmm_rp_master_agent_cp_ready;                                     // pipeline_stage_005:in_ready -> pcie_hip_avmm_RP_Master_agent:cp_ready
	wire          pcie_hip_avmm_rp_master_agent_cp_startofpacket;                             // pcie_hip_avmm_RP_Master_agent:cp_startofpacket -> pipeline_stage_005:in_startofpacket
	wire          pcie_hip_avmm_rp_master_agent_cp_endofpacket;                               // pcie_hip_avmm_RP_Master_agent:cp_endofpacket -> pipeline_stage_005:in_endofpacket
	wire          pipeline_stage_005_source0_valid;                                           // pipeline_stage_005:out_valid -> router:sink_valid
	wire  [146:0] pipeline_stage_005_source0_data;                                            // pipeline_stage_005:out_data -> router:sink_data
	wire          pipeline_stage_005_source0_ready;                                           // router:sink_ready -> pipeline_stage_005:out_ready
	wire          pipeline_stage_005_source0_startofpacket;                                   // pipeline_stage_005:out_startofpacket -> router:sink_startofpacket
	wire          pipeline_stage_005_source0_endofpacket;                                     // pipeline_stage_005:out_endofpacket -> router:sink_endofpacket
	wire    [0:0] pcie_hip_avmm_rp_master_limiter_cmd_src_valid;                              // pcie_hip_avmm_RP_Master_limiter:cmd_src_valid -> pipeline_stage_006:in_valid
	wire  [146:0] pcie_hip_avmm_rp_master_limiter_cmd_src_data;                               // pcie_hip_avmm_RP_Master_limiter:cmd_src_data -> pipeline_stage_006:in_data
	wire          pcie_hip_avmm_rp_master_limiter_cmd_src_ready;                              // pipeline_stage_006:in_ready -> pcie_hip_avmm_RP_Master_limiter:cmd_src_ready
	wire    [3:0] pcie_hip_avmm_rp_master_limiter_cmd_src_channel;                            // pcie_hip_avmm_RP_Master_limiter:cmd_src_channel -> pipeline_stage_006:in_channel
	wire          pcie_hip_avmm_rp_master_limiter_cmd_src_startofpacket;                      // pcie_hip_avmm_RP_Master_limiter:cmd_src_startofpacket -> pipeline_stage_006:in_startofpacket
	wire          pcie_hip_avmm_rp_master_limiter_cmd_src_endofpacket;                        // pcie_hip_avmm_RP_Master_limiter:cmd_src_endofpacket -> pipeline_stage_006:in_endofpacket
	wire          pipeline_stage_006_source0_valid;                                           // pipeline_stage_006:out_valid -> cmd_demux:sink_valid
	wire  [146:0] pipeline_stage_006_source0_data;                                            // pipeline_stage_006:out_data -> cmd_demux:sink_data
	wire          pipeline_stage_006_source0_ready;                                           // cmd_demux:sink_ready -> pipeline_stage_006:out_ready
	wire    [3:0] pipeline_stage_006_source0_channel;                                         // pipeline_stage_006:out_channel -> cmd_demux:sink_channel
	wire          pipeline_stage_006_source0_startofpacket;                                   // pipeline_stage_006:out_startofpacket -> cmd_demux:sink_startofpacket
	wire          pipeline_stage_006_source0_endofpacket;                                     // pipeline_stage_006:out_endofpacket -> cmd_demux:sink_endofpacket
	wire          pb_rxm_2_msi_s0_agent_rdata_fifo_out_valid;                                 // pb_rxm_2_msi_s0_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
	wire   [33:0] pb_rxm_2_msi_s0_agent_rdata_fifo_out_data;                                  // pb_rxm_2_msi_s0_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
	wire          pb_rxm_2_msi_s0_agent_rdata_fifo_out_ready;                                 // avalon_st_adapter:in_0_ready -> pb_rxm_2_msi_s0_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_out_0_valid;                                              // avalon_st_adapter:out_0_valid -> pb_rxm_2_msi_s0_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_out_0_data;                                               // avalon_st_adapter:out_0_data -> pb_rxm_2_msi_s0_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_out_0_ready;                                              // pb_rxm_2_msi_s0_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
	wire    [0:0] avalon_st_adapter_out_0_error;                                              // avalon_st_adapter:out_0_error -> pb_rxm_2_msi_s0_agent:rdata_fifo_sink_error
	wire          pb_2_ocm_s0_agent_rdata_fifo_out_valid;                                     // pb_2_ocm_s0_agent_rdata_fifo:out_valid -> avalon_st_adapter_001:in_0_valid
	wire   [65:0] pb_2_ocm_s0_agent_rdata_fifo_out_data;                                      // pb_2_ocm_s0_agent_rdata_fifo:out_data -> avalon_st_adapter_001:in_0_data
	wire          pb_2_ocm_s0_agent_rdata_fifo_out_ready;                                     // avalon_st_adapter_001:in_0_ready -> pb_2_ocm_s0_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_001_out_0_valid;                                          // avalon_st_adapter_001:out_0_valid -> pb_2_ocm_s0_agent:rdata_fifo_sink_valid
	wire   [65:0] avalon_st_adapter_001_out_0_data;                                           // avalon_st_adapter_001:out_0_data -> pb_2_ocm_s0_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_001_out_0_ready;                                          // pb_2_ocm_s0_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
	wire    [0:0] avalon_st_adapter_001_out_0_error;                                          // avalon_st_adapter_001:out_0_error -> pb_2_ocm_s0_agent:rdata_fifo_sink_error
	wire          pb_f2sdram_s0_agent_rdata_fifo_out_valid;                                   // pb_f2sdram_s0_agent_rdata_fifo:out_valid -> avalon_st_adapter_002:in_0_valid
	wire   [65:0] pb_f2sdram_s0_agent_rdata_fifo_out_data;                                    // pb_f2sdram_s0_agent_rdata_fifo:out_data -> avalon_st_adapter_002:in_0_data
	wire          pb_f2sdram_s0_agent_rdata_fifo_out_ready;                                   // avalon_st_adapter_002:in_0_ready -> pb_f2sdram_s0_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_002_out_0_valid;                                          // avalon_st_adapter_002:out_0_valid -> pb_f2sdram_s0_agent:rdata_fifo_sink_valid
	wire   [65:0] avalon_st_adapter_002_out_0_data;                                           // avalon_st_adapter_002:out_0_data -> pb_f2sdram_s0_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_002_out_0_ready;                                          // pb_f2sdram_s0_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
	wire    [0:0] avalon_st_adapter_002_out_0_error;                                          // avalon_st_adapter_002:out_0_error -> pb_f2sdram_s0_agent:rdata_fifo_sink_error
	wire          pb_msgdma_2_txs_s0_agent_rdata_fifo_out_valid;                              // pb_msgdma_2_txs_s0_agent_rdata_fifo:out_valid -> avalon_st_adapter_003:in_0_valid
	wire   [65:0] pb_msgdma_2_txs_s0_agent_rdata_fifo_out_data;                               // pb_msgdma_2_txs_s0_agent_rdata_fifo:out_data -> avalon_st_adapter_003:in_0_data
	wire          pb_msgdma_2_txs_s0_agent_rdata_fifo_out_ready;                              // avalon_st_adapter_003:in_0_ready -> pb_msgdma_2_txs_s0_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_003_out_0_valid;                                          // avalon_st_adapter_003:out_0_valid -> pb_msgdma_2_txs_s0_agent:rdata_fifo_sink_valid
	wire   [65:0] avalon_st_adapter_003_out_0_data;                                           // avalon_st_adapter_003:out_0_data -> pb_msgdma_2_txs_s0_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_003_out_0_ready;                                          // pb_msgdma_2_txs_s0_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
	wire    [0:0] avalon_st_adapter_003_out_0_error;                                          // avalon_st_adapter_003:out_0_error -> pb_msgdma_2_txs_s0_agent:rdata_fifo_sink_error

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (64),
		.AV_BURSTCOUNT_W             (7),
		.AV_BYTEENABLE_W             (8),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (10),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (8),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) pcie_hip_avmm_rp_master_translator (
		.clk                    (pcie_hip_avmm_coreclkout_clk),                                               //                       clk.clk
		.reset                  (pcie_hip_avmm_RP_Master_translator_reset_reset_bridge_in_reset_reset),       //                     reset.reset
		.uav_address            (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (pcie_hip_avmm_RP_Master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (pcie_hip_avmm_RP_Master_waitrequest),                                        //                          .waitrequest
		.av_burstcount          (pcie_hip_avmm_RP_Master_burstcount),                                         //                          .burstcount
		.av_byteenable          (pcie_hip_avmm_RP_Master_byteenable),                                         //                          .byteenable
		.av_read                (pcie_hip_avmm_RP_Master_read),                                               //                          .read
		.av_readdata            (pcie_hip_avmm_RP_Master_readdata),                                           //                          .readdata
		.av_readdatavalid       (pcie_hip_avmm_RP_Master_readdatavalid),                                      //                          .readdatavalid
		.av_write               (pcie_hip_avmm_RP_Master_write),                                              //                          .write
		.av_writedata           (pcie_hip_avmm_RP_Master_writedata),                                          //                          .writedata
		.av_beginbursttransfer  (1'b0),                                                                       //               (terminated)
		.av_begintransfer       (1'b0),                                                                       //               (terminated)
		.av_chipselect          (1'b0),                                                                       //               (terminated)
		.av_lock                (1'b0),                                                                       //               (terminated)
		.av_debugaccess         (1'b0),                                                                       //               (terminated)
		.uav_clken              (),                                                                           //               (terminated)
		.av_clken               (1'b1),                                                                       //               (terminated)
		.uav_response           (2'b00),                                                                      //               (terminated)
		.av_response            (),                                                                           //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                       //               (terminated)
		.av_writeresponsevalid  ()                                                                            //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (64),
		.AV_BURSTCOUNT_W             (7),
		.AV_BYTEENABLE_W             (8),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (10),
		.USE_READ                    (1),
		.USE_WRITE                   (0),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (8),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) msgdma_0_mm_read_translator (
		.clk                    (custom_reset_synchronizer_0_clock_out_clk),                            //                       clk.clk
		.reset                  (msgdma_0_reset_n_reset_bridge_in_reset_reset),                         //                     reset.reset
		.uav_address            (msgdma_0_mm_read_translator_avalon_universal_master_0_address),        // avalon_universal_master_0.address
		.uav_burstcount         (msgdma_0_mm_read_translator_avalon_universal_master_0_burstcount),     //                          .burstcount
		.uav_read               (msgdma_0_mm_read_translator_avalon_universal_master_0_read),           //                          .read
		.uav_write              (msgdma_0_mm_read_translator_avalon_universal_master_0_write),          //                          .write
		.uav_waitrequest        (msgdma_0_mm_read_translator_avalon_universal_master_0_waitrequest),    //                          .waitrequest
		.uav_readdatavalid      (msgdma_0_mm_read_translator_avalon_universal_master_0_readdatavalid),  //                          .readdatavalid
		.uav_byteenable         (msgdma_0_mm_read_translator_avalon_universal_master_0_byteenable),     //                          .byteenable
		.uav_readdata           (msgdma_0_mm_read_translator_avalon_universal_master_0_readdata),       //                          .readdata
		.uav_writedata          (msgdma_0_mm_read_translator_avalon_universal_master_0_writedata),      //                          .writedata
		.uav_lock               (msgdma_0_mm_read_translator_avalon_universal_master_0_lock),           //                          .lock
		.uav_debugaccess        (msgdma_0_mm_read_translator_avalon_universal_master_0_debugaccess),    //                          .debugaccess
		.av_address             (msgdma_0_mm_read_address),                                             //      avalon_anti_master_0.address
		.av_waitrequest         (msgdma_0_mm_read_waitrequest),                                         //                          .waitrequest
		.av_burstcount          (msgdma_0_mm_read_burstcount),                                          //                          .burstcount
		.av_byteenable          (msgdma_0_mm_read_byteenable),                                          //                          .byteenable
		.av_read                (msgdma_0_mm_read_read),                                                //                          .read
		.av_readdata            (msgdma_0_mm_read_readdata),                                            //                          .readdata
		.av_readdatavalid       (msgdma_0_mm_read_readdatavalid),                                       //                          .readdatavalid
		.av_beginbursttransfer  (1'b0),                                                                 //               (terminated)
		.av_begintransfer       (1'b0),                                                                 //               (terminated)
		.av_chipselect          (1'b0),                                                                 //               (terminated)
		.av_write               (1'b0),                                                                 //               (terminated)
		.av_writedata           (64'b0000000000000000000000000000000000000000000000000000000000000000), //               (terminated)
		.av_lock                (1'b0),                                                                 //               (terminated)
		.av_debugaccess         (1'b0),                                                                 //               (terminated)
		.uav_clken              (),                                                                     //               (terminated)
		.av_clken               (1'b1),                                                                 //               (terminated)
		.uav_response           (2'b00),                                                                //               (terminated)
		.av_response            (),                                                                     //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                 //               (terminated)
		.av_writeresponsevalid  ()                                                                      //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (64),
		.AV_BURSTCOUNT_W             (7),
		.AV_BYTEENABLE_W             (8),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (10),
		.USE_READ                    (0),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (0),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (8),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) msgdma_0_mm_write_translator (
		.clk                    (custom_reset_synchronizer_0_clock_out_clk),                            //                       clk.clk
		.reset                  (msgdma_0_reset_n_reset_bridge_in_reset_reset),                         //                     reset.reset
		.uav_address            (msgdma_0_mm_write_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (msgdma_0_mm_write_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (msgdma_0_mm_write_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (msgdma_0_mm_write_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (msgdma_0_mm_write_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (msgdma_0_mm_write_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (msgdma_0_mm_write_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (msgdma_0_mm_write_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (msgdma_0_mm_write_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (msgdma_0_mm_write_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (msgdma_0_mm_write_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (msgdma_0_mm_write_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (msgdma_0_mm_write_waitrequest),                                        //                          .waitrequest
		.av_burstcount          (msgdma_0_mm_write_burstcount),                                         //                          .burstcount
		.av_byteenable          (msgdma_0_mm_write_byteenable),                                         //                          .byteenable
		.av_write               (msgdma_0_mm_write_write),                                              //                          .write
		.av_writedata           (msgdma_0_mm_write_writedata),                                          //                          .writedata
		.av_beginbursttransfer  (1'b0),                                                                 //               (terminated)
		.av_begintransfer       (1'b0),                                                                 //               (terminated)
		.av_chipselect          (1'b0),                                                                 //               (terminated)
		.av_read                (1'b0),                                                                 //               (terminated)
		.av_readdata            (),                                                                     //               (terminated)
		.av_readdatavalid       (),                                                                     //               (terminated)
		.av_lock                (1'b0),                                                                 //               (terminated)
		.av_debugaccess         (1'b0),                                                                 //               (terminated)
		.uav_clken              (),                                                                     //               (terminated)
		.av_clken               (1'b1),                                                                 //               (terminated)
		.uav_response           (2'b00),                                                                //               (terminated)
		.av_response            (),                                                                     //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                 //               (terminated)
		.av_writeresponsevalid  ()                                                                      //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (15),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) pb_rxm_2_msi_s0_translator (
		.clk                    (custom_reset_synchronizer_0_clock_out_clk),    //                      clk.clk
		.reset                  (msgdma_0_reset_n_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (pb_rxm_2_msi_s0_agent_m0_address),             // avalon_universal_slave_0.address
		.uav_burstcount         (pb_rxm_2_msi_s0_agent_m0_burstcount),          //                         .burstcount
		.uav_read               (pb_rxm_2_msi_s0_agent_m0_read),                //                         .read
		.uav_write              (pb_rxm_2_msi_s0_agent_m0_write),               //                         .write
		.uav_waitrequest        (pb_rxm_2_msi_s0_agent_m0_waitrequest),         //                         .waitrequest
		.uav_readdatavalid      (pb_rxm_2_msi_s0_agent_m0_readdatavalid),       //                         .readdatavalid
		.uav_byteenable         (pb_rxm_2_msi_s0_agent_m0_byteenable),          //                         .byteenable
		.uav_readdata           (pb_rxm_2_msi_s0_agent_m0_readdata),            //                         .readdata
		.uav_writedata          (pb_rxm_2_msi_s0_agent_m0_writedata),           //                         .writedata
		.uav_lock               (pb_rxm_2_msi_s0_agent_m0_lock),                //                         .lock
		.uav_debugaccess        (pb_rxm_2_msi_s0_agent_m0_debugaccess),         //                         .debugaccess
		.av_address             (pb_rxm_2_msi_s0_address),                      //      avalon_anti_slave_0.address
		.av_write               (pb_rxm_2_msi_s0_write),                        //                         .write
		.av_read                (pb_rxm_2_msi_s0_read),                         //                         .read
		.av_readdata            (pb_rxm_2_msi_s0_readdata),                     //                         .readdata
		.av_writedata           (pb_rxm_2_msi_s0_writedata),                    //                         .writedata
		.av_burstcount          (pb_rxm_2_msi_s0_burstcount),                   //                         .burstcount
		.av_byteenable          (pb_rxm_2_msi_s0_byteenable),                   //                         .byteenable
		.av_readdatavalid       (pb_rxm_2_msi_s0_readdatavalid),                //                         .readdatavalid
		.av_waitrequest         (pb_rxm_2_msi_s0_waitrequest),                  //                         .waitrequest
		.av_debugaccess         (pb_rxm_2_msi_s0_debugaccess),                  //                         .debugaccess
		.av_begintransfer       (),                                             //              (terminated)
		.av_beginbursttransfer  (),                                             //              (terminated)
		.av_writebyteenable     (),                                             //              (terminated)
		.av_lock                (),                                             //              (terminated)
		.av_chipselect          (),                                             //              (terminated)
		.av_clken               (),                                             //              (terminated)
		.uav_clken              (1'b0),                                         //              (terminated)
		.av_outputenable        (),                                             //              (terminated)
		.uav_response           (),                                             //              (terminated)
		.av_response            (2'b00),                                        //              (terminated)
		.uav_writeresponsevalid (),                                             //              (terminated)
		.av_writeresponsevalid  (1'b0)                                          //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (16),
		.AV_DATA_W                      (64),
		.UAV_DATA_W                     (64),
		.AV_BURSTCOUNT_W                (7),
		.AV_BYTEENABLE_W                (8),
		.UAV_BYTEENABLE_W               (8),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (10),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (8),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) pb_2_ocm_s0_translator (
		.clk                    (custom_reset_synchronizer_0_clock_out_clk),    //                      clk.clk
		.reset                  (msgdma_0_reset_n_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (pb_2_ocm_s0_agent_m0_address),                 // avalon_universal_slave_0.address
		.uav_burstcount         (pb_2_ocm_s0_agent_m0_burstcount),              //                         .burstcount
		.uav_read               (pb_2_ocm_s0_agent_m0_read),                    //                         .read
		.uav_write              (pb_2_ocm_s0_agent_m0_write),                   //                         .write
		.uav_waitrequest        (pb_2_ocm_s0_agent_m0_waitrequest),             //                         .waitrequest
		.uav_readdatavalid      (pb_2_ocm_s0_agent_m0_readdatavalid),           //                         .readdatavalid
		.uav_byteenable         (pb_2_ocm_s0_agent_m0_byteenable),              //                         .byteenable
		.uav_readdata           (pb_2_ocm_s0_agent_m0_readdata),                //                         .readdata
		.uav_writedata          (pb_2_ocm_s0_agent_m0_writedata),               //                         .writedata
		.uav_lock               (pb_2_ocm_s0_agent_m0_lock),                    //                         .lock
		.uav_debugaccess        (pb_2_ocm_s0_agent_m0_debugaccess),             //                         .debugaccess
		.av_address             (pb_2_ocm_s0_address),                          //      avalon_anti_slave_0.address
		.av_write               (pb_2_ocm_s0_write),                            //                         .write
		.av_read                (pb_2_ocm_s0_read),                             //                         .read
		.av_readdata            (pb_2_ocm_s0_readdata),                         //                         .readdata
		.av_writedata           (pb_2_ocm_s0_writedata),                        //                         .writedata
		.av_burstcount          (pb_2_ocm_s0_burstcount),                       //                         .burstcount
		.av_byteenable          (pb_2_ocm_s0_byteenable),                       //                         .byteenable
		.av_readdatavalid       (pb_2_ocm_s0_readdatavalid),                    //                         .readdatavalid
		.av_waitrequest         (pb_2_ocm_s0_waitrequest),                      //                         .waitrequest
		.av_debugaccess         (pb_2_ocm_s0_debugaccess),                      //                         .debugaccess
		.av_begintransfer       (),                                             //              (terminated)
		.av_beginbursttransfer  (),                                             //              (terminated)
		.av_writebyteenable     (),                                             //              (terminated)
		.av_lock                (),                                             //              (terminated)
		.av_chipselect          (),                                             //              (terminated)
		.av_clken               (),                                             //              (terminated)
		.uav_clken              (1'b0),                                         //              (terminated)
		.av_outputenable        (),                                             //              (terminated)
		.uav_response           (),                                             //              (terminated)
		.av_response            (2'b00),                                        //              (terminated)
		.uav_writeresponsevalid (),                                             //              (terminated)
		.av_writeresponsevalid  (1'b0)                                          //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (30),
		.AV_DATA_W                      (64),
		.UAV_DATA_W                     (64),
		.AV_BURSTCOUNT_W                (7),
		.AV_BYTEENABLE_W                (8),
		.UAV_BYTEENABLE_W               (8),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (10),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (8),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) pb_f2sdram_s0_translator (
		.clk                    (custom_reset_synchronizer_0_clock_out_clk),    //                      clk.clk
		.reset                  (msgdma_0_reset_n_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (pb_f2sdram_s0_agent_m0_address),               // avalon_universal_slave_0.address
		.uav_burstcount         (pb_f2sdram_s0_agent_m0_burstcount),            //                         .burstcount
		.uav_read               (pb_f2sdram_s0_agent_m0_read),                  //                         .read
		.uav_write              (pb_f2sdram_s0_agent_m0_write),                 //                         .write
		.uav_waitrequest        (pb_f2sdram_s0_agent_m0_waitrequest),           //                         .waitrequest
		.uav_readdatavalid      (pb_f2sdram_s0_agent_m0_readdatavalid),         //                         .readdatavalid
		.uav_byteenable         (pb_f2sdram_s0_agent_m0_byteenable),            //                         .byteenable
		.uav_readdata           (pb_f2sdram_s0_agent_m0_readdata),              //                         .readdata
		.uav_writedata          (pb_f2sdram_s0_agent_m0_writedata),             //                         .writedata
		.uav_lock               (pb_f2sdram_s0_agent_m0_lock),                  //                         .lock
		.uav_debugaccess        (pb_f2sdram_s0_agent_m0_debugaccess),           //                         .debugaccess
		.av_address             (pb_f2sdram_s0_address),                        //      avalon_anti_slave_0.address
		.av_write               (pb_f2sdram_s0_write),                          //                         .write
		.av_read                (pb_f2sdram_s0_read),                           //                         .read
		.av_readdata            (pb_f2sdram_s0_readdata),                       //                         .readdata
		.av_writedata           (pb_f2sdram_s0_writedata),                      //                         .writedata
		.av_burstcount          (pb_f2sdram_s0_burstcount),                     //                         .burstcount
		.av_byteenable          (pb_f2sdram_s0_byteenable),                     //                         .byteenable
		.av_readdatavalid       (pb_f2sdram_s0_readdatavalid),                  //                         .readdatavalid
		.av_waitrequest         (pb_f2sdram_s0_waitrequest),                    //                         .waitrequest
		.av_debugaccess         (pb_f2sdram_s0_debugaccess),                    //                         .debugaccess
		.av_begintransfer       (),                                             //              (terminated)
		.av_beginbursttransfer  (),                                             //              (terminated)
		.av_writebyteenable     (),                                             //              (terminated)
		.av_lock                (),                                             //              (terminated)
		.av_chipselect          (),                                             //              (terminated)
		.av_clken               (),                                             //              (terminated)
		.uav_clken              (1'b0),                                         //              (terminated)
		.av_outputenable        (),                                             //              (terminated)
		.uav_response           (),                                             //              (terminated)
		.av_response            (2'b00),                                        //              (terminated)
		.uav_writeresponsevalid (),                                             //              (terminated)
		.av_writeresponsevalid  (1'b0)                                          //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (28),
		.AV_DATA_W                      (64),
		.UAV_DATA_W                     (64),
		.AV_BURSTCOUNT_W                (7),
		.AV_BYTEENABLE_W                (8),
		.UAV_BYTEENABLE_W               (8),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (10),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (8),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) pb_msgdma_2_txs_s0_translator (
		.clk                    (custom_reset_synchronizer_0_clock_out_clk),    //                      clk.clk
		.reset                  (msgdma_0_reset_n_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (pb_msgdma_2_txs_s0_agent_m0_address),          // avalon_universal_slave_0.address
		.uav_burstcount         (pb_msgdma_2_txs_s0_agent_m0_burstcount),       //                         .burstcount
		.uav_read               (pb_msgdma_2_txs_s0_agent_m0_read),             //                         .read
		.uav_write              (pb_msgdma_2_txs_s0_agent_m0_write),            //                         .write
		.uav_waitrequest        (pb_msgdma_2_txs_s0_agent_m0_waitrequest),      //                         .waitrequest
		.uav_readdatavalid      (pb_msgdma_2_txs_s0_agent_m0_readdatavalid),    //                         .readdatavalid
		.uav_byteenable         (pb_msgdma_2_txs_s0_agent_m0_byteenable),       //                         .byteenable
		.uav_readdata           (pb_msgdma_2_txs_s0_agent_m0_readdata),         //                         .readdata
		.uav_writedata          (pb_msgdma_2_txs_s0_agent_m0_writedata),        //                         .writedata
		.uav_lock               (pb_msgdma_2_txs_s0_agent_m0_lock),             //                         .lock
		.uav_debugaccess        (pb_msgdma_2_txs_s0_agent_m0_debugaccess),      //                         .debugaccess
		.av_address             (pb_msgdma_2_txs_s0_address),                   //      avalon_anti_slave_0.address
		.av_write               (pb_msgdma_2_txs_s0_write),                     //                         .write
		.av_read                (pb_msgdma_2_txs_s0_read),                      //                         .read
		.av_readdata            (pb_msgdma_2_txs_s0_readdata),                  //                         .readdata
		.av_writedata           (pb_msgdma_2_txs_s0_writedata),                 //                         .writedata
		.av_burstcount          (pb_msgdma_2_txs_s0_burstcount),                //                         .burstcount
		.av_byteenable          (pb_msgdma_2_txs_s0_byteenable),                //                         .byteenable
		.av_readdatavalid       (pb_msgdma_2_txs_s0_readdatavalid),             //                         .readdatavalid
		.av_waitrequest         (pb_msgdma_2_txs_s0_waitrequest),               //                         .waitrequest
		.av_debugaccess         (pb_msgdma_2_txs_s0_debugaccess),               //                         .debugaccess
		.av_begintransfer       (),                                             //              (terminated)
		.av_beginbursttransfer  (),                                             //              (terminated)
		.av_writebyteenable     (),                                             //              (terminated)
		.av_lock                (),                                             //              (terminated)
		.av_chipselect          (),                                             //              (terminated)
		.av_clken               (),                                             //              (terminated)
		.uav_clken              (1'b0),                                         //              (terminated)
		.av_outputenable        (),                                             //              (terminated)
		.uav_response           (),                                             //              (terminated)
		.av_response            (2'b00),                                        //              (terminated)
		.uav_writeresponsevalid (),                                             //              (terminated)
		.av_writeresponsevalid  (1'b0)                                          //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (146),
		.PKT_ORI_BURST_SIZE_L      (144),
		.PKT_RESPONSE_STATUS_H     (143),
		.PKT_RESPONSE_STATUS_L     (142),
		.PKT_QOS_H                 (129),
		.PKT_QOS_L                 (129),
		.PKT_DATA_SIDEBAND_H       (127),
		.PKT_DATA_SIDEBAND_L       (127),
		.PKT_ADDR_SIDEBAND_H       (126),
		.PKT_ADDR_SIDEBAND_L       (126),
		.PKT_BURST_TYPE_H          (125),
		.PKT_BURST_TYPE_L          (124),
		.PKT_CACHE_H               (141),
		.PKT_CACHE_L               (138),
		.PKT_THREAD_ID_H           (134),
		.PKT_THREAD_ID_L           (134),
		.PKT_BURST_SIZE_H          (123),
		.PKT_BURST_SIZE_L          (121),
		.PKT_TRANS_EXCLUSIVE       (109),
		.PKT_TRANS_LOCK            (108),
		.PKT_BEGIN_BURST           (128),
		.PKT_PROTECTION_H          (137),
		.PKT_PROTECTION_L          (135),
		.PKT_BURSTWRAP_H           (120),
		.PKT_BURSTWRAP_L           (120),
		.PKT_BYTE_CNT_H            (119),
		.PKT_BYTE_CNT_L            (110),
		.PKT_ADDR_H                (103),
		.PKT_ADDR_L                (72),
		.PKT_TRANS_COMPRESSED_READ (104),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.PKT_TRANS_READ            (107),
		.PKT_DATA_H                (63),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_SRC_ID_H              (131),
		.PKT_SRC_ID_L              (130),
		.PKT_DEST_ID_H             (133),
		.PKT_DEST_ID_L             (132),
		.ST_DATA_W                 (147),
		.ST_CHANNEL_W              (4),
		.AV_BURSTCOUNT_W           (10),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (2),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) pcie_hip_avmm_rp_master_agent (
		.clk                   (pcie_hip_avmm_coreclkout_clk),                                               //       clk.clk
		.reset                 (pcie_hip_avmm_RP_Master_translator_reset_reset_bridge_in_reset_reset),       // clk_reset.reset
		.av_address            (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (pcie_hip_avmm_rp_master_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (pcie_hip_avmm_rp_master_agent_cp_valid),                                     //        cp.valid
		.cp_data               (pcie_hip_avmm_rp_master_agent_cp_data),                                      //          .data
		.cp_startofpacket      (pcie_hip_avmm_rp_master_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (pcie_hip_avmm_rp_master_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (pcie_hip_avmm_rp_master_agent_cp_ready),                                     //          .ready
		.rp_valid              (pcie_hip_avmm_rp_master_limiter_rsp_src_valid),                              //        rp.valid
		.rp_data               (pcie_hip_avmm_rp_master_limiter_rsp_src_data),                               //          .data
		.rp_channel            (pcie_hip_avmm_rp_master_limiter_rsp_src_channel),                            //          .channel
		.rp_startofpacket      (pcie_hip_avmm_rp_master_limiter_rsp_src_startofpacket),                      //          .startofpacket
		.rp_endofpacket        (pcie_hip_avmm_rp_master_limiter_rsp_src_endofpacket),                        //          .endofpacket
		.rp_ready              (pcie_hip_avmm_rp_master_limiter_rsp_src_ready),                              //          .ready
		.av_response           (),                                                                           // (terminated)
		.av_writeresponsevalid ()                                                                            // (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (146),
		.PKT_ORI_BURST_SIZE_L      (144),
		.PKT_RESPONSE_STATUS_H     (143),
		.PKT_RESPONSE_STATUS_L     (142),
		.PKT_QOS_H                 (129),
		.PKT_QOS_L                 (129),
		.PKT_DATA_SIDEBAND_H       (127),
		.PKT_DATA_SIDEBAND_L       (127),
		.PKT_ADDR_SIDEBAND_H       (126),
		.PKT_ADDR_SIDEBAND_L       (126),
		.PKT_BURST_TYPE_H          (125),
		.PKT_BURST_TYPE_L          (124),
		.PKT_CACHE_H               (141),
		.PKT_CACHE_L               (138),
		.PKT_THREAD_ID_H           (134),
		.PKT_THREAD_ID_L           (134),
		.PKT_BURST_SIZE_H          (123),
		.PKT_BURST_SIZE_L          (121),
		.PKT_TRANS_EXCLUSIVE       (109),
		.PKT_TRANS_LOCK            (108),
		.PKT_BEGIN_BURST           (128),
		.PKT_PROTECTION_H          (137),
		.PKT_PROTECTION_L          (135),
		.PKT_BURSTWRAP_H           (120),
		.PKT_BURSTWRAP_L           (120),
		.PKT_BYTE_CNT_H            (119),
		.PKT_BYTE_CNT_L            (110),
		.PKT_ADDR_H                (103),
		.PKT_ADDR_L                (72),
		.PKT_TRANS_COMPRESSED_READ (104),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.PKT_TRANS_READ            (107),
		.PKT_DATA_H                (63),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_SRC_ID_H              (131),
		.PKT_SRC_ID_L              (130),
		.PKT_DEST_ID_H             (133),
		.PKT_DEST_ID_L             (132),
		.ST_DATA_W                 (147),
		.ST_CHANNEL_W              (4),
		.AV_BURSTCOUNT_W           (10),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) msgdma_0_mm_read_agent (
		.clk                   (custom_reset_synchronizer_0_clock_out_clk),                           //       clk.clk
		.reset                 (msgdma_0_reset_n_reset_bridge_in_reset_reset),                        // clk_reset.reset
		.av_address            (msgdma_0_mm_read_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (msgdma_0_mm_read_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (msgdma_0_mm_read_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (msgdma_0_mm_read_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (msgdma_0_mm_read_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (msgdma_0_mm_read_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (msgdma_0_mm_read_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (msgdma_0_mm_read_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (msgdma_0_mm_read_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (msgdma_0_mm_read_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (msgdma_0_mm_read_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (msgdma_0_mm_read_agent_cp_valid),                                     //        cp.valid
		.cp_data               (msgdma_0_mm_read_agent_cp_data),                                      //          .data
		.cp_startofpacket      (msgdma_0_mm_read_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (msgdma_0_mm_read_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (msgdma_0_mm_read_agent_cp_ready),                                     //          .ready
		.rp_valid              (msgdma_0_mm_read_limiter_rsp_src_valid),                              //        rp.valid
		.rp_data               (msgdma_0_mm_read_limiter_rsp_src_data),                               //          .data
		.rp_channel            (msgdma_0_mm_read_limiter_rsp_src_channel),                            //          .channel
		.rp_startofpacket      (msgdma_0_mm_read_limiter_rsp_src_startofpacket),                      //          .startofpacket
		.rp_endofpacket        (msgdma_0_mm_read_limiter_rsp_src_endofpacket),                        //          .endofpacket
		.rp_ready              (msgdma_0_mm_read_limiter_rsp_src_ready),                              //          .ready
		.av_response           (),                                                                    // (terminated)
		.av_writeresponsevalid ()                                                                     // (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (146),
		.PKT_ORI_BURST_SIZE_L      (144),
		.PKT_RESPONSE_STATUS_H     (143),
		.PKT_RESPONSE_STATUS_L     (142),
		.PKT_QOS_H                 (129),
		.PKT_QOS_L                 (129),
		.PKT_DATA_SIDEBAND_H       (127),
		.PKT_DATA_SIDEBAND_L       (127),
		.PKT_ADDR_SIDEBAND_H       (126),
		.PKT_ADDR_SIDEBAND_L       (126),
		.PKT_BURST_TYPE_H          (125),
		.PKT_BURST_TYPE_L          (124),
		.PKT_CACHE_H               (141),
		.PKT_CACHE_L               (138),
		.PKT_THREAD_ID_H           (134),
		.PKT_THREAD_ID_L           (134),
		.PKT_BURST_SIZE_H          (123),
		.PKT_BURST_SIZE_L          (121),
		.PKT_TRANS_EXCLUSIVE       (109),
		.PKT_TRANS_LOCK            (108),
		.PKT_BEGIN_BURST           (128),
		.PKT_PROTECTION_H          (137),
		.PKT_PROTECTION_L          (135),
		.PKT_BURSTWRAP_H           (120),
		.PKT_BURSTWRAP_L           (120),
		.PKT_BYTE_CNT_H            (119),
		.PKT_BYTE_CNT_L            (110),
		.PKT_ADDR_H                (103),
		.PKT_ADDR_L                (72),
		.PKT_TRANS_COMPRESSED_READ (104),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.PKT_TRANS_READ            (107),
		.PKT_DATA_H                (63),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_SRC_ID_H              (131),
		.PKT_SRC_ID_L              (130),
		.PKT_DEST_ID_H             (133),
		.PKT_DEST_ID_L             (132),
		.ST_DATA_W                 (147),
		.ST_CHANNEL_W              (4),
		.AV_BURSTCOUNT_W           (10),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (1),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) msgdma_0_mm_write_agent (
		.clk                   (custom_reset_synchronizer_0_clock_out_clk),                            //       clk.clk
		.reset                 (msgdma_0_reset_n_reset_bridge_in_reset_reset),                         // clk_reset.reset
		.av_address            (msgdma_0_mm_write_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (msgdma_0_mm_write_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (msgdma_0_mm_write_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (msgdma_0_mm_write_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (msgdma_0_mm_write_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (msgdma_0_mm_write_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (msgdma_0_mm_write_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (msgdma_0_mm_write_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (msgdma_0_mm_write_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (msgdma_0_mm_write_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (msgdma_0_mm_write_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (msgdma_0_mm_write_agent_cp_valid),                                     //        cp.valid
		.cp_data               (msgdma_0_mm_write_agent_cp_data),                                      //          .data
		.cp_startofpacket      (msgdma_0_mm_write_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (msgdma_0_mm_write_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (msgdma_0_mm_write_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_002_src_valid),                                                //        rp.valid
		.rp_data               (rsp_mux_002_src_data),                                                 //          .data
		.rp_channel            (rsp_mux_002_src_channel),                                              //          .channel
		.rp_startofpacket      (rsp_mux_002_src_startofpacket),                                        //          .startofpacket
		.rp_endofpacket        (rsp_mux_002_src_endofpacket),                                          //          .endofpacket
		.rp_ready              (rsp_mux_002_src_ready),                                                //          .ready
		.av_response           (),                                                                     // (terminated)
		.av_writeresponsevalid ()                                                                      // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (87),
		.PKT_BURST_SIZE_L          (85),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (92),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (84),
		.PKT_BURSTWRAP_L           (84),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (95),
		.PKT_SRC_ID_L              (94),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (96),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (4),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) pb_rxm_2_msi_s0_agent (
		.clk                     (custom_reset_synchronizer_0_clock_out_clk),        //             clk.clk
		.reset                   (msgdma_0_reset_n_reset_bridge_in_reset_reset),     //       clk_reset.reset
		.m0_address              (pb_rxm_2_msi_s0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (pb_rxm_2_msi_s0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (pb_rxm_2_msi_s0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (pb_rxm_2_msi_s0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (pb_rxm_2_msi_s0_agent_m0_lock),                    //                .lock
		.m0_readdata             (pb_rxm_2_msi_s0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (pb_rxm_2_msi_s0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (pb_rxm_2_msi_s0_agent_m0_read),                    //                .read
		.m0_waitrequest          (pb_rxm_2_msi_s0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (pb_rxm_2_msi_s0_agent_m0_writedata),               //                .writedata
		.m0_write                (pb_rxm_2_msi_s0_agent_m0_write),                   //                .write
		.rp_endofpacket          (pb_rxm_2_msi_s0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (pb_rxm_2_msi_s0_agent_rp_ready),                   //                .ready
		.rp_valid                (pb_rxm_2_msi_s0_agent_rp_valid),                   //                .valid
		.rp_data                 (pb_rxm_2_msi_s0_agent_rp_data),                    //                .data
		.rp_startofpacket        (pb_rxm_2_msi_s0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (agent_pipeline_source0_ready),                     //              cp.ready
		.cp_valid                (agent_pipeline_source0_valid),                     //                .valid
		.cp_data                 (agent_pipeline_source0_data),                      //                .data
		.cp_startofpacket        (agent_pipeline_source0_startofpacket),             //                .startofpacket
		.cp_endofpacket          (agent_pipeline_source0_endofpacket),               //                .endofpacket
		.cp_channel              (agent_pipeline_source0_channel),                   //                .channel
		.rf_sink_ready           (pb_rxm_2_msi_s0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (pb_rxm_2_msi_s0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (pb_rxm_2_msi_s0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (pb_rxm_2_msi_s0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (pb_rxm_2_msi_s0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (pb_rxm_2_msi_s0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (pb_rxm_2_msi_s0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (pb_rxm_2_msi_s0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (pb_rxm_2_msi_s0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (pb_rxm_2_msi_s0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                    // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                    //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                     //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                    //                .error
		.rdata_fifo_src_ready    (pb_rxm_2_msi_s0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (pb_rxm_2_msi_s0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (pb_rxm_2_msi_s0_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                            //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                              //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (3),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) pb_rxm_2_msi_s0_agent_rsp_fifo (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),        //       clk.clk
		.reset             (msgdma_0_reset_n_reset_bridge_in_reset_reset),     // clk_reset.reset
		.in_data           (pb_rxm_2_msi_s0_agent_rf_source_data),             //        in.data
		.in_valid          (pb_rxm_2_msi_s0_agent_rf_source_valid),            //          .valid
		.in_ready          (pb_rxm_2_msi_s0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (pb_rxm_2_msi_s0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (pb_rxm_2_msi_s0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (pb_rxm_2_msi_s0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (pb_rxm_2_msi_s0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (pb_rxm_2_msi_s0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (pb_rxm_2_msi_s0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (pb_rxm_2_msi_s0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                            // (terminated)
		.csr_read          (1'b0),                                             // (terminated)
		.csr_write         (1'b0),                                             // (terminated)
		.csr_readdata      (),                                                 // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),             // (terminated)
		.almost_full_data  (),                                                 // (terminated)
		.almost_empty_data (),                                                 // (terminated)
		.in_empty          (1'b0),                                             // (terminated)
		.out_empty         (),                                                 // (terminated)
		.in_error          (1'b0),                                             // (terminated)
		.out_error         (),                                                 // (terminated)
		.in_channel        (1'b0),                                             // (terminated)
		.out_channel       ()                                                  // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (3),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) pb_rxm_2_msi_s0_agent_rdata_fifo (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset             (msgdma_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (pb_rxm_2_msi_s0_agent_rdata_fifo_src_data),    //        in.data
		.in_valid          (pb_rxm_2_msi_s0_agent_rdata_fifo_src_valid),   //          .valid
		.in_ready          (pb_rxm_2_msi_s0_agent_rdata_fifo_src_ready),   //          .ready
		.out_data          (pb_rxm_2_msi_s0_agent_rdata_fifo_out_data),    //       out.data
		.out_valid         (pb_rxm_2_msi_s0_agent_rdata_fifo_out_valid),   //          .valid
		.out_ready         (pb_rxm_2_msi_s0_agent_rdata_fifo_out_ready),   //          .ready
		.csr_address       (2'b00),                                        // (terminated)
		.csr_read          (1'b0),                                         // (terminated)
		.csr_write         (1'b0),                                         // (terminated)
		.csr_readdata      (),                                             // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),         // (terminated)
		.almost_full_data  (),                                             // (terminated)
		.almost_empty_data (),                                             // (terminated)
		.in_startofpacket  (1'b0),                                         // (terminated)
		.in_endofpacket    (1'b0),                                         // (terminated)
		.out_startofpacket (),                                             // (terminated)
		.out_endofpacket   (),                                             // (terminated)
		.in_empty          (1'b0),                                         // (terminated)
		.out_empty         (),                                             // (terminated)
		.in_error          (1'b0),                                         // (terminated)
		.out_error         (),                                             // (terminated)
		.in_channel        (1'b0),                                         // (terminated)
		.out_channel       ()                                              // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (146),
		.PKT_ORI_BURST_SIZE_L      (144),
		.PKT_RESPONSE_STATUS_H     (143),
		.PKT_RESPONSE_STATUS_L     (142),
		.PKT_BURST_SIZE_H          (123),
		.PKT_BURST_SIZE_L          (121),
		.PKT_TRANS_LOCK            (108),
		.PKT_BEGIN_BURST           (128),
		.PKT_PROTECTION_H          (137),
		.PKT_PROTECTION_L          (135),
		.PKT_BURSTWRAP_H           (120),
		.PKT_BURSTWRAP_L           (120),
		.PKT_BYTE_CNT_H            (119),
		.PKT_BYTE_CNT_L            (110),
		.PKT_ADDR_H                (103),
		.PKT_ADDR_L                (72),
		.PKT_TRANS_COMPRESSED_READ (104),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.PKT_TRANS_READ            (107),
		.PKT_DATA_H                (63),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_SRC_ID_H              (131),
		.PKT_SRC_ID_L              (130),
		.PKT_DEST_ID_H             (133),
		.PKT_DEST_ID_L             (132),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (4),
		.ST_DATA_W                 (147),
		.AVS_BURSTCOUNT_W          (10),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) pb_2_ocm_s0_agent (
		.clk                     (custom_reset_synchronizer_0_clock_out_clk),    //             clk.clk
		.reset                   (msgdma_0_reset_n_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (pb_2_ocm_s0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (pb_2_ocm_s0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (pb_2_ocm_s0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (pb_2_ocm_s0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (pb_2_ocm_s0_agent_m0_lock),                    //                .lock
		.m0_readdata             (pb_2_ocm_s0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (pb_2_ocm_s0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (pb_2_ocm_s0_agent_m0_read),                    //                .read
		.m0_waitrequest          (pb_2_ocm_s0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (pb_2_ocm_s0_agent_m0_writedata),               //                .writedata
		.m0_write                (pb_2_ocm_s0_agent_m0_write),                   //                .write
		.rp_endofpacket          (pb_2_ocm_s0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (pb_2_ocm_s0_agent_rp_ready),                   //                .ready
		.rp_valid                (pb_2_ocm_s0_agent_rp_valid),                   //                .valid
		.rp_data                 (pb_2_ocm_s0_agent_rp_data),                    //                .data
		.rp_startofpacket        (pb_2_ocm_s0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (agent_pipeline_002_source0_ready),             //              cp.ready
		.cp_valid                (agent_pipeline_002_source0_valid),             //                .valid
		.cp_data                 (agent_pipeline_002_source0_data),              //                .data
		.cp_startofpacket        (agent_pipeline_002_source0_startofpacket),     //                .startofpacket
		.cp_endofpacket          (agent_pipeline_002_source0_endofpacket),       //                .endofpacket
		.cp_channel              (agent_pipeline_002_source0_channel),           //                .channel
		.rf_sink_ready           (pb_2_ocm_s0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (pb_2_ocm_s0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (pb_2_ocm_s0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (pb_2_ocm_s0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (pb_2_ocm_s0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (pb_2_ocm_s0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (pb_2_ocm_s0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (pb_2_ocm_s0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (pb_2_ocm_s0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (pb_2_ocm_s0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_001_out_0_ready),            // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_001_out_0_valid),            //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_001_out_0_data),             //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_001_out_0_error),            //                .error
		.rdata_fifo_src_ready    (pb_2_ocm_s0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (pb_2_ocm_s0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (pb_2_ocm_s0_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                        //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                          //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (148),
		.FIFO_DEPTH          (5),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) pb_2_ocm_s0_agent_rsp_fifo (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset             (msgdma_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (pb_2_ocm_s0_agent_rf_source_data),             //        in.data
		.in_valid          (pb_2_ocm_s0_agent_rf_source_valid),            //          .valid
		.in_ready          (pb_2_ocm_s0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (pb_2_ocm_s0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (pb_2_ocm_s0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (pb_2_ocm_s0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (pb_2_ocm_s0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (pb_2_ocm_s0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (pb_2_ocm_s0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (pb_2_ocm_s0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                        // (terminated)
		.csr_read          (1'b0),                                         // (terminated)
		.csr_write         (1'b0),                                         // (terminated)
		.csr_readdata      (),                                             // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),         // (terminated)
		.almost_full_data  (),                                             // (terminated)
		.almost_empty_data (),                                             // (terminated)
		.in_empty          (1'b0),                                         // (terminated)
		.out_empty         (),                                             // (terminated)
		.in_error          (1'b0),                                         // (terminated)
		.out_error         (),                                             // (terminated)
		.in_channel        (1'b0),                                         // (terminated)
		.out_channel       ()                                              // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (66),
		.FIFO_DEPTH          (512),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (3),
		.USE_MEMORY_BLOCKS   (1),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) pb_2_ocm_s0_agent_rdata_fifo (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset             (msgdma_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (pb_2_ocm_s0_agent_rdata_fifo_src_data),        //        in.data
		.in_valid          (pb_2_ocm_s0_agent_rdata_fifo_src_valid),       //          .valid
		.in_ready          (pb_2_ocm_s0_agent_rdata_fifo_src_ready),       //          .ready
		.out_data          (pb_2_ocm_s0_agent_rdata_fifo_out_data),        //       out.data
		.out_valid         (pb_2_ocm_s0_agent_rdata_fifo_out_valid),       //          .valid
		.out_ready         (pb_2_ocm_s0_agent_rdata_fifo_out_ready),       //          .ready
		.csr_address       (2'b00),                                        // (terminated)
		.csr_read          (1'b0),                                         // (terminated)
		.csr_write         (1'b0),                                         // (terminated)
		.csr_readdata      (),                                             // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),         // (terminated)
		.almost_full_data  (),                                             // (terminated)
		.almost_empty_data (),                                             // (terminated)
		.in_startofpacket  (1'b0),                                         // (terminated)
		.in_endofpacket    (1'b0),                                         // (terminated)
		.out_startofpacket (),                                             // (terminated)
		.out_endofpacket   (),                                             // (terminated)
		.in_empty          (1'b0),                                         // (terminated)
		.out_empty         (),                                             // (terminated)
		.in_error          (1'b0),                                         // (terminated)
		.out_error         (),                                             // (terminated)
		.in_channel        (1'b0),                                         // (terminated)
		.out_channel       ()                                              // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (146),
		.PKT_ORI_BURST_SIZE_L      (144),
		.PKT_RESPONSE_STATUS_H     (143),
		.PKT_RESPONSE_STATUS_L     (142),
		.PKT_BURST_SIZE_H          (123),
		.PKT_BURST_SIZE_L          (121),
		.PKT_TRANS_LOCK            (108),
		.PKT_BEGIN_BURST           (128),
		.PKT_PROTECTION_H          (137),
		.PKT_PROTECTION_L          (135),
		.PKT_BURSTWRAP_H           (120),
		.PKT_BURSTWRAP_L           (120),
		.PKT_BYTE_CNT_H            (119),
		.PKT_BYTE_CNT_L            (110),
		.PKT_ADDR_H                (103),
		.PKT_ADDR_L                (72),
		.PKT_TRANS_COMPRESSED_READ (104),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.PKT_TRANS_READ            (107),
		.PKT_DATA_H                (63),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_SRC_ID_H              (131),
		.PKT_SRC_ID_L              (130),
		.PKT_DEST_ID_H             (133),
		.PKT_DEST_ID_L             (132),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (4),
		.ST_DATA_W                 (147),
		.AVS_BURSTCOUNT_W          (10),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) pb_f2sdram_s0_agent (
		.clk                     (custom_reset_synchronizer_0_clock_out_clk),      //             clk.clk
		.reset                   (msgdma_0_reset_n_reset_bridge_in_reset_reset),   //       clk_reset.reset
		.m0_address              (pb_f2sdram_s0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (pb_f2sdram_s0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (pb_f2sdram_s0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (pb_f2sdram_s0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (pb_f2sdram_s0_agent_m0_lock),                    //                .lock
		.m0_readdata             (pb_f2sdram_s0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (pb_f2sdram_s0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (pb_f2sdram_s0_agent_m0_read),                    //                .read
		.m0_waitrequest          (pb_f2sdram_s0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (pb_f2sdram_s0_agent_m0_writedata),               //                .writedata
		.m0_write                (pb_f2sdram_s0_agent_m0_write),                   //                .write
		.rp_endofpacket          (pb_f2sdram_s0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (pb_f2sdram_s0_agent_rp_ready),                   //                .ready
		.rp_valid                (pb_f2sdram_s0_agent_rp_valid),                   //                .valid
		.rp_data                 (pb_f2sdram_s0_agent_rp_data),                    //                .data
		.rp_startofpacket        (pb_f2sdram_s0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (pipeline_stage_001_source0_ready),               //              cp.ready
		.cp_valid                (pipeline_stage_001_source0_valid),               //                .valid
		.cp_data                 (pipeline_stage_001_source0_data),                //                .data
		.cp_startofpacket        (pipeline_stage_001_source0_startofpacket),       //                .startofpacket
		.cp_endofpacket          (pipeline_stage_001_source0_endofpacket),         //                .endofpacket
		.cp_channel              (pipeline_stage_001_source0_channel),             //                .channel
		.rf_sink_ready           (pb_f2sdram_s0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (pb_f2sdram_s0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (pb_f2sdram_s0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (pb_f2sdram_s0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (pb_f2sdram_s0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (pb_f2sdram_s0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (pb_f2sdram_s0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (pb_f2sdram_s0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (pb_f2sdram_s0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (pb_f2sdram_s0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_002_out_0_ready),              // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_002_out_0_valid),              //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_002_out_0_data),               //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_002_out_0_error),              //                .error
		.rdata_fifo_src_ready    (pb_f2sdram_s0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (pb_f2sdram_s0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (pb_f2sdram_s0_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                          //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (148),
		.FIFO_DEPTH          (5),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) pb_f2sdram_s0_agent_rsp_fifo (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),      //       clk.clk
		.reset             (msgdma_0_reset_n_reset_bridge_in_reset_reset),   // clk_reset.reset
		.in_data           (pb_f2sdram_s0_agent_rf_source_data),             //        in.data
		.in_valid          (pb_f2sdram_s0_agent_rf_source_valid),            //          .valid
		.in_ready          (pb_f2sdram_s0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (pb_f2sdram_s0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (pb_f2sdram_s0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (pb_f2sdram_s0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (pb_f2sdram_s0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (pb_f2sdram_s0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (pb_f2sdram_s0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (pb_f2sdram_s0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                          // (terminated)
		.csr_read          (1'b0),                                           // (terminated)
		.csr_write         (1'b0),                                           // (terminated)
		.csr_readdata      (),                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),           // (terminated)
		.almost_full_data  (),                                               // (terminated)
		.almost_empty_data (),                                               // (terminated)
		.in_empty          (1'b0),                                           // (terminated)
		.out_empty         (),                                               // (terminated)
		.in_error          (1'b0),                                           // (terminated)
		.out_error         (),                                               // (terminated)
		.in_channel        (1'b0),                                           // (terminated)
		.out_channel       ()                                                // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (66),
		.FIFO_DEPTH          (512),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (3),
		.USE_MEMORY_BLOCKS   (1),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) pb_f2sdram_s0_agent_rdata_fifo (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset             (msgdma_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (pb_f2sdram_s0_agent_rdata_fifo_src_data),      //        in.data
		.in_valid          (pb_f2sdram_s0_agent_rdata_fifo_src_valid),     //          .valid
		.in_ready          (pb_f2sdram_s0_agent_rdata_fifo_src_ready),     //          .ready
		.out_data          (pb_f2sdram_s0_agent_rdata_fifo_out_data),      //       out.data
		.out_valid         (pb_f2sdram_s0_agent_rdata_fifo_out_valid),     //          .valid
		.out_ready         (pb_f2sdram_s0_agent_rdata_fifo_out_ready),     //          .ready
		.csr_address       (2'b00),                                        // (terminated)
		.csr_read          (1'b0),                                         // (terminated)
		.csr_write         (1'b0),                                         // (terminated)
		.csr_readdata      (),                                             // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),         // (terminated)
		.almost_full_data  (),                                             // (terminated)
		.almost_empty_data (),                                             // (terminated)
		.in_startofpacket  (1'b0),                                         // (terminated)
		.in_endofpacket    (1'b0),                                         // (terminated)
		.out_startofpacket (),                                             // (terminated)
		.out_endofpacket   (),                                             // (terminated)
		.in_empty          (1'b0),                                         // (terminated)
		.out_empty         (),                                             // (terminated)
		.in_error          (1'b0),                                         // (terminated)
		.out_error         (),                                             // (terminated)
		.in_channel        (1'b0),                                         // (terminated)
		.out_channel       ()                                              // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (146),
		.PKT_ORI_BURST_SIZE_L      (144),
		.PKT_RESPONSE_STATUS_H     (143),
		.PKT_RESPONSE_STATUS_L     (142),
		.PKT_BURST_SIZE_H          (123),
		.PKT_BURST_SIZE_L          (121),
		.PKT_TRANS_LOCK            (108),
		.PKT_BEGIN_BURST           (128),
		.PKT_PROTECTION_H          (137),
		.PKT_PROTECTION_L          (135),
		.PKT_BURSTWRAP_H           (120),
		.PKT_BURSTWRAP_L           (120),
		.PKT_BYTE_CNT_H            (119),
		.PKT_BYTE_CNT_L            (110),
		.PKT_ADDR_H                (103),
		.PKT_ADDR_L                (72),
		.PKT_TRANS_COMPRESSED_READ (104),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.PKT_TRANS_READ            (107),
		.PKT_DATA_H                (63),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_SRC_ID_H              (131),
		.PKT_SRC_ID_L              (130),
		.PKT_DEST_ID_H             (133),
		.PKT_DEST_ID_L             (132),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (4),
		.ST_DATA_W                 (147),
		.AVS_BURSTCOUNT_W          (10),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) pb_msgdma_2_txs_s0_agent (
		.clk                     (custom_reset_synchronizer_0_clock_out_clk),           //             clk.clk
		.reset                   (msgdma_0_reset_n_reset_bridge_in_reset_reset),        //       clk_reset.reset
		.m0_address              (pb_msgdma_2_txs_s0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (pb_msgdma_2_txs_s0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (pb_msgdma_2_txs_s0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (pb_msgdma_2_txs_s0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (pb_msgdma_2_txs_s0_agent_m0_lock),                    //                .lock
		.m0_readdata             (pb_msgdma_2_txs_s0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (pb_msgdma_2_txs_s0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (pb_msgdma_2_txs_s0_agent_m0_read),                    //                .read
		.m0_waitrequest          (pb_msgdma_2_txs_s0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (pb_msgdma_2_txs_s0_agent_m0_writedata),               //                .writedata
		.m0_write                (pb_msgdma_2_txs_s0_agent_m0_write),                   //                .write
		.rp_endofpacket          (pb_msgdma_2_txs_s0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (pb_msgdma_2_txs_s0_agent_rp_ready),                   //                .ready
		.rp_valid                (pb_msgdma_2_txs_s0_agent_rp_valid),                   //                .valid
		.rp_data                 (pb_msgdma_2_txs_s0_agent_rp_data),                    //                .data
		.rp_startofpacket        (pb_msgdma_2_txs_s0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (agent_pipeline_005_source0_ready),                    //              cp.ready
		.cp_valid                (agent_pipeline_005_source0_valid),                    //                .valid
		.cp_data                 (agent_pipeline_005_source0_data),                     //                .data
		.cp_startofpacket        (agent_pipeline_005_source0_startofpacket),            //                .startofpacket
		.cp_endofpacket          (agent_pipeline_005_source0_endofpacket),              //                .endofpacket
		.cp_channel              (agent_pipeline_005_source0_channel),                  //                .channel
		.rf_sink_ready           (pb_msgdma_2_txs_s0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (pb_msgdma_2_txs_s0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (pb_msgdma_2_txs_s0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (pb_msgdma_2_txs_s0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (pb_msgdma_2_txs_s0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (pb_msgdma_2_txs_s0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (pb_msgdma_2_txs_s0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (pb_msgdma_2_txs_s0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (pb_msgdma_2_txs_s0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (pb_msgdma_2_txs_s0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_003_out_0_ready),                   // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_003_out_0_valid),                   //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_003_out_0_data),                    //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_003_out_0_error),                   //                .error
		.rdata_fifo_src_ready    (pb_msgdma_2_txs_s0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (pb_msgdma_2_txs_s0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (pb_msgdma_2_txs_s0_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                               //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                 //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (148),
		.FIFO_DEPTH          (5),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) pb_msgdma_2_txs_s0_agent_rsp_fifo (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),           //       clk.clk
		.reset             (msgdma_0_reset_n_reset_bridge_in_reset_reset),        // clk_reset.reset
		.in_data           (pb_msgdma_2_txs_s0_agent_rf_source_data),             //        in.data
		.in_valid          (pb_msgdma_2_txs_s0_agent_rf_source_valid),            //          .valid
		.in_ready          (pb_msgdma_2_txs_s0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (pb_msgdma_2_txs_s0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (pb_msgdma_2_txs_s0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (pb_msgdma_2_txs_s0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (pb_msgdma_2_txs_s0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (pb_msgdma_2_txs_s0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (pb_msgdma_2_txs_s0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (pb_msgdma_2_txs_s0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                               // (terminated)
		.csr_read          (1'b0),                                                // (terminated)
		.csr_write         (1'b0),                                                // (terminated)
		.csr_readdata      (),                                                    // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                // (terminated)
		.almost_full_data  (),                                                    // (terminated)
		.almost_empty_data (),                                                    // (terminated)
		.in_empty          (1'b0),                                                // (terminated)
		.out_empty         (),                                                    // (terminated)
		.in_error          (1'b0),                                                // (terminated)
		.out_error         (),                                                    // (terminated)
		.in_channel        (1'b0),                                                // (terminated)
		.out_channel       ()                                                     // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (66),
		.FIFO_DEPTH          (512),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (3),
		.USE_MEMORY_BLOCKS   (1),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) pb_msgdma_2_txs_s0_agent_rdata_fifo (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),     //       clk.clk
		.reset             (msgdma_0_reset_n_reset_bridge_in_reset_reset),  // clk_reset.reset
		.in_data           (pb_msgdma_2_txs_s0_agent_rdata_fifo_src_data),  //        in.data
		.in_valid          (pb_msgdma_2_txs_s0_agent_rdata_fifo_src_valid), //          .valid
		.in_ready          (pb_msgdma_2_txs_s0_agent_rdata_fifo_src_ready), //          .ready
		.out_data          (pb_msgdma_2_txs_s0_agent_rdata_fifo_out_data),  //       out.data
		.out_valid         (pb_msgdma_2_txs_s0_agent_rdata_fifo_out_valid), //          .valid
		.out_ready         (pb_msgdma_2_txs_s0_agent_rdata_fifo_out_ready), //          .ready
		.csr_address       (2'b00),                                         // (terminated)
		.csr_read          (1'b0),                                          // (terminated)
		.csr_write         (1'b0),                                          // (terminated)
		.csr_readdata      (),                                              // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),          // (terminated)
		.almost_full_data  (),                                              // (terminated)
		.almost_empty_data (),                                              // (terminated)
		.in_startofpacket  (1'b0),                                          // (terminated)
		.in_endofpacket    (1'b0),                                          // (terminated)
		.out_startofpacket (),                                              // (terminated)
		.out_endofpacket   (),                                              // (terminated)
		.in_empty          (1'b0),                                          // (terminated)
		.out_empty         (),                                              // (terminated)
		.in_error          (1'b0),                                          // (terminated)
		.out_error         (),                                              // (terminated)
		.in_channel        (1'b0),                                          // (terminated)
		.out_channel       ()                                               // (terminated)
	);

	soc_system_pcie_0_mm_interconnect_0_router router (
		.sink_ready         (pipeline_stage_005_source0_ready),                                     //      sink.ready
		.sink_valid         (pipeline_stage_005_source0_valid),                                     //          .valid
		.sink_data          (pipeline_stage_005_source0_data),                                      //          .data
		.sink_startofpacket (pipeline_stage_005_source0_startofpacket),                             //          .startofpacket
		.sink_endofpacket   (pipeline_stage_005_source0_endofpacket),                               //          .endofpacket
		.clk                (pcie_hip_avmm_coreclkout_clk),                                         //       clk.clk
		.reset              (pcie_hip_avmm_RP_Master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_src_ready),                                                     //       src.ready
		.src_valid          (router_src_valid),                                                     //          .valid
		.src_data           (router_src_data),                                                      //          .data
		.src_channel        (router_src_channel),                                                   //          .channel
		.src_startofpacket  (router_src_startofpacket),                                             //          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                                //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_0_router_001 router_001 (
		.sink_ready         (pipeline_stage_002_source0_ready),             //      sink.ready
		.sink_valid         (pipeline_stage_002_source0_valid),             //          .valid
		.sink_data          (pipeline_stage_002_source0_data),              //          .data
		.sink_startofpacket (pipeline_stage_002_source0_startofpacket),     //          .startofpacket
		.sink_endofpacket   (pipeline_stage_002_source0_endofpacket),       //          .endofpacket
		.clk                (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset              (msgdma_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_001_src_ready),                         //       src.ready
		.src_valid          (router_001_src_valid),                         //          .valid
		.src_data           (router_001_src_data),                          //          .data
		.src_channel        (router_001_src_channel),                       //          .channel
		.src_startofpacket  (router_001_src_startofpacket),                 //          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                    //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_0_router_001 router_002 (
		.sink_ready         (pipeline_stage_004_source0_ready),             //      sink.ready
		.sink_valid         (pipeline_stage_004_source0_valid),             //          .valid
		.sink_data          (pipeline_stage_004_source0_data),              //          .data
		.sink_startofpacket (pipeline_stage_004_source0_startofpacket),     //          .startofpacket
		.sink_endofpacket   (pipeline_stage_004_source0_endofpacket),       //          .endofpacket
		.clk                (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset              (msgdma_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_002_src_ready),                         //       src.ready
		.src_valid          (router_002_src_valid),                         //          .valid
		.src_data           (router_002_src_data),                          //          .data
		.src_channel        (router_002_src_channel),                       //          .channel
		.src_startofpacket  (router_002_src_startofpacket),                 //          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                    //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_0_router_003 router_003 (
		.sink_ready         (agent_pipeline_001_source0_ready),             //      sink.ready
		.sink_valid         (agent_pipeline_001_source0_valid),             //          .valid
		.sink_data          (agent_pipeline_001_source0_data),              //          .data
		.sink_startofpacket (agent_pipeline_001_source0_startofpacket),     //          .startofpacket
		.sink_endofpacket   (agent_pipeline_001_source0_endofpacket),       //          .endofpacket
		.clk                (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset              (msgdma_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_003_src_ready),                         //       src.ready
		.src_valid          (router_003_src_valid),                         //          .valid
		.src_data           (router_003_src_data),                          //          .data
		.src_channel        (router_003_src_channel),                       //          .channel
		.src_startofpacket  (router_003_src_startofpacket),                 //          .startofpacket
		.src_endofpacket    (router_003_src_endofpacket)                    //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_0_router_004 router_004 (
		.sink_ready         (agent_pipeline_003_source0_ready),             //      sink.ready
		.sink_valid         (agent_pipeline_003_source0_valid),             //          .valid
		.sink_data          (agent_pipeline_003_source0_data),              //          .data
		.sink_startofpacket (agent_pipeline_003_source0_startofpacket),     //          .startofpacket
		.sink_endofpacket   (agent_pipeline_003_source0_endofpacket),       //          .endofpacket
		.clk                (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset              (msgdma_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_004_src_ready),                         //       src.ready
		.src_valid          (router_004_src_valid),                         //          .valid
		.src_data           (router_004_src_data),                          //          .data
		.src_channel        (router_004_src_channel),                       //          .channel
		.src_startofpacket  (router_004_src_startofpacket),                 //          .startofpacket
		.src_endofpacket    (router_004_src_endofpacket)                    //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_0_router_004 router_005 (
		.sink_ready         (agent_pipeline_004_source0_ready),             //      sink.ready
		.sink_valid         (agent_pipeline_004_source0_valid),             //          .valid
		.sink_data          (agent_pipeline_004_source0_data),              //          .data
		.sink_startofpacket (agent_pipeline_004_source0_startofpacket),     //          .startofpacket
		.sink_endofpacket   (agent_pipeline_004_source0_endofpacket),       //          .endofpacket
		.clk                (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset              (msgdma_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_005_src_ready),                         //       src.ready
		.src_valid          (router_005_src_valid),                         //          .valid
		.src_data           (router_005_src_data),                          //          .data
		.src_channel        (router_005_src_channel),                       //          .channel
		.src_startofpacket  (router_005_src_startofpacket),                 //          .startofpacket
		.src_endofpacket    (router_005_src_endofpacket)                    //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_0_router_006 router_006 (
		.sink_ready         (agent_pipeline_006_source0_ready),             //      sink.ready
		.sink_valid         (agent_pipeline_006_source0_valid),             //          .valid
		.sink_data          (agent_pipeline_006_source0_data),              //          .data
		.sink_startofpacket (agent_pipeline_006_source0_startofpacket),     //          .startofpacket
		.sink_endofpacket   (agent_pipeline_006_source0_endofpacket),       //          .endofpacket
		.clk                (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset              (msgdma_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_006_src_ready),                         //       src.ready
		.src_valid          (router_006_src_valid),                         //          .valid
		.src_data           (router_006_src_data),                          //          .data
		.src_channel        (router_006_src_channel),                       //          .channel
		.src_startofpacket  (router_006_src_startofpacket),                 //          .startofpacket
		.src_endofpacket    (router_006_src_endofpacket)                    //          .endofpacket
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (133),
		.PKT_DEST_ID_L             (132),
		.PKT_SRC_ID_H              (131),
		.PKT_SRC_ID_L              (130),
		.PKT_BYTE_CNT_H            (119),
		.PKT_BYTE_CNT_L            (110),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.MAX_OUTSTANDING_RESPONSES (30),
		.PIPELINED                 (0),
		.ST_DATA_W                 (147),
		.ST_CHANNEL_W              (4),
		.VALID_WIDTH               (1),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (0),
		.SUPPORTS_POSTED_WRITES    (1),
		.SUPPORTS_NONPOSTED_WRITES (0),
		.REORDER                   (0)
	) pcie_hip_avmm_rp_master_limiter (
		.clk                    (pcie_hip_avmm_coreclkout_clk),                                         //       clk.clk
		.reset                  (pcie_hip_avmm_RP_Master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.cmd_sink_ready         (router_src_ready),                                                     //  cmd_sink.ready
		.cmd_sink_valid         (router_src_valid),                                                     //          .valid
		.cmd_sink_data          (router_src_data),                                                      //          .data
		.cmd_sink_channel       (router_src_channel),                                                   //          .channel
		.cmd_sink_startofpacket (router_src_startofpacket),                                             //          .startofpacket
		.cmd_sink_endofpacket   (router_src_endofpacket),                                               //          .endofpacket
		.cmd_src_ready          (pcie_hip_avmm_rp_master_limiter_cmd_src_ready),                        //   cmd_src.ready
		.cmd_src_data           (pcie_hip_avmm_rp_master_limiter_cmd_src_data),                         //          .data
		.cmd_src_channel        (pcie_hip_avmm_rp_master_limiter_cmd_src_channel),                      //          .channel
		.cmd_src_startofpacket  (pcie_hip_avmm_rp_master_limiter_cmd_src_startofpacket),                //          .startofpacket
		.cmd_src_endofpacket    (pcie_hip_avmm_rp_master_limiter_cmd_src_endofpacket),                  //          .endofpacket
		.cmd_src_valid          (pcie_hip_avmm_rp_master_limiter_cmd_src_valid),                        //          .valid
		.rsp_sink_ready         (limiter_pipeline_source0_ready),                                       //  rsp_sink.ready
		.rsp_sink_valid         (limiter_pipeline_source0_valid),                                       //          .valid
		.rsp_sink_channel       (limiter_pipeline_source0_channel),                                     //          .channel
		.rsp_sink_data          (limiter_pipeline_source0_data),                                        //          .data
		.rsp_sink_startofpacket (limiter_pipeline_source0_startofpacket),                               //          .startofpacket
		.rsp_sink_endofpacket   (limiter_pipeline_source0_endofpacket),                                 //          .endofpacket
		.rsp_src_ready          (pcie_hip_avmm_rp_master_limiter_rsp_src_ready),                        //   rsp_src.ready
		.rsp_src_valid          (pcie_hip_avmm_rp_master_limiter_rsp_src_valid),                        //          .valid
		.rsp_src_data           (pcie_hip_avmm_rp_master_limiter_rsp_src_data),                         //          .data
		.rsp_src_channel        (pcie_hip_avmm_rp_master_limiter_rsp_src_channel),                      //          .channel
		.rsp_src_startofpacket  (pcie_hip_avmm_rp_master_limiter_rsp_src_startofpacket),                //          .startofpacket
		.rsp_src_endofpacket    (pcie_hip_avmm_rp_master_limiter_rsp_src_endofpacket)                   //          .endofpacket
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (133),
		.PKT_DEST_ID_L             (132),
		.PKT_SRC_ID_H              (131),
		.PKT_SRC_ID_L              (130),
		.PKT_BYTE_CNT_H            (119),
		.PKT_BYTE_CNT_L            (110),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.MAX_OUTSTANDING_RESPONSES (12),
		.PIPELINED                 (0),
		.ST_DATA_W                 (147),
		.ST_CHANNEL_W              (4),
		.VALID_WIDTH               (1),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (0),
		.SUPPORTS_POSTED_WRITES    (1),
		.SUPPORTS_NONPOSTED_WRITES (0),
		.REORDER                   (0)
	) msgdma_0_mm_read_limiter (
		.clk                    (custom_reset_synchronizer_0_clock_out_clk),      //       clk.clk
		.reset                  (msgdma_0_reset_n_reset_bridge_in_reset_reset),   // clk_reset.reset
		.cmd_sink_ready         (router_001_src_ready),                           //  cmd_sink.ready
		.cmd_sink_valid         (router_001_src_valid),                           //          .valid
		.cmd_sink_data          (router_001_src_data),                            //          .data
		.cmd_sink_channel       (router_001_src_channel),                         //          .channel
		.cmd_sink_startofpacket (router_001_src_startofpacket),                   //          .startofpacket
		.cmd_sink_endofpacket   (router_001_src_endofpacket),                     //          .endofpacket
		.cmd_src_ready          (msgdma_0_mm_read_limiter_cmd_src_ready),         //   cmd_src.ready
		.cmd_src_data           (msgdma_0_mm_read_limiter_cmd_src_data),          //          .data
		.cmd_src_channel        (msgdma_0_mm_read_limiter_cmd_src_channel),       //          .channel
		.cmd_src_startofpacket  (msgdma_0_mm_read_limiter_cmd_src_startofpacket), //          .startofpacket
		.cmd_src_endofpacket    (msgdma_0_mm_read_limiter_cmd_src_endofpacket),   //          .endofpacket
		.cmd_src_valid          (msgdma_0_mm_read_limiter_cmd_src_valid),         //          .valid
		.rsp_sink_ready         (limiter_pipeline_001_source0_ready),             //  rsp_sink.ready
		.rsp_sink_valid         (limiter_pipeline_001_source0_valid),             //          .valid
		.rsp_sink_channel       (limiter_pipeline_001_source0_channel),           //          .channel
		.rsp_sink_data          (limiter_pipeline_001_source0_data),              //          .data
		.rsp_sink_startofpacket (limiter_pipeline_001_source0_startofpacket),     //          .startofpacket
		.rsp_sink_endofpacket   (limiter_pipeline_001_source0_endofpacket),       //          .endofpacket
		.rsp_src_ready          (msgdma_0_mm_read_limiter_rsp_src_ready),         //   rsp_src.ready
		.rsp_src_valid          (msgdma_0_mm_read_limiter_rsp_src_valid),         //          .valid
		.rsp_src_data           (msgdma_0_mm_read_limiter_rsp_src_data),          //          .data
		.rsp_src_channel        (msgdma_0_mm_read_limiter_rsp_src_channel),       //          .channel
		.rsp_src_startofpacket  (msgdma_0_mm_read_limiter_rsp_src_startofpacket), //          .startofpacket
		.rsp_src_endofpacket    (msgdma_0_mm_read_limiter_rsp_src_endofpacket)    //          .endofpacket
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (92),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (87),
		.PKT_BURST_SIZE_L          (85),
		.PKT_BURST_TYPE_H          (89),
		.PKT_BURST_TYPE_L          (88),
		.PKT_BURSTWRAP_H           (84),
		.PKT_BURSTWRAP_L           (84),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (111),
		.ST_CHANNEL_W              (4),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (84),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (1),
		.BURSTWRAP_CONST_VALUE     (1),
		.ADAPTER_VERSION           ("13.1")
	) pb_rxm_2_msi_s0_burst_adapter (
		.clk                   (custom_reset_synchronizer_0_clock_out_clk),           //       cr0.clk
		.reset                 (msgdma_0_reset_n_reset_bridge_in_reset_reset),        // cr0_reset.reset
		.sink0_valid           (pb_rxm_2_msi_s0_cmd_width_adapter_src_valid),         //     sink0.valid
		.sink0_data            (pb_rxm_2_msi_s0_cmd_width_adapter_src_data),          //          .data
		.sink0_channel         (pb_rxm_2_msi_s0_cmd_width_adapter_src_channel),       //          .channel
		.sink0_startofpacket   (pb_rxm_2_msi_s0_cmd_width_adapter_src_startofpacket), //          .startofpacket
		.sink0_endofpacket     (pb_rxm_2_msi_s0_cmd_width_adapter_src_endofpacket),   //          .endofpacket
		.sink0_ready           (pb_rxm_2_msi_s0_cmd_width_adapter_src_ready),         //          .ready
		.source0_valid         (pb_rxm_2_msi_s0_burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (pb_rxm_2_msi_s0_burst_adapter_source0_data),          //          .data
		.source0_channel       (pb_rxm_2_msi_s0_burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (pb_rxm_2_msi_s0_burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (pb_rxm_2_msi_s0_burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (pb_rxm_2_msi_s0_burst_adapter_source0_ready)          //          .ready
	);

	soc_system_pcie_0_mm_interconnect_0_cmd_demux cmd_demux (
		.clk                (pcie_hip_avmm_coreclkout_clk),                                         //       clk.clk
		.reset              (pcie_hip_avmm_RP_Master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (pipeline_stage_006_source0_ready),                                     //      sink.ready
		.sink_channel       (pipeline_stage_006_source0_channel),                                   //          .channel
		.sink_data          (pipeline_stage_006_source0_data),                                      //          .data
		.sink_startofpacket (pipeline_stage_006_source0_startofpacket),                             //          .startofpacket
		.sink_endofpacket   (pipeline_stage_006_source0_endofpacket),                               //          .endofpacket
		.sink_valid         (pipeline_stage_006_source0_valid),                                     //          .valid
		.src0_ready         (cmd_demux_src0_ready),                                                 //      src0.ready
		.src0_valid         (cmd_demux_src0_valid),                                                 //          .valid
		.src0_data          (cmd_demux_src0_data),                                                  //          .data
		.src0_channel       (cmd_demux_src0_channel),                                               //          .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                                         //          .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket),                                           //          .endofpacket
		.src1_ready         (cmd_demux_src1_ready),                                                 //      src1.ready
		.src1_valid         (cmd_demux_src1_valid),                                                 //          .valid
		.src1_data          (cmd_demux_src1_data),                                                  //          .data
		.src1_channel       (cmd_demux_src1_channel),                                               //          .channel
		.src1_startofpacket (cmd_demux_src1_startofpacket),                                         //          .startofpacket
		.src1_endofpacket   (cmd_demux_src1_endofpacket),                                           //          .endofpacket
		.src2_ready         (cmd_demux_src2_ready),                                                 //      src2.ready
		.src2_valid         (cmd_demux_src2_valid),                                                 //          .valid
		.src2_data          (cmd_demux_src2_data),                                                  //          .data
		.src2_channel       (cmd_demux_src2_channel),                                               //          .channel
		.src2_startofpacket (cmd_demux_src2_startofpacket),                                         //          .startofpacket
		.src2_endofpacket   (cmd_demux_src2_endofpacket)                                            //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
		.clk                (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset              (msgdma_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (pipeline_stage_003_source0_ready),             //      sink.ready
		.sink_channel       (pipeline_stage_003_source0_channel),           //          .channel
		.sink_data          (pipeline_stage_003_source0_data),              //          .data
		.sink_startofpacket (pipeline_stage_003_source0_startofpacket),     //          .startofpacket
		.sink_endofpacket   (pipeline_stage_003_source0_endofpacket),       //          .endofpacket
		.sink_valid         (pipeline_stage_003_source0_valid),             //          .valid
		.src0_ready         (cmd_demux_001_src0_ready),                     //      src0.ready
		.src0_valid         (cmd_demux_001_src0_valid),                     //          .valid
		.src0_data          (cmd_demux_001_src0_data),                      //          .data
		.src0_channel       (cmd_demux_001_src0_channel),                   //          .channel
		.src0_startofpacket (cmd_demux_001_src0_startofpacket),             //          .startofpacket
		.src0_endofpacket   (cmd_demux_001_src0_endofpacket),               //          .endofpacket
		.src1_ready         (cmd_demux_001_src1_ready),                     //      src1.ready
		.src1_valid         (cmd_demux_001_src1_valid),                     //          .valid
		.src1_data          (cmd_demux_001_src1_data),                      //          .data
		.src1_channel       (cmd_demux_001_src1_channel),                   //          .channel
		.src1_startofpacket (cmd_demux_001_src1_startofpacket),             //          .startofpacket
		.src1_endofpacket   (cmd_demux_001_src1_endofpacket),               //          .endofpacket
		.src2_ready         (cmd_demux_001_src2_ready),                     //      src2.ready
		.src2_valid         (cmd_demux_001_src2_valid),                     //          .valid
		.src2_data          (cmd_demux_001_src2_data),                      //          .data
		.src2_channel       (cmd_demux_001_src2_channel),                   //          .channel
		.src2_startofpacket (cmd_demux_001_src2_startofpacket),             //          .startofpacket
		.src2_endofpacket   (cmd_demux_001_src2_endofpacket)                //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_0_cmd_demux_001 cmd_demux_002 (
		.clk                (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset              (msgdma_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_002_src_ready),                         //      sink.ready
		.sink_channel       (router_002_src_channel),                       //          .channel
		.sink_data          (router_002_src_data),                          //          .data
		.sink_startofpacket (router_002_src_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (router_002_src_endofpacket),                   //          .endofpacket
		.sink_valid         (router_002_src_valid),                         //          .valid
		.src0_ready         (cmd_demux_002_src0_ready),                     //      src0.ready
		.src0_valid         (cmd_demux_002_src0_valid),                     //          .valid
		.src0_data          (cmd_demux_002_src0_data),                      //          .data
		.src0_channel       (cmd_demux_002_src0_channel),                   //          .channel
		.src0_startofpacket (cmd_demux_002_src0_startofpacket),             //          .startofpacket
		.src0_endofpacket   (cmd_demux_002_src0_endofpacket),               //          .endofpacket
		.src1_ready         (cmd_demux_002_src1_ready),                     //      src1.ready
		.src1_valid         (cmd_demux_002_src1_valid),                     //          .valid
		.src1_data          (cmd_demux_002_src1_data),                      //          .data
		.src1_channel       (cmd_demux_002_src1_channel),                   //          .channel
		.src1_startofpacket (cmd_demux_002_src1_startofpacket),             //          .startofpacket
		.src1_endofpacket   (cmd_demux_002_src1_endofpacket),               //          .endofpacket
		.src2_ready         (cmd_demux_002_src2_ready),                     //      src2.ready
		.src2_valid         (cmd_demux_002_src2_valid),                     //          .valid
		.src2_data          (cmd_demux_002_src2_data),                      //          .data
		.src2_channel       (cmd_demux_002_src2_channel),                   //          .channel
		.src2_startofpacket (cmd_demux_002_src2_startofpacket),             //          .startofpacket
		.src2_endofpacket   (cmd_demux_002_src2_endofpacket)                //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_0_cmd_mux cmd_mux (
		.clk                 (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset               (msgdma_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                            //       src.ready
		.src_valid           (cmd_mux_src_valid),                            //          .valid
		.src_data            (cmd_mux_src_data),                             //          .data
		.src_channel         (cmd_mux_src_channel),                          //          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                    //          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                      //          .endofpacket
		.sink0_ready         (async_fifo_out_ready),                         //     sink0.ready
		.sink0_valid         (async_fifo_out_valid),                         //          .valid
		.sink0_channel       (async_fifo_out_channel),                       //          .channel
		.sink0_data          (async_fifo_out_data),                          //          .data
		.sink0_startofpacket (async_fifo_out_startofpacket),                 //          .startofpacket
		.sink0_endofpacket   (async_fifo_out_endofpacket)                    //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
		.clk                 (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset               (msgdma_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_001_src_ready),                        //       src.ready
		.src_valid           (cmd_mux_001_src_valid),                        //          .valid
		.src_data            (cmd_mux_001_src_data),                         //          .data
		.src_channel         (cmd_mux_001_src_channel),                      //          .channel
		.src_startofpacket   (cmd_mux_001_src_startofpacket),                //          .startofpacket
		.src_endofpacket     (cmd_mux_001_src_endofpacket),                  //          .endofpacket
		.sink0_ready         (async_fifo_001_out_ready),                     //     sink0.ready
		.sink0_valid         (async_fifo_001_out_valid),                     //          .valid
		.sink0_channel       (async_fifo_001_out_channel),                   //          .channel
		.sink0_data          (async_fifo_001_out_data),                      //          .data
		.sink0_startofpacket (async_fifo_001_out_startofpacket),             //          .startofpacket
		.sink0_endofpacket   (async_fifo_001_out_endofpacket),               //          .endofpacket
		.sink1_ready         (cmd_demux_001_src0_ready),                     //     sink1.ready
		.sink1_valid         (cmd_demux_001_src0_valid),                     //          .valid
		.sink1_channel       (cmd_demux_001_src0_channel),                   //          .channel
		.sink1_data          (cmd_demux_001_src0_data),                      //          .data
		.sink1_startofpacket (cmd_demux_001_src0_startofpacket),             //          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src0_endofpacket),               //          .endofpacket
		.sink2_ready         (pipeline_stage_source0_ready),                 //     sink2.ready
		.sink2_valid         (pipeline_stage_source0_valid),                 //          .valid
		.sink2_channel       (pipeline_stage_source0_channel),               //          .channel
		.sink2_data          (pipeline_stage_source0_data),                  //          .data
		.sink2_startofpacket (pipeline_stage_source0_startofpacket),         //          .startofpacket
		.sink2_endofpacket   (pipeline_stage_source0_endofpacket)            //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_0_cmd_mux_001 cmd_mux_002 (
		.clk                 (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset               (msgdma_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_002_src_ready),                        //       src.ready
		.src_valid           (cmd_mux_002_src_valid),                        //          .valid
		.src_data            (cmd_mux_002_src_data),                         //          .data
		.src_channel         (cmd_mux_002_src_channel),                      //          .channel
		.src_startofpacket   (cmd_mux_002_src_startofpacket),                //          .startofpacket
		.src_endofpacket     (cmd_mux_002_src_endofpacket),                  //          .endofpacket
		.sink0_ready         (async_fifo_002_out_ready),                     //     sink0.ready
		.sink0_valid         (async_fifo_002_out_valid),                     //          .valid
		.sink0_channel       (async_fifo_002_out_channel),                   //          .channel
		.sink0_data          (async_fifo_002_out_data),                      //          .data
		.sink0_startofpacket (async_fifo_002_out_startofpacket),             //          .startofpacket
		.sink0_endofpacket   (async_fifo_002_out_endofpacket),               //          .endofpacket
		.sink1_ready         (cmd_demux_001_src1_ready),                     //     sink1.ready
		.sink1_valid         (cmd_demux_001_src1_valid),                     //          .valid
		.sink1_channel       (cmd_demux_001_src1_channel),                   //          .channel
		.sink1_data          (cmd_demux_001_src1_data),                      //          .data
		.sink1_startofpacket (cmd_demux_001_src1_startofpacket),             //          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src1_endofpacket),               //          .endofpacket
		.sink2_ready         (cmd_demux_002_src1_ready),                     //     sink2.ready
		.sink2_valid         (cmd_demux_002_src1_valid),                     //          .valid
		.sink2_channel       (cmd_demux_002_src1_channel),                   //          .channel
		.sink2_data          (cmd_demux_002_src1_data),                      //          .data
		.sink2_startofpacket (cmd_demux_002_src1_startofpacket),             //          .startofpacket
		.sink2_endofpacket   (cmd_demux_002_src1_endofpacket)                //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_0_cmd_mux_003 cmd_mux_003 (
		.clk                 (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset               (msgdma_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_003_src_ready),                        //       src.ready
		.src_valid           (cmd_mux_003_src_valid),                        //          .valid
		.src_data            (cmd_mux_003_src_data),                         //          .data
		.src_channel         (cmd_mux_003_src_channel),                      //          .channel
		.src_startofpacket   (cmd_mux_003_src_startofpacket),                //          .startofpacket
		.src_endofpacket     (cmd_mux_003_src_endofpacket),                  //          .endofpacket
		.sink0_ready         (cmd_demux_001_src2_ready),                     //     sink0.ready
		.sink0_valid         (cmd_demux_001_src2_valid),                     //          .valid
		.sink0_channel       (cmd_demux_001_src2_channel),                   //          .channel
		.sink0_data          (cmd_demux_001_src2_data),                      //          .data
		.sink0_startofpacket (cmd_demux_001_src2_startofpacket),             //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src2_endofpacket),               //          .endofpacket
		.sink1_ready         (cmd_demux_002_src2_ready),                     //     sink1.ready
		.sink1_valid         (cmd_demux_002_src2_valid),                     //          .valid
		.sink1_channel       (cmd_demux_002_src2_channel),                   //          .channel
		.sink1_data          (cmd_demux_002_src2_data),                      //          .data
		.sink1_startofpacket (cmd_demux_002_src2_startofpacket),             //          .startofpacket
		.sink1_endofpacket   (cmd_demux_002_src2_endofpacket)                //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_0_rsp_demux rsp_demux (
		.clk                (custom_reset_synchronizer_0_clock_out_clk),           //       clk.clk
		.reset              (msgdma_0_reset_n_reset_bridge_in_reset_reset),        // clk_reset.reset
		.sink_ready         (pb_rxm_2_msi_s0_rsp_width_adapter_src_ready),         //      sink.ready
		.sink_channel       (pb_rxm_2_msi_s0_rsp_width_adapter_src_channel),       //          .channel
		.sink_data          (pb_rxm_2_msi_s0_rsp_width_adapter_src_data),          //          .data
		.sink_startofpacket (pb_rxm_2_msi_s0_rsp_width_adapter_src_startofpacket), //          .startofpacket
		.sink_endofpacket   (pb_rxm_2_msi_s0_rsp_width_adapter_src_endofpacket),   //          .endofpacket
		.sink_valid         (pb_rxm_2_msi_s0_rsp_width_adapter_src_valid),         //          .valid
		.src0_ready         (rsp_demux_src0_ready),                                //      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                                //          .valid
		.src0_data          (rsp_demux_src0_data),                                 //          .data
		.src0_channel       (rsp_demux_src0_channel),                              //          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                        //          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket)                           //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_0_cmd_demux_001 rsp_demux_001 (
		.clk                (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset              (msgdma_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_004_src_ready),                         //      sink.ready
		.sink_channel       (router_004_src_channel),                       //          .channel
		.sink_data          (router_004_src_data),                          //          .data
		.sink_startofpacket (router_004_src_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (router_004_src_endofpacket),                   //          .endofpacket
		.sink_valid         (router_004_src_valid),                         //          .valid
		.src0_ready         (rsp_demux_001_src0_ready),                     //      src0.ready
		.src0_valid         (rsp_demux_001_src0_valid),                     //          .valid
		.src0_data          (rsp_demux_001_src0_data),                      //          .data
		.src0_channel       (rsp_demux_001_src0_channel),                   //          .channel
		.src0_startofpacket (rsp_demux_001_src0_startofpacket),             //          .startofpacket
		.src0_endofpacket   (rsp_demux_001_src0_endofpacket),               //          .endofpacket
		.src1_ready         (rsp_demux_001_src1_ready),                     //      src1.ready
		.src1_valid         (rsp_demux_001_src1_valid),                     //          .valid
		.src1_data          (rsp_demux_001_src1_data),                      //          .data
		.src1_channel       (rsp_demux_001_src1_channel),                   //          .channel
		.src1_startofpacket (rsp_demux_001_src1_startofpacket),             //          .startofpacket
		.src1_endofpacket   (rsp_demux_001_src1_endofpacket),               //          .endofpacket
		.src2_ready         (rsp_demux_001_src2_ready),                     //      src2.ready
		.src2_valid         (rsp_demux_001_src2_valid),                     //          .valid
		.src2_data          (rsp_demux_001_src2_data),                      //          .data
		.src2_channel       (rsp_demux_001_src2_channel),                   //          .channel
		.src2_startofpacket (rsp_demux_001_src2_startofpacket),             //          .startofpacket
		.src2_endofpacket   (rsp_demux_001_src2_endofpacket)                //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_0_cmd_demux_001 rsp_demux_002 (
		.clk                (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset              (msgdma_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_005_src_ready),                         //      sink.ready
		.sink_channel       (router_005_src_channel),                       //          .channel
		.sink_data          (router_005_src_data),                          //          .data
		.sink_startofpacket (router_005_src_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (router_005_src_endofpacket),                   //          .endofpacket
		.sink_valid         (router_005_src_valid),                         //          .valid
		.src0_ready         (rsp_demux_002_src0_ready),                     //      src0.ready
		.src0_valid         (rsp_demux_002_src0_valid),                     //          .valid
		.src0_data          (rsp_demux_002_src0_data),                      //          .data
		.src0_channel       (rsp_demux_002_src0_channel),                   //          .channel
		.src0_startofpacket (rsp_demux_002_src0_startofpacket),             //          .startofpacket
		.src0_endofpacket   (rsp_demux_002_src0_endofpacket),               //          .endofpacket
		.src1_ready         (rsp_demux_002_src1_ready),                     //      src1.ready
		.src1_valid         (rsp_demux_002_src1_valid),                     //          .valid
		.src1_data          (rsp_demux_002_src1_data),                      //          .data
		.src1_channel       (rsp_demux_002_src1_channel),                   //          .channel
		.src1_startofpacket (rsp_demux_002_src1_startofpacket),             //          .startofpacket
		.src1_endofpacket   (rsp_demux_002_src1_endofpacket),               //          .endofpacket
		.src2_ready         (rsp_demux_002_src2_ready),                     //      src2.ready
		.src2_valid         (rsp_demux_002_src2_valid),                     //          .valid
		.src2_data          (rsp_demux_002_src2_data),                      //          .data
		.src2_channel       (rsp_demux_002_src2_channel),                   //          .channel
		.src2_startofpacket (rsp_demux_002_src2_startofpacket),             //          .startofpacket
		.src2_endofpacket   (rsp_demux_002_src2_endofpacket)                //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_0_rsp_demux_003 rsp_demux_003 (
		.clk                (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset              (msgdma_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_006_src_ready),                         //      sink.ready
		.sink_channel       (router_006_src_channel),                       //          .channel
		.sink_data          (router_006_src_data),                          //          .data
		.sink_startofpacket (router_006_src_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (router_006_src_endofpacket),                   //          .endofpacket
		.sink_valid         (router_006_src_valid),                         //          .valid
		.src0_ready         (rsp_demux_003_src0_ready),                     //      src0.ready
		.src0_valid         (rsp_demux_003_src0_valid),                     //          .valid
		.src0_data          (rsp_demux_003_src0_data),                      //          .data
		.src0_channel       (rsp_demux_003_src0_channel),                   //          .channel
		.src0_startofpacket (rsp_demux_003_src0_startofpacket),             //          .startofpacket
		.src0_endofpacket   (rsp_demux_003_src0_endofpacket),               //          .endofpacket
		.src1_ready         (rsp_demux_003_src1_ready),                     //      src1.ready
		.src1_valid         (rsp_demux_003_src1_valid),                     //          .valid
		.src1_data          (rsp_demux_003_src1_data),                      //          .data
		.src1_channel       (rsp_demux_003_src1_channel),                   //          .channel
		.src1_startofpacket (rsp_demux_003_src1_startofpacket),             //          .startofpacket
		.src1_endofpacket   (rsp_demux_003_src1_endofpacket)                //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_0_rsp_mux rsp_mux (
		.clk                 (pcie_hip_avmm_coreclkout_clk),                                         //       clk.clk
		.reset               (pcie_hip_avmm_RP_Master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                                                    //       src.ready
		.src_valid           (rsp_mux_src_valid),                                                    //          .valid
		.src_data            (rsp_mux_src_data),                                                     //          .data
		.src_channel         (rsp_mux_src_channel),                                                  //          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                                            //          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                                              //          .endofpacket
		.sink0_ready         (async_fifo_003_out_ready),                                             //     sink0.ready
		.sink0_valid         (async_fifo_003_out_valid),                                             //          .valid
		.sink0_channel       (async_fifo_003_out_channel),                                           //          .channel
		.sink0_data          (async_fifo_003_out_data),                                              //          .data
		.sink0_startofpacket (async_fifo_003_out_startofpacket),                                     //          .startofpacket
		.sink0_endofpacket   (async_fifo_003_out_endofpacket),                                       //          .endofpacket
		.sink1_ready         (async_fifo_004_out_ready),                                             //     sink1.ready
		.sink1_valid         (async_fifo_004_out_valid),                                             //          .valid
		.sink1_channel       (async_fifo_004_out_channel),                                           //          .channel
		.sink1_data          (async_fifo_004_out_data),                                              //          .data
		.sink1_startofpacket (async_fifo_004_out_startofpacket),                                     //          .startofpacket
		.sink1_endofpacket   (async_fifo_004_out_endofpacket),                                       //          .endofpacket
		.sink2_ready         (async_fifo_005_out_ready),                                             //     sink2.ready
		.sink2_valid         (async_fifo_005_out_valid),                                             //          .valid
		.sink2_channel       (async_fifo_005_out_channel),                                           //          .channel
		.sink2_data          (async_fifo_005_out_data),                                              //          .data
		.sink2_startofpacket (async_fifo_005_out_startofpacket),                                     //          .startofpacket
		.sink2_endofpacket   (async_fifo_005_out_endofpacket)                                        //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_0_rsp_mux rsp_mux_001 (
		.clk                 (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset               (msgdma_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_001_src_ready),                        //       src.ready
		.src_valid           (rsp_mux_001_src_valid),                        //          .valid
		.src_data            (rsp_mux_001_src_data),                         //          .data
		.src_channel         (rsp_mux_001_src_channel),                      //          .channel
		.src_startofpacket   (rsp_mux_001_src_startofpacket),                //          .startofpacket
		.src_endofpacket     (rsp_mux_001_src_endofpacket),                  //          .endofpacket
		.sink0_ready         (rsp_demux_001_src1_ready),                     //     sink0.ready
		.sink0_valid         (rsp_demux_001_src1_valid),                     //          .valid
		.sink0_channel       (rsp_demux_001_src1_channel),                   //          .channel
		.sink0_data          (rsp_demux_001_src1_data),                      //          .data
		.sink0_startofpacket (rsp_demux_001_src1_startofpacket),             //          .startofpacket
		.sink0_endofpacket   (rsp_demux_001_src1_endofpacket),               //          .endofpacket
		.sink1_ready         (rsp_demux_002_src1_ready),                     //     sink1.ready
		.sink1_valid         (rsp_demux_002_src1_valid),                     //          .valid
		.sink1_channel       (rsp_demux_002_src1_channel),                   //          .channel
		.sink1_data          (rsp_demux_002_src1_data),                      //          .data
		.sink1_startofpacket (rsp_demux_002_src1_startofpacket),             //          .startofpacket
		.sink1_endofpacket   (rsp_demux_002_src1_endofpacket),               //          .endofpacket
		.sink2_ready         (rsp_demux_003_src0_ready),                     //     sink2.ready
		.sink2_valid         (rsp_demux_003_src0_valid),                     //          .valid
		.sink2_channel       (rsp_demux_003_src0_channel),                   //          .channel
		.sink2_data          (rsp_demux_003_src0_data),                      //          .data
		.sink2_startofpacket (rsp_demux_003_src0_startofpacket),             //          .startofpacket
		.sink2_endofpacket   (rsp_demux_003_src0_endofpacket)                //          .endofpacket
	);

	soc_system_pcie_0_mm_interconnect_0_rsp_mux rsp_mux_002 (
		.clk                 (custom_reset_synchronizer_0_clock_out_clk),    //       clk.clk
		.reset               (msgdma_0_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_002_src_ready),                        //       src.ready
		.src_valid           (rsp_mux_002_src_valid),                        //          .valid
		.src_data            (rsp_mux_002_src_data),                         //          .data
		.src_channel         (rsp_mux_002_src_channel),                      //          .channel
		.src_startofpacket   (rsp_mux_002_src_startofpacket),                //          .startofpacket
		.src_endofpacket     (rsp_mux_002_src_endofpacket),                  //          .endofpacket
		.sink0_ready         (rsp_demux_001_src2_ready),                     //     sink0.ready
		.sink0_valid         (rsp_demux_001_src2_valid),                     //          .valid
		.sink0_channel       (rsp_demux_001_src2_channel),                   //          .channel
		.sink0_data          (rsp_demux_001_src2_data),                      //          .data
		.sink0_startofpacket (rsp_demux_001_src2_startofpacket),             //          .startofpacket
		.sink0_endofpacket   (rsp_demux_001_src2_endofpacket),               //          .endofpacket
		.sink1_ready         (rsp_demux_002_src2_ready),                     //     sink1.ready
		.sink1_valid         (rsp_demux_002_src2_valid),                     //          .valid
		.sink1_channel       (rsp_demux_002_src2_channel),                   //          .channel
		.sink1_data          (rsp_demux_002_src2_data),                      //          .data
		.sink1_startofpacket (rsp_demux_002_src2_startofpacket),             //          .startofpacket
		.sink1_endofpacket   (rsp_demux_002_src2_endofpacket),               //          .endofpacket
		.sink2_ready         (rsp_demux_003_src1_ready),                     //     sink2.ready
		.sink2_valid         (rsp_demux_003_src1_valid),                     //          .valid
		.sink2_channel       (rsp_demux_003_src1_channel),                   //          .channel
		.sink2_data          (rsp_demux_003_src1_data),                      //          .data
		.sink2_startofpacket (rsp_demux_003_src1_startofpacket),             //          .startofpacket
		.sink2_endofpacket   (rsp_demux_003_src1_endofpacket)                //          .endofpacket
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (67),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (83),
		.IN_PKT_BYTE_CNT_L             (74),
		.IN_PKT_TRANS_COMPRESSED_READ  (68),
		.IN_PKT_TRANS_WRITE            (70),
		.IN_PKT_BURSTWRAP_H            (84),
		.IN_PKT_BURSTWRAP_L            (84),
		.IN_PKT_BURST_SIZE_H           (87),
		.IN_PKT_BURST_SIZE_L           (85),
		.IN_PKT_RESPONSE_STATUS_H      (107),
		.IN_PKT_RESPONSE_STATUS_L      (106),
		.IN_PKT_TRANS_EXCLUSIVE        (73),
		.IN_PKT_BURST_TYPE_H           (89),
		.IN_PKT_BURST_TYPE_L           (88),
		.IN_PKT_ORI_BURST_SIZE_L       (108),
		.IN_PKT_ORI_BURST_SIZE_H       (110),
		.IN_ST_DATA_W                  (111),
		.OUT_PKT_ADDR_H                (103),
		.OUT_PKT_ADDR_L                (72),
		.OUT_PKT_DATA_H                (63),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (71),
		.OUT_PKT_BYTEEN_L              (64),
		.OUT_PKT_BYTE_CNT_H            (119),
		.OUT_PKT_BYTE_CNT_L            (110),
		.OUT_PKT_TRANS_COMPRESSED_READ (104),
		.OUT_PKT_BURST_SIZE_H          (123),
		.OUT_PKT_BURST_SIZE_L          (121),
		.OUT_PKT_RESPONSE_STATUS_H     (143),
		.OUT_PKT_RESPONSE_STATUS_L     (142),
		.OUT_PKT_TRANS_EXCLUSIVE       (109),
		.OUT_PKT_BURST_TYPE_H          (125),
		.OUT_PKT_BURST_TYPE_L          (124),
		.OUT_PKT_ORI_BURST_SIZE_L      (144),
		.OUT_PKT_ORI_BURST_SIZE_H      (146),
		.OUT_ST_DATA_W                 (147),
		.ST_CHANNEL_W                  (4),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (1),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0)
	) pb_rxm_2_msi_s0_rsp_width_adapter (
		.clk                  (custom_reset_synchronizer_0_clock_out_clk),           //       clk.clk
		.reset                (msgdma_0_reset_n_reset_bridge_in_reset_reset),        // clk_reset.reset
		.in_valid             (router_003_src_valid),                                //      sink.valid
		.in_channel           (router_003_src_channel),                              //          .channel
		.in_startofpacket     (router_003_src_startofpacket),                        //          .startofpacket
		.in_endofpacket       (router_003_src_endofpacket),                          //          .endofpacket
		.in_ready             (router_003_src_ready),                                //          .ready
		.in_data              (router_003_src_data),                                 //          .data
		.out_endofpacket      (pb_rxm_2_msi_s0_rsp_width_adapter_src_endofpacket),   //       src.endofpacket
		.out_data             (pb_rxm_2_msi_s0_rsp_width_adapter_src_data),          //          .data
		.out_channel          (pb_rxm_2_msi_s0_rsp_width_adapter_src_channel),       //          .channel
		.out_valid            (pb_rxm_2_msi_s0_rsp_width_adapter_src_valid),         //          .valid
		.out_ready            (pb_rxm_2_msi_s0_rsp_width_adapter_src_ready),         //          .ready
		.out_startofpacket    (pb_rxm_2_msi_s0_rsp_width_adapter_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                                               // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (103),
		.IN_PKT_ADDR_L                 (72),
		.IN_PKT_DATA_H                 (63),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (71),
		.IN_PKT_BYTEEN_L               (64),
		.IN_PKT_BYTE_CNT_H             (119),
		.IN_PKT_BYTE_CNT_L             (110),
		.IN_PKT_TRANS_COMPRESSED_READ  (104),
		.IN_PKT_TRANS_WRITE            (106),
		.IN_PKT_BURSTWRAP_H            (120),
		.IN_PKT_BURSTWRAP_L            (120),
		.IN_PKT_BURST_SIZE_H           (123),
		.IN_PKT_BURST_SIZE_L           (121),
		.IN_PKT_RESPONSE_STATUS_H      (143),
		.IN_PKT_RESPONSE_STATUS_L      (142),
		.IN_PKT_TRANS_EXCLUSIVE        (109),
		.IN_PKT_BURST_TYPE_H           (125),
		.IN_PKT_BURST_TYPE_L           (124),
		.IN_PKT_ORI_BURST_SIZE_L       (144),
		.IN_PKT_ORI_BURST_SIZE_H       (146),
		.IN_ST_DATA_W                  (147),
		.OUT_PKT_ADDR_H                (67),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (83),
		.OUT_PKT_BYTE_CNT_L            (74),
		.OUT_PKT_TRANS_COMPRESSED_READ (68),
		.OUT_PKT_BURST_SIZE_H          (87),
		.OUT_PKT_BURST_SIZE_L          (85),
		.OUT_PKT_RESPONSE_STATUS_H     (107),
		.OUT_PKT_RESPONSE_STATUS_L     (106),
		.OUT_PKT_TRANS_EXCLUSIVE       (73),
		.OUT_PKT_BURST_TYPE_H          (89),
		.OUT_PKT_BURST_TYPE_L          (88),
		.OUT_PKT_ORI_BURST_SIZE_L      (108),
		.OUT_PKT_ORI_BURST_SIZE_H      (110),
		.OUT_ST_DATA_W                 (111),
		.ST_CHANNEL_W                  (4),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (1),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0)
	) pb_rxm_2_msi_s0_cmd_width_adapter (
		.clk                  (custom_reset_synchronizer_0_clock_out_clk),           //       clk.clk
		.reset                (msgdma_0_reset_n_reset_bridge_in_reset_reset),        // clk_reset.reset
		.in_valid             (cmd_mux_src_valid),                                   //      sink.valid
		.in_channel           (cmd_mux_src_channel),                                 //          .channel
		.in_startofpacket     (cmd_mux_src_startofpacket),                           //          .startofpacket
		.in_endofpacket       (cmd_mux_src_endofpacket),                             //          .endofpacket
		.in_ready             (cmd_mux_src_ready),                                   //          .ready
		.in_data              (cmd_mux_src_data),                                    //          .data
		.out_endofpacket      (pb_rxm_2_msi_s0_cmd_width_adapter_src_endofpacket),   //       src.endofpacket
		.out_data             (pb_rxm_2_msi_s0_cmd_width_adapter_src_data),          //          .data
		.out_channel          (pb_rxm_2_msi_s0_cmd_width_adapter_src_channel),       //          .channel
		.out_valid            (pb_rxm_2_msi_s0_cmd_width_adapter_src_valid),         //          .valid
		.out_ready            (pb_rxm_2_msi_s0_cmd_width_adapter_src_ready),         //          .ready
		.out_startofpacket    (pb_rxm_2_msi_s0_cmd_width_adapter_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                                               // (terminated)
	);

	altera_avalon_dc_fifo #(
		.SYMBOLS_PER_BEAT   (1),
		.BITS_PER_SYMBOL    (147),
		.FIFO_DEPTH         (8),
		.CHANNEL_WIDTH      (4),
		.ERROR_WIDTH        (0),
		.USE_PACKETS        (1),
		.USE_IN_FILL_LEVEL  (0),
		.USE_OUT_FILL_LEVEL (0),
		.WR_SYNC_DEPTH      (3),
		.RD_SYNC_DEPTH      (3)
	) async_fifo (
		.in_clk            (pcie_hip_avmm_coreclkout_clk),                                          //        in_clk.clk
		.in_reset_n        (~pcie_hip_avmm_RP_Master_translator_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset_n
		.out_clk           (custom_reset_synchronizer_0_clock_out_clk),                             //       out_clk.clk
		.out_reset_n       (~msgdma_0_reset_n_reset_bridge_in_reset_reset),                         // out_clk_reset.reset_n
		.in_data           (cmd_demux_src0_data),                                                   //            in.data
		.in_valid          (cmd_demux_src0_valid),                                                  //              .valid
		.in_ready          (cmd_demux_src0_ready),                                                  //              .ready
		.in_startofpacket  (cmd_demux_src0_startofpacket),                                          //              .startofpacket
		.in_endofpacket    (cmd_demux_src0_endofpacket),                                            //              .endofpacket
		.in_channel        (cmd_demux_src0_channel),                                                //              .channel
		.out_data          (async_fifo_out_data),                                                   //           out.data
		.out_valid         (async_fifo_out_valid),                                                  //              .valid
		.out_ready         (async_fifo_out_ready),                                                  //              .ready
		.out_startofpacket (async_fifo_out_startofpacket),                                          //              .startofpacket
		.out_endofpacket   (async_fifo_out_endofpacket),                                            //              .endofpacket
		.out_channel       (async_fifo_out_channel),                                                //              .channel
		.in_csr_address    (1'b0),                                                                  //   (terminated)
		.in_csr_read       (1'b0),                                                                  //   (terminated)
		.in_csr_write      (1'b0),                                                                  //   (terminated)
		.in_csr_readdata   (),                                                                      //   (terminated)
		.in_csr_writedata  (32'b00000000000000000000000000000000),                                  //   (terminated)
		.out_csr_address   (1'b0),                                                                  //   (terminated)
		.out_csr_read      (1'b0),                                                                  //   (terminated)
		.out_csr_write     (1'b0),                                                                  //   (terminated)
		.out_csr_readdata  (),                                                                      //   (terminated)
		.out_csr_writedata (32'b00000000000000000000000000000000),                                  //   (terminated)
		.in_empty          (1'b0),                                                                  //   (terminated)
		.out_empty         (),                                                                      //   (terminated)
		.in_error          (1'b0),                                                                  //   (terminated)
		.out_error         (),                                                                      //   (terminated)
		.space_avail_data  ()                                                                       //   (terminated)
	);

	altera_avalon_dc_fifo #(
		.SYMBOLS_PER_BEAT   (1),
		.BITS_PER_SYMBOL    (147),
		.FIFO_DEPTH         (8),
		.CHANNEL_WIDTH      (4),
		.ERROR_WIDTH        (0),
		.USE_PACKETS        (1),
		.USE_IN_FILL_LEVEL  (0),
		.USE_OUT_FILL_LEVEL (0),
		.WR_SYNC_DEPTH      (3),
		.RD_SYNC_DEPTH      (3)
	) async_fifo_001 (
		.in_clk            (pcie_hip_avmm_coreclkout_clk),                                          //        in_clk.clk
		.in_reset_n        (~pcie_hip_avmm_RP_Master_translator_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset_n
		.out_clk           (custom_reset_synchronizer_0_clock_out_clk),                             //       out_clk.clk
		.out_reset_n       (~msgdma_0_reset_n_reset_bridge_in_reset_reset),                         // out_clk_reset.reset_n
		.in_data           (cmd_demux_src1_data),                                                   //            in.data
		.in_valid          (cmd_demux_src1_valid),                                                  //              .valid
		.in_ready          (cmd_demux_src1_ready),                                                  //              .ready
		.in_startofpacket  (cmd_demux_src1_startofpacket),                                          //              .startofpacket
		.in_endofpacket    (cmd_demux_src1_endofpacket),                                            //              .endofpacket
		.in_channel        (cmd_demux_src1_channel),                                                //              .channel
		.out_data          (async_fifo_001_out_data),                                               //           out.data
		.out_valid         (async_fifo_001_out_valid),                                              //              .valid
		.out_ready         (async_fifo_001_out_ready),                                              //              .ready
		.out_startofpacket (async_fifo_001_out_startofpacket),                                      //              .startofpacket
		.out_endofpacket   (async_fifo_001_out_endofpacket),                                        //              .endofpacket
		.out_channel       (async_fifo_001_out_channel),                                            //              .channel
		.in_csr_address    (1'b0),                                                                  //   (terminated)
		.in_csr_read       (1'b0),                                                                  //   (terminated)
		.in_csr_write      (1'b0),                                                                  //   (terminated)
		.in_csr_readdata   (),                                                                      //   (terminated)
		.in_csr_writedata  (32'b00000000000000000000000000000000),                                  //   (terminated)
		.out_csr_address   (1'b0),                                                                  //   (terminated)
		.out_csr_read      (1'b0),                                                                  //   (terminated)
		.out_csr_write     (1'b0),                                                                  //   (terminated)
		.out_csr_readdata  (),                                                                      //   (terminated)
		.out_csr_writedata (32'b00000000000000000000000000000000),                                  //   (terminated)
		.in_empty          (1'b0),                                                                  //   (terminated)
		.out_empty         (),                                                                      //   (terminated)
		.in_error          (1'b0),                                                                  //   (terminated)
		.out_error         (),                                                                      //   (terminated)
		.space_avail_data  ()                                                                       //   (terminated)
	);

	altera_avalon_dc_fifo #(
		.SYMBOLS_PER_BEAT   (1),
		.BITS_PER_SYMBOL    (147),
		.FIFO_DEPTH         (8),
		.CHANNEL_WIDTH      (4),
		.ERROR_WIDTH        (0),
		.USE_PACKETS        (1),
		.USE_IN_FILL_LEVEL  (0),
		.USE_OUT_FILL_LEVEL (0),
		.WR_SYNC_DEPTH      (3),
		.RD_SYNC_DEPTH      (3)
	) async_fifo_002 (
		.in_clk            (pcie_hip_avmm_coreclkout_clk),                                          //        in_clk.clk
		.in_reset_n        (~pcie_hip_avmm_RP_Master_translator_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset_n
		.out_clk           (custom_reset_synchronizer_0_clock_out_clk),                             //       out_clk.clk
		.out_reset_n       (~msgdma_0_reset_n_reset_bridge_in_reset_reset),                         // out_clk_reset.reset_n
		.in_data           (cmd_demux_src2_data),                                                   //            in.data
		.in_valid          (cmd_demux_src2_valid),                                                  //              .valid
		.in_ready          (cmd_demux_src2_ready),                                                  //              .ready
		.in_startofpacket  (cmd_demux_src2_startofpacket),                                          //              .startofpacket
		.in_endofpacket    (cmd_demux_src2_endofpacket),                                            //              .endofpacket
		.in_channel        (cmd_demux_src2_channel),                                                //              .channel
		.out_data          (async_fifo_002_out_data),                                               //           out.data
		.out_valid         (async_fifo_002_out_valid),                                              //              .valid
		.out_ready         (async_fifo_002_out_ready),                                              //              .ready
		.out_startofpacket (async_fifo_002_out_startofpacket),                                      //              .startofpacket
		.out_endofpacket   (async_fifo_002_out_endofpacket),                                        //              .endofpacket
		.out_channel       (async_fifo_002_out_channel),                                            //              .channel
		.in_csr_address    (1'b0),                                                                  //   (terminated)
		.in_csr_read       (1'b0),                                                                  //   (terminated)
		.in_csr_write      (1'b0),                                                                  //   (terminated)
		.in_csr_readdata   (),                                                                      //   (terminated)
		.in_csr_writedata  (32'b00000000000000000000000000000000),                                  //   (terminated)
		.out_csr_address   (1'b0),                                                                  //   (terminated)
		.out_csr_read      (1'b0),                                                                  //   (terminated)
		.out_csr_write     (1'b0),                                                                  //   (terminated)
		.out_csr_readdata  (),                                                                      //   (terminated)
		.out_csr_writedata (32'b00000000000000000000000000000000),                                  //   (terminated)
		.in_empty          (1'b0),                                                                  //   (terminated)
		.out_empty         (),                                                                      //   (terminated)
		.in_error          (1'b0),                                                                  //   (terminated)
		.out_error         (),                                                                      //   (terminated)
		.space_avail_data  ()                                                                       //   (terminated)
	);

	altera_avalon_dc_fifo #(
		.SYMBOLS_PER_BEAT   (1),
		.BITS_PER_SYMBOL    (147),
		.FIFO_DEPTH         (8),
		.CHANNEL_WIDTH      (4),
		.ERROR_WIDTH        (0),
		.USE_PACKETS        (1),
		.USE_IN_FILL_LEVEL  (0),
		.USE_OUT_FILL_LEVEL (0),
		.WR_SYNC_DEPTH      (3),
		.RD_SYNC_DEPTH      (3)
	) async_fifo_003 (
		.in_clk            (custom_reset_synchronizer_0_clock_out_clk),                             //        in_clk.clk
		.in_reset_n        (~msgdma_0_reset_n_reset_bridge_in_reset_reset),                         //  in_clk_reset.reset_n
		.out_clk           (pcie_hip_avmm_coreclkout_clk),                                          //       out_clk.clk
		.out_reset_n       (~pcie_hip_avmm_RP_Master_translator_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset_n
		.in_data           (rsp_demux_src0_data),                                                   //            in.data
		.in_valid          (rsp_demux_src0_valid),                                                  //              .valid
		.in_ready          (rsp_demux_src0_ready),                                                  //              .ready
		.in_startofpacket  (rsp_demux_src0_startofpacket),                                          //              .startofpacket
		.in_endofpacket    (rsp_demux_src0_endofpacket),                                            //              .endofpacket
		.in_channel        (rsp_demux_src0_channel),                                                //              .channel
		.out_data          (async_fifo_003_out_data),                                               //           out.data
		.out_valid         (async_fifo_003_out_valid),                                              //              .valid
		.out_ready         (async_fifo_003_out_ready),                                              //              .ready
		.out_startofpacket (async_fifo_003_out_startofpacket),                                      //              .startofpacket
		.out_endofpacket   (async_fifo_003_out_endofpacket),                                        //              .endofpacket
		.out_channel       (async_fifo_003_out_channel),                                            //              .channel
		.in_csr_address    (1'b0),                                                                  //   (terminated)
		.in_csr_read       (1'b0),                                                                  //   (terminated)
		.in_csr_write      (1'b0),                                                                  //   (terminated)
		.in_csr_readdata   (),                                                                      //   (terminated)
		.in_csr_writedata  (32'b00000000000000000000000000000000),                                  //   (terminated)
		.out_csr_address   (1'b0),                                                                  //   (terminated)
		.out_csr_read      (1'b0),                                                                  //   (terminated)
		.out_csr_write     (1'b0),                                                                  //   (terminated)
		.out_csr_readdata  (),                                                                      //   (terminated)
		.out_csr_writedata (32'b00000000000000000000000000000000),                                  //   (terminated)
		.in_empty          (1'b0),                                                                  //   (terminated)
		.out_empty         (),                                                                      //   (terminated)
		.in_error          (1'b0),                                                                  //   (terminated)
		.out_error         (),                                                                      //   (terminated)
		.space_avail_data  ()                                                                       //   (terminated)
	);

	altera_avalon_dc_fifo #(
		.SYMBOLS_PER_BEAT   (1),
		.BITS_PER_SYMBOL    (147),
		.FIFO_DEPTH         (8),
		.CHANNEL_WIDTH      (4),
		.ERROR_WIDTH        (0),
		.USE_PACKETS        (1),
		.USE_IN_FILL_LEVEL  (0),
		.USE_OUT_FILL_LEVEL (0),
		.WR_SYNC_DEPTH      (3),
		.RD_SYNC_DEPTH      (3)
	) async_fifo_004 (
		.in_clk            (custom_reset_synchronizer_0_clock_out_clk),                             //        in_clk.clk
		.in_reset_n        (~msgdma_0_reset_n_reset_bridge_in_reset_reset),                         //  in_clk_reset.reset_n
		.out_clk           (pcie_hip_avmm_coreclkout_clk),                                          //       out_clk.clk
		.out_reset_n       (~pcie_hip_avmm_RP_Master_translator_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset_n
		.in_data           (rsp_demux_001_src0_data),                                               //            in.data
		.in_valid          (rsp_demux_001_src0_valid),                                              //              .valid
		.in_ready          (rsp_demux_001_src0_ready),                                              //              .ready
		.in_startofpacket  (rsp_demux_001_src0_startofpacket),                                      //              .startofpacket
		.in_endofpacket    (rsp_demux_001_src0_endofpacket),                                        //              .endofpacket
		.in_channel        (rsp_demux_001_src0_channel),                                            //              .channel
		.out_data          (async_fifo_004_out_data),                                               //           out.data
		.out_valid         (async_fifo_004_out_valid),                                              //              .valid
		.out_ready         (async_fifo_004_out_ready),                                              //              .ready
		.out_startofpacket (async_fifo_004_out_startofpacket),                                      //              .startofpacket
		.out_endofpacket   (async_fifo_004_out_endofpacket),                                        //              .endofpacket
		.out_channel       (async_fifo_004_out_channel),                                            //              .channel
		.in_csr_address    (1'b0),                                                                  //   (terminated)
		.in_csr_read       (1'b0),                                                                  //   (terminated)
		.in_csr_write      (1'b0),                                                                  //   (terminated)
		.in_csr_readdata   (),                                                                      //   (terminated)
		.in_csr_writedata  (32'b00000000000000000000000000000000),                                  //   (terminated)
		.out_csr_address   (1'b0),                                                                  //   (terminated)
		.out_csr_read      (1'b0),                                                                  //   (terminated)
		.out_csr_write     (1'b0),                                                                  //   (terminated)
		.out_csr_readdata  (),                                                                      //   (terminated)
		.out_csr_writedata (32'b00000000000000000000000000000000),                                  //   (terminated)
		.in_empty          (1'b0),                                                                  //   (terminated)
		.out_empty         (),                                                                      //   (terminated)
		.in_error          (1'b0),                                                                  //   (terminated)
		.out_error         (),                                                                      //   (terminated)
		.space_avail_data  ()                                                                       //   (terminated)
	);

	altera_avalon_dc_fifo #(
		.SYMBOLS_PER_BEAT   (1),
		.BITS_PER_SYMBOL    (147),
		.FIFO_DEPTH         (8),
		.CHANNEL_WIDTH      (4),
		.ERROR_WIDTH        (0),
		.USE_PACKETS        (1),
		.USE_IN_FILL_LEVEL  (0),
		.USE_OUT_FILL_LEVEL (0),
		.WR_SYNC_DEPTH      (3),
		.RD_SYNC_DEPTH      (3)
	) async_fifo_005 (
		.in_clk            (custom_reset_synchronizer_0_clock_out_clk),                             //        in_clk.clk
		.in_reset_n        (~msgdma_0_reset_n_reset_bridge_in_reset_reset),                         //  in_clk_reset.reset_n
		.out_clk           (pcie_hip_avmm_coreclkout_clk),                                          //       out_clk.clk
		.out_reset_n       (~pcie_hip_avmm_RP_Master_translator_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset_n
		.in_data           (rsp_demux_002_src0_data),                                               //            in.data
		.in_valid          (rsp_demux_002_src0_valid),                                              //              .valid
		.in_ready          (rsp_demux_002_src0_ready),                                              //              .ready
		.in_startofpacket  (rsp_demux_002_src0_startofpacket),                                      //              .startofpacket
		.in_endofpacket    (rsp_demux_002_src0_endofpacket),                                        //              .endofpacket
		.in_channel        (rsp_demux_002_src0_channel),                                            //              .channel
		.out_data          (async_fifo_005_out_data),                                               //           out.data
		.out_valid         (async_fifo_005_out_valid),                                              //              .valid
		.out_ready         (async_fifo_005_out_ready),                                              //              .ready
		.out_startofpacket (async_fifo_005_out_startofpacket),                                      //              .startofpacket
		.out_endofpacket   (async_fifo_005_out_endofpacket),                                        //              .endofpacket
		.out_channel       (async_fifo_005_out_channel),                                            //              .channel
		.in_csr_address    (1'b0),                                                                  //   (terminated)
		.in_csr_read       (1'b0),                                                                  //   (terminated)
		.in_csr_write      (1'b0),                                                                  //   (terminated)
		.in_csr_readdata   (),                                                                      //   (terminated)
		.in_csr_writedata  (32'b00000000000000000000000000000000),                                  //   (terminated)
		.out_csr_address   (1'b0),                                                                  //   (terminated)
		.out_csr_read      (1'b0),                                                                  //   (terminated)
		.out_csr_write     (1'b0),                                                                  //   (terminated)
		.out_csr_readdata  (),                                                                      //   (terminated)
		.out_csr_writedata (32'b00000000000000000000000000000000),                                  //   (terminated)
		.in_empty          (1'b0),                                                                  //   (terminated)
		.out_empty         (),                                                                      //   (terminated)
		.in_error          (1'b0),                                                                  //   (terminated)
		.out_error         (),                                                                      //   (terminated)
		.space_avail_data  ()                                                                       //   (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (147),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) limiter_pipeline (
		.clk               (pcie_hip_avmm_coreclkout_clk),                                         //       cr0.clk
		.reset             (pcie_hip_avmm_RP_Master_translator_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (rsp_mux_src_ready),                                                    //     sink0.ready
		.in_valid          (rsp_mux_src_valid),                                                    //          .valid
		.in_startofpacket  (rsp_mux_src_startofpacket),                                            //          .startofpacket
		.in_endofpacket    (rsp_mux_src_endofpacket),                                              //          .endofpacket
		.in_data           (rsp_mux_src_data),                                                     //          .data
		.in_channel        (rsp_mux_src_channel),                                                  //          .channel
		.out_ready         (limiter_pipeline_source0_ready),                                       //   source0.ready
		.out_valid         (limiter_pipeline_source0_valid),                                       //          .valid
		.out_startofpacket (limiter_pipeline_source0_startofpacket),                               //          .startofpacket
		.out_endofpacket   (limiter_pipeline_source0_endofpacket),                                 //          .endofpacket
		.out_data          (limiter_pipeline_source0_data),                                        //          .data
		.out_channel       (limiter_pipeline_source0_channel),                                     //          .channel
		.in_empty          (1'b0),                                                                 // (terminated)
		.out_empty         (),                                                                     // (terminated)
		.out_error         (),                                                                     // (terminated)
		.in_error          (1'b0)                                                                  // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (147),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) limiter_pipeline_001 (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),    //       cr0.clk
		.reset             (msgdma_0_reset_n_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (rsp_mux_001_src_ready),                        //     sink0.ready
		.in_valid          (rsp_mux_001_src_valid),                        //          .valid
		.in_startofpacket  (rsp_mux_001_src_startofpacket),                //          .startofpacket
		.in_endofpacket    (rsp_mux_001_src_endofpacket),                  //          .endofpacket
		.in_data           (rsp_mux_001_src_data),                         //          .data
		.in_channel        (rsp_mux_001_src_channel),                      //          .channel
		.out_ready         (limiter_pipeline_001_source0_ready),           //   source0.ready
		.out_valid         (limiter_pipeline_001_source0_valid),           //          .valid
		.out_startofpacket (limiter_pipeline_001_source0_startofpacket),   //          .startofpacket
		.out_endofpacket   (limiter_pipeline_001_source0_endofpacket),     //          .endofpacket
		.out_data          (limiter_pipeline_001_source0_data),            //          .data
		.out_channel       (limiter_pipeline_001_source0_channel),         //          .channel
		.in_empty          (1'b0),                                         // (terminated)
		.out_empty         (),                                             // (terminated)
		.out_error         (),                                             // (terminated)
		.in_error          (1'b0)                                          // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (111),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),           //       cr0.clk
		.reset             (msgdma_0_reset_n_reset_bridge_in_reset_reset),        // cr0_reset.reset
		.in_ready          (pb_rxm_2_msi_s0_burst_adapter_source0_ready),         //     sink0.ready
		.in_valid          (pb_rxm_2_msi_s0_burst_adapter_source0_valid),         //          .valid
		.in_startofpacket  (pb_rxm_2_msi_s0_burst_adapter_source0_startofpacket), //          .startofpacket
		.in_endofpacket    (pb_rxm_2_msi_s0_burst_adapter_source0_endofpacket),   //          .endofpacket
		.in_data           (pb_rxm_2_msi_s0_burst_adapter_source0_data),          //          .data
		.in_channel        (pb_rxm_2_msi_s0_burst_adapter_source0_channel),       //          .channel
		.out_ready         (agent_pipeline_source0_ready),                        //   source0.ready
		.out_valid         (agent_pipeline_source0_valid),                        //          .valid
		.out_startofpacket (agent_pipeline_source0_startofpacket),                //          .startofpacket
		.out_endofpacket   (agent_pipeline_source0_endofpacket),                  //          .endofpacket
		.out_data          (agent_pipeline_source0_data),                         //          .data
		.out_channel       (agent_pipeline_source0_channel),                      //          .channel
		.in_empty          (1'b0),                                                // (terminated)
		.out_empty         (),                                                    // (terminated)
		.out_error         (),                                                    // (terminated)
		.in_error          (1'b0)                                                 // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (111),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_001 (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),    //       cr0.clk
		.reset             (msgdma_0_reset_n_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (pb_rxm_2_msi_s0_agent_rp_ready),               //     sink0.ready
		.in_valid          (pb_rxm_2_msi_s0_agent_rp_valid),               //          .valid
		.in_startofpacket  (pb_rxm_2_msi_s0_agent_rp_startofpacket),       //          .startofpacket
		.in_endofpacket    (pb_rxm_2_msi_s0_agent_rp_endofpacket),         //          .endofpacket
		.in_data           (pb_rxm_2_msi_s0_agent_rp_data),                //          .data
		.out_ready         (agent_pipeline_001_source0_ready),             //   source0.ready
		.out_valid         (agent_pipeline_001_source0_valid),             //          .valid
		.out_startofpacket (agent_pipeline_001_source0_startofpacket),     //          .startofpacket
		.out_endofpacket   (agent_pipeline_001_source0_endofpacket),       //          .endofpacket
		.out_data          (agent_pipeline_001_source0_data),              //          .data
		.in_empty          (1'b0),                                         // (terminated)
		.out_empty         (),                                             // (terminated)
		.out_error         (),                                             // (terminated)
		.in_error          (1'b0),                                         // (terminated)
		.out_channel       (),                                             // (terminated)
		.in_channel        (1'b0)                                          // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (147),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_002 (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),    //       cr0.clk
		.reset             (msgdma_0_reset_n_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (cmd_mux_001_src_ready),                        //     sink0.ready
		.in_valid          (cmd_mux_001_src_valid),                        //          .valid
		.in_startofpacket  (cmd_mux_001_src_startofpacket),                //          .startofpacket
		.in_endofpacket    (cmd_mux_001_src_endofpacket),                  //          .endofpacket
		.in_data           (cmd_mux_001_src_data),                         //          .data
		.in_channel        (cmd_mux_001_src_channel),                      //          .channel
		.out_ready         (agent_pipeline_002_source0_ready),             //   source0.ready
		.out_valid         (agent_pipeline_002_source0_valid),             //          .valid
		.out_startofpacket (agent_pipeline_002_source0_startofpacket),     //          .startofpacket
		.out_endofpacket   (agent_pipeline_002_source0_endofpacket),       //          .endofpacket
		.out_data          (agent_pipeline_002_source0_data),              //          .data
		.out_channel       (agent_pipeline_002_source0_channel),           //          .channel
		.in_empty          (1'b0),                                         // (terminated)
		.out_empty         (),                                             // (terminated)
		.out_error         (),                                             // (terminated)
		.in_error          (1'b0)                                          // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (147),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_003 (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),    //       cr0.clk
		.reset             (msgdma_0_reset_n_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (pb_2_ocm_s0_agent_rp_ready),                   //     sink0.ready
		.in_valid          (pb_2_ocm_s0_agent_rp_valid),                   //          .valid
		.in_startofpacket  (pb_2_ocm_s0_agent_rp_startofpacket),           //          .startofpacket
		.in_endofpacket    (pb_2_ocm_s0_agent_rp_endofpacket),             //          .endofpacket
		.in_data           (pb_2_ocm_s0_agent_rp_data),                    //          .data
		.out_ready         (agent_pipeline_003_source0_ready),             //   source0.ready
		.out_valid         (agent_pipeline_003_source0_valid),             //          .valid
		.out_startofpacket (agent_pipeline_003_source0_startofpacket),     //          .startofpacket
		.out_endofpacket   (agent_pipeline_003_source0_endofpacket),       //          .endofpacket
		.out_data          (agent_pipeline_003_source0_data),              //          .data
		.in_empty          (1'b0),                                         // (terminated)
		.out_empty         (),                                             // (terminated)
		.out_error         (),                                             // (terminated)
		.in_error          (1'b0),                                         // (terminated)
		.out_channel       (),                                             // (terminated)
		.in_channel        (1'b0)                                          // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (147),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_004 (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),    //       cr0.clk
		.reset             (msgdma_0_reset_n_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (pb_f2sdram_s0_agent_rp_ready),                 //     sink0.ready
		.in_valid          (pb_f2sdram_s0_agent_rp_valid),                 //          .valid
		.in_startofpacket  (pb_f2sdram_s0_agent_rp_startofpacket),         //          .startofpacket
		.in_endofpacket    (pb_f2sdram_s0_agent_rp_endofpacket),           //          .endofpacket
		.in_data           (pb_f2sdram_s0_agent_rp_data),                  //          .data
		.out_ready         (agent_pipeline_004_source0_ready),             //   source0.ready
		.out_valid         (agent_pipeline_004_source0_valid),             //          .valid
		.out_startofpacket (agent_pipeline_004_source0_startofpacket),     //          .startofpacket
		.out_endofpacket   (agent_pipeline_004_source0_endofpacket),       //          .endofpacket
		.out_data          (agent_pipeline_004_source0_data),              //          .data
		.in_empty          (1'b0),                                         // (terminated)
		.out_empty         (),                                             // (terminated)
		.out_error         (),                                             // (terminated)
		.in_error          (1'b0),                                         // (terminated)
		.out_channel       (),                                             // (terminated)
		.in_channel        (1'b0)                                          // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (147),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_005 (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),    //       cr0.clk
		.reset             (msgdma_0_reset_n_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (cmd_mux_003_src_ready),                        //     sink0.ready
		.in_valid          (cmd_mux_003_src_valid),                        //          .valid
		.in_startofpacket  (cmd_mux_003_src_startofpacket),                //          .startofpacket
		.in_endofpacket    (cmd_mux_003_src_endofpacket),                  //          .endofpacket
		.in_data           (cmd_mux_003_src_data),                         //          .data
		.in_channel        (cmd_mux_003_src_channel),                      //          .channel
		.out_ready         (agent_pipeline_005_source0_ready),             //   source0.ready
		.out_valid         (agent_pipeline_005_source0_valid),             //          .valid
		.out_startofpacket (agent_pipeline_005_source0_startofpacket),     //          .startofpacket
		.out_endofpacket   (agent_pipeline_005_source0_endofpacket),       //          .endofpacket
		.out_data          (agent_pipeline_005_source0_data),              //          .data
		.out_channel       (agent_pipeline_005_source0_channel),           //          .channel
		.in_empty          (1'b0),                                         // (terminated)
		.out_empty         (),                                             // (terminated)
		.out_error         (),                                             // (terminated)
		.in_error          (1'b0)                                          // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (147),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) agent_pipeline_006 (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),    //       cr0.clk
		.reset             (msgdma_0_reset_n_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (pb_msgdma_2_txs_s0_agent_rp_ready),            //     sink0.ready
		.in_valid          (pb_msgdma_2_txs_s0_agent_rp_valid),            //          .valid
		.in_startofpacket  (pb_msgdma_2_txs_s0_agent_rp_startofpacket),    //          .startofpacket
		.in_endofpacket    (pb_msgdma_2_txs_s0_agent_rp_endofpacket),      //          .endofpacket
		.in_data           (pb_msgdma_2_txs_s0_agent_rp_data),             //          .data
		.out_ready         (agent_pipeline_006_source0_ready),             //   source0.ready
		.out_valid         (agent_pipeline_006_source0_valid),             //          .valid
		.out_startofpacket (agent_pipeline_006_source0_startofpacket),     //          .startofpacket
		.out_endofpacket   (agent_pipeline_006_source0_endofpacket),       //          .endofpacket
		.out_data          (agent_pipeline_006_source0_data),              //          .data
		.in_empty          (1'b0),                                         // (terminated)
		.out_empty         (),                                             // (terminated)
		.out_error         (),                                             // (terminated)
		.in_error          (1'b0),                                         // (terminated)
		.out_channel       (),                                             // (terminated)
		.in_channel        (1'b0)                                          // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (147),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) pipeline_stage (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),    //       cr0.clk
		.reset             (msgdma_0_reset_n_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (cmd_demux_002_src0_ready),                     //     sink0.ready
		.in_valid          (cmd_demux_002_src0_valid),                     //          .valid
		.in_startofpacket  (cmd_demux_002_src0_startofpacket),             //          .startofpacket
		.in_endofpacket    (cmd_demux_002_src0_endofpacket),               //          .endofpacket
		.in_data           (cmd_demux_002_src0_data),                      //          .data
		.in_channel        (cmd_demux_002_src0_channel),                   //          .channel
		.out_ready         (pipeline_stage_source0_ready),                 //   source0.ready
		.out_valid         (pipeline_stage_source0_valid),                 //          .valid
		.out_startofpacket (pipeline_stage_source0_startofpacket),         //          .startofpacket
		.out_endofpacket   (pipeline_stage_source0_endofpacket),           //          .endofpacket
		.out_data          (pipeline_stage_source0_data),                  //          .data
		.out_channel       (pipeline_stage_source0_channel),               //          .channel
		.in_empty          (1'b0),                                         // (terminated)
		.out_empty         (),                                             // (terminated)
		.out_error         (),                                             // (terminated)
		.in_error          (1'b0)                                          // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (147),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) pipeline_stage_001 (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),    //       cr0.clk
		.reset             (msgdma_0_reset_n_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (cmd_mux_002_src_ready),                        //     sink0.ready
		.in_valid          (cmd_mux_002_src_valid),                        //          .valid
		.in_startofpacket  (cmd_mux_002_src_startofpacket),                //          .startofpacket
		.in_endofpacket    (cmd_mux_002_src_endofpacket),                  //          .endofpacket
		.in_data           (cmd_mux_002_src_data),                         //          .data
		.in_channel        (cmd_mux_002_src_channel),                      //          .channel
		.out_ready         (pipeline_stage_001_source0_ready),             //   source0.ready
		.out_valid         (pipeline_stage_001_source0_valid),             //          .valid
		.out_startofpacket (pipeline_stage_001_source0_startofpacket),     //          .startofpacket
		.out_endofpacket   (pipeline_stage_001_source0_endofpacket),       //          .endofpacket
		.out_data          (pipeline_stage_001_source0_data),              //          .data
		.out_channel       (pipeline_stage_001_source0_channel),           //          .channel
		.in_empty          (1'b0),                                         // (terminated)
		.out_empty         (),                                             // (terminated)
		.out_error         (),                                             // (terminated)
		.in_error          (1'b0)                                          // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (147),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) pipeline_stage_002 (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),    //       cr0.clk
		.reset             (msgdma_0_reset_n_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (msgdma_0_mm_read_agent_cp_ready),              //     sink0.ready
		.in_valid          (msgdma_0_mm_read_agent_cp_valid),              //          .valid
		.in_startofpacket  (msgdma_0_mm_read_agent_cp_startofpacket),      //          .startofpacket
		.in_endofpacket    (msgdma_0_mm_read_agent_cp_endofpacket),        //          .endofpacket
		.in_data           (msgdma_0_mm_read_agent_cp_data),               //          .data
		.out_ready         (pipeline_stage_002_source0_ready),             //   source0.ready
		.out_valid         (pipeline_stage_002_source0_valid),             //          .valid
		.out_startofpacket (pipeline_stage_002_source0_startofpacket),     //          .startofpacket
		.out_endofpacket   (pipeline_stage_002_source0_endofpacket),       //          .endofpacket
		.out_data          (pipeline_stage_002_source0_data),              //          .data
		.in_empty          (1'b0),                                         // (terminated)
		.out_empty         (),                                             // (terminated)
		.out_error         (),                                             // (terminated)
		.in_error          (1'b0),                                         // (terminated)
		.out_channel       (),                                             // (terminated)
		.in_channel        (1'b0)                                          // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (147),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) pipeline_stage_003 (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),      //       cr0.clk
		.reset             (msgdma_0_reset_n_reset_bridge_in_reset_reset),   // cr0_reset.reset
		.in_ready          (msgdma_0_mm_read_limiter_cmd_src_ready),         //     sink0.ready
		.in_valid          (msgdma_0_mm_read_limiter_cmd_src_valid),         //          .valid
		.in_startofpacket  (msgdma_0_mm_read_limiter_cmd_src_startofpacket), //          .startofpacket
		.in_endofpacket    (msgdma_0_mm_read_limiter_cmd_src_endofpacket),   //          .endofpacket
		.in_data           (msgdma_0_mm_read_limiter_cmd_src_data),          //          .data
		.in_channel        (msgdma_0_mm_read_limiter_cmd_src_channel),       //          .channel
		.out_ready         (pipeline_stage_003_source0_ready),               //   source0.ready
		.out_valid         (pipeline_stage_003_source0_valid),               //          .valid
		.out_startofpacket (pipeline_stage_003_source0_startofpacket),       //          .startofpacket
		.out_endofpacket   (pipeline_stage_003_source0_endofpacket),         //          .endofpacket
		.out_data          (pipeline_stage_003_source0_data),                //          .data
		.out_channel       (pipeline_stage_003_source0_channel),             //          .channel
		.in_empty          (1'b0),                                           // (terminated)
		.out_empty         (),                                               // (terminated)
		.out_error         (),                                               // (terminated)
		.in_error          (1'b0)                                            // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (147),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) pipeline_stage_004 (
		.clk               (custom_reset_synchronizer_0_clock_out_clk),    //       cr0.clk
		.reset             (msgdma_0_reset_n_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (msgdma_0_mm_write_agent_cp_ready),             //     sink0.ready
		.in_valid          (msgdma_0_mm_write_agent_cp_valid),             //          .valid
		.in_startofpacket  (msgdma_0_mm_write_agent_cp_startofpacket),     //          .startofpacket
		.in_endofpacket    (msgdma_0_mm_write_agent_cp_endofpacket),       //          .endofpacket
		.in_data           (msgdma_0_mm_write_agent_cp_data),              //          .data
		.out_ready         (pipeline_stage_004_source0_ready),             //   source0.ready
		.out_valid         (pipeline_stage_004_source0_valid),             //          .valid
		.out_startofpacket (pipeline_stage_004_source0_startofpacket),     //          .startofpacket
		.out_endofpacket   (pipeline_stage_004_source0_endofpacket),       //          .endofpacket
		.out_data          (pipeline_stage_004_source0_data),              //          .data
		.in_empty          (1'b0),                                         // (terminated)
		.out_empty         (),                                             // (terminated)
		.out_error         (),                                             // (terminated)
		.in_error          (1'b0),                                         // (terminated)
		.out_channel       (),                                             // (terminated)
		.in_channel        (1'b0)                                          // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (147),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) pipeline_stage_005 (
		.clk               (pcie_hip_avmm_coreclkout_clk),                                         //       cr0.clk
		.reset             (pcie_hip_avmm_RP_Master_translator_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (pcie_hip_avmm_rp_master_agent_cp_ready),                               //     sink0.ready
		.in_valid          (pcie_hip_avmm_rp_master_agent_cp_valid),                               //          .valid
		.in_startofpacket  (pcie_hip_avmm_rp_master_agent_cp_startofpacket),                       //          .startofpacket
		.in_endofpacket    (pcie_hip_avmm_rp_master_agent_cp_endofpacket),                         //          .endofpacket
		.in_data           (pcie_hip_avmm_rp_master_agent_cp_data),                                //          .data
		.out_ready         (pipeline_stage_005_source0_ready),                                     //   source0.ready
		.out_valid         (pipeline_stage_005_source0_valid),                                     //          .valid
		.out_startofpacket (pipeline_stage_005_source0_startofpacket),                             //          .startofpacket
		.out_endofpacket   (pipeline_stage_005_source0_endofpacket),                               //          .endofpacket
		.out_data          (pipeline_stage_005_source0_data),                                      //          .data
		.in_empty          (1'b0),                                                                 // (terminated)
		.out_empty         (),                                                                     // (terminated)
		.out_error         (),                                                                     // (terminated)
		.in_error          (1'b0),                                                                 // (terminated)
		.out_channel       (),                                                                     // (terminated)
		.in_channel        (1'b0)                                                                  // (terminated)
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (147),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (4),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1)
	) pipeline_stage_006 (
		.clk               (pcie_hip_avmm_coreclkout_clk),                                         //       cr0.clk
		.reset             (pcie_hip_avmm_RP_Master_translator_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.in_ready          (pcie_hip_avmm_rp_master_limiter_cmd_src_ready),                        //     sink0.ready
		.in_valid          (pcie_hip_avmm_rp_master_limiter_cmd_src_valid),                        //          .valid
		.in_startofpacket  (pcie_hip_avmm_rp_master_limiter_cmd_src_startofpacket),                //          .startofpacket
		.in_endofpacket    (pcie_hip_avmm_rp_master_limiter_cmd_src_endofpacket),                  //          .endofpacket
		.in_data           (pcie_hip_avmm_rp_master_limiter_cmd_src_data),                         //          .data
		.in_channel        (pcie_hip_avmm_rp_master_limiter_cmd_src_channel),                      //          .channel
		.out_ready         (pipeline_stage_006_source0_ready),                                     //   source0.ready
		.out_valid         (pipeline_stage_006_source0_valid),                                     //          .valid
		.out_startofpacket (pipeline_stage_006_source0_startofpacket),                             //          .startofpacket
		.out_endofpacket   (pipeline_stage_006_source0_endofpacket),                               //          .endofpacket
		.out_data          (pipeline_stage_006_source0_data),                                      //          .data
		.out_channel       (pipeline_stage_006_source0_channel),                                   //          .channel
		.in_empty          (1'b0),                                                                 // (terminated)
		.out_empty         (),                                                                     // (terminated)
		.out_error         (),                                                                     // (terminated)
		.in_error          (1'b0)                                                                  // (terminated)
	);

	soc_system_mm_interconnect_2_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter (
		.in_clk_0_clk   (custom_reset_synchronizer_0_clock_out_clk),    // in_clk_0.clk
		.in_rst_0_reset (msgdma_0_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (pb_rxm_2_msi_s0_agent_rdata_fifo_out_data),    //     in_0.data
		.in_0_valid     (pb_rxm_2_msi_s0_agent_rdata_fifo_out_valid),   //         .valid
		.in_0_ready     (pb_rxm_2_msi_s0_agent_rdata_fifo_out_ready),   //         .ready
		.out_0_data     (avalon_st_adapter_out_0_data),                 //    out_0.data
		.out_0_valid    (avalon_st_adapter_out_0_valid),                //         .valid
		.out_0_ready    (avalon_st_adapter_out_0_ready),                //         .ready
		.out_0_error    (avalon_st_adapter_out_0_error)                 //         .error
	);

	soc_system_mm_interconnect_1_avalon_st_adapter #(
		.inBitsPerSymbol (66),
		.inUsePackets    (0),
		.inDataWidth     (66),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (66),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_001 (
		.in_clk_0_clk   (custom_reset_synchronizer_0_clock_out_clk),    // in_clk_0.clk
		.in_rst_0_reset (msgdma_0_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (pb_2_ocm_s0_agent_rdata_fifo_out_data),        //     in_0.data
		.in_0_valid     (pb_2_ocm_s0_agent_rdata_fifo_out_valid),       //         .valid
		.in_0_ready     (pb_2_ocm_s0_agent_rdata_fifo_out_ready),       //         .ready
		.out_0_data     (avalon_st_adapter_001_out_0_data),             //    out_0.data
		.out_0_valid    (avalon_st_adapter_001_out_0_valid),            //         .valid
		.out_0_ready    (avalon_st_adapter_001_out_0_ready),            //         .ready
		.out_0_error    (avalon_st_adapter_001_out_0_error)             //         .error
	);

	soc_system_mm_interconnect_1_avalon_st_adapter #(
		.inBitsPerSymbol (66),
		.inUsePackets    (0),
		.inDataWidth     (66),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (66),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_002 (
		.in_clk_0_clk   (custom_reset_synchronizer_0_clock_out_clk),    // in_clk_0.clk
		.in_rst_0_reset (msgdma_0_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (pb_f2sdram_s0_agent_rdata_fifo_out_data),      //     in_0.data
		.in_0_valid     (pb_f2sdram_s0_agent_rdata_fifo_out_valid),     //         .valid
		.in_0_ready     (pb_f2sdram_s0_agent_rdata_fifo_out_ready),     //         .ready
		.out_0_data     (avalon_st_adapter_002_out_0_data),             //    out_0.data
		.out_0_valid    (avalon_st_adapter_002_out_0_valid),            //         .valid
		.out_0_ready    (avalon_st_adapter_002_out_0_ready),            //         .ready
		.out_0_error    (avalon_st_adapter_002_out_0_error)             //         .error
	);

	soc_system_mm_interconnect_1_avalon_st_adapter #(
		.inBitsPerSymbol (66),
		.inUsePackets    (0),
		.inDataWidth     (66),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (66),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_003 (
		.in_clk_0_clk   (custom_reset_synchronizer_0_clock_out_clk),     // in_clk_0.clk
		.in_rst_0_reset (msgdma_0_reset_n_reset_bridge_in_reset_reset),  // in_rst_0.reset
		.in_0_data      (pb_msgdma_2_txs_s0_agent_rdata_fifo_out_data),  //     in_0.data
		.in_0_valid     (pb_msgdma_2_txs_s0_agent_rdata_fifo_out_valid), //         .valid
		.in_0_ready     (pb_msgdma_2_txs_s0_agent_rdata_fifo_out_ready), //         .ready
		.out_0_data     (avalon_st_adapter_003_out_0_data),              //    out_0.data
		.out_0_valid    (avalon_st_adapter_003_out_0_valid),             //         .valid
		.out_0_ready    (avalon_st_adapter_003_out_0_ready),             //         .ready
		.out_0_error    (avalon_st_adapter_003_out_0_error)              //         .error
	);

endmodule
